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Design, Automation & Test in Europe Conference & Exhibition (2004)
Paris, France
Feb. 16, 2004 to Feb. 20, 2004
ISSN: 1530-1591
ISBN: 0-7695-2085-5
pp: 21364
Anuradha Agarwal , University of Cincinnati
Hemanth Sampath , University of Cincinnati
Veena Yelamanchili , University of Cincinnati
Ranga Vemuri , University of Cincinnati
This paper presents efficient and accurate techniques for modeling parasitic capacitances in analog CMOS circuits. A layout aware synthesis .ow using these parasitic models has been proposed. The fast parasitic estimation process replaces the time consuming steps of layout generation and extraction during synthesis. Results indicate that these models are extremely fast and accurate.

R. Vemuri, V. Yelamanchili, A. Agarwal and H. Sampath, "Accurate Estimation of Parasitic Capacitances in Analog Circuits," Design, Automation & Test in Europe Conference & Exhibition(DATE), Paris, France, 2004, pp. 21364.
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