The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2004)
Paris, France
Feb. 16, 2004 to Feb. 20, 2004
ISSN: 1530-1591
ISBN: 0-7695-2085-5
TABLE OF CONTENTS

Foreword (PDF)

pp. xxvii,xxviii
Plenary — Keynote Session
1A: Architectural-Level Power Management

null (PDF)

pp. null

Hybrid Architectural Dynamic Thermal Management (Abstract)

Kevin Skadron , University of Virginia
pp. 10010

Value-Conscious Cache: Simple Technique for Reducing Cache Access Power (Abstract)

Yen-Jen Chang , National ChungHsing University
Chia-Lin Yang , National Taiwan University
Feipei Lai , National Taiwan University
pp. 10016

State-Preserving vs. Non-State-Preserving Leakage Control in Caches (Abstract)

Yingmin Li , University of Virginia
Dharmesh Parikh , University of Virginia
Yan Zhang , University of Virginia
Karthik Sankaranarayanan , University of Virginia
Mircea Stan , University of Virginia
Kevin Skadron , University of Virginia
pp. 10022
1B: Formal Verification Using Functional and Structural Information

null (PDF)

pp. null

Arithmetic Reasoning in DPLL-Based SAT Solving (Abstract)

Markus Wedler , University of Kaiserslautern
Dominik Stoffel , University of Kaiserslautern
Wolfgang Kunz , University of Kaiserslautern
pp. 10030

Enhanced Diameter Bounding via Structural (Abstract)

Jason Baumgartner , IBM Server Group
Andreas Kuehlmann , Cadence Berkeley Labs
pp. 10036
1C: Power, Timing and Diagnosis Constrained Testing

null (PDF)

pp. null

Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults (Abstract)

Saravanan Padmanaban , University of Maryland at Baltimore County
Spyros Tragoudas , Southern Illinois University
pp. 10050

Level of Similarity: A Metric for Fault Collapsing (Abstract)

Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
pp. 10056

Design of Routing-Constrained Low Power Scan Chains (Abstract)

Y. Bonhomme , Universit? de Montpellier II/CNRS
P. Girard , Universit? de Montpellier II/CNRS
L. Guiller , Synopsys, Inc.
C. Landrault , Universit? de Montpellier II/CNRS
S. Pravossoudovitch , Universit? de Montpellier II/CNRS
A. Virazel , Universit? de Montpellier II/CNRS
pp. 10062

Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis (Abstract)

Irith Pomeranz , Purdue University
Srikanth Venkataraman , Intel Corporation
Sudhakar M. Reddy , University of Iowa
Bharath Seshadri , Purdue University
pp. 10068
1D: Mixed-Signal Circuits and Systems

null (PDF)

pp. null

Digital Background Gain Error Correction in Pipeline ADCs (Abstract)

Antonio J. Gin? , Instituto de Microelect?nica de Sevilla, Centro Nacional de Microelectr?nica
Eduardo J. Peral?as , Instituto de Microelect?nica de Sevilla, Centro Nacional de Microelectr?nica
Adoraci? Rueda , Instituto de Microelect?nica de Sevilla, Centro Nacional de Microelectr?nica
pp. 10082

Digital Ground Bounce Reduction by Phase Modulation of the Clock (Abstract)

Mustafa Badaroglu , IMEC and K.U. Leuven
Piet Wambacq , K.U. Leuven
Geert Van der Plas , K.U. Leuven
St?phane Donnay , K.U. Leuven
Georges Gielen , K.U. Leuven
Hugo De Man , K.U. Leuven
pp. 10088

Pseudo-Random Sequence Based Tuning System for Continuous-Time Filters (Abstract)

F. Corsi , Politecnico di Bari
C. Marzocca , Politecnico di Bari
G. Matarrese , Politecnico di Bari
A. Baschirotto , Universit? di Lecce
S. D?Amico , Universit? di Lecce
pp. 10094
1E: Communication-Centric and Source-Level Optimisations for High-Level Synthesis

null (PDF)

pp. null

A Crosstalk Aware Interconnect with Variable Cycle Transmission (Abstract)

Lin Li , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
Mahmut Kandemir , Pennsylvania State University
Mary Jane Irwin , Pennsylvania State University
pp. 10102

Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip (Abstract)

Nattawut Thepayasuwan , State University of New York at Stony Brook
Alex Doboli , State University of New York at Stony Brook
pp. 10108

Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow (Abstract)

Sumit Gupta , University of California at Irvine
Nikil Dutt , University of California at Irvine
Rajesh Gupta , University of California at San Diego
Alexandru Nicolau , University of California at Irvine
pp. 10114
1F: Panel Session: SystemC and System Verilog: Where do They Fit? Where are They Going?

null (PDF)

pp. null

SystemC and SystemVerilog: Where do They Fit? Where are They Going? (Abstract)

Donatella Sciuto , Politecnico di Milano
Grant Martin , Cadence Berkeley Labs
Wolfgang Rosenstiel , University of T?bingen
Stuart Swan , Cadence Design Systems
Frank Ghenassia , ST Microelectronics
Peter Flake , Synopsys
Johny Srouji , Intel
pp. 10122
2A: Low Power Systems and Architectures

null (PDF)

pp. null

Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus (Abstract)

Siu-Kei Wong , Hong Kong University of Science and Technology
Chi-Ying Tsui , Hong Kong University of Science and Technology
pp. 10130

Hierarchical Adaptive Dynamic Power Management (Abstract)

Zhiyuan Ren , Carnegie Mellon University
Bruce H. Krogh , Carnegie Mellon University
Radu Marculescu , Carnegie Mellon University
pp. 10136

A Self-Tuning Cache Architecture for Embedded Systems (Abstract)

Chuanjun Zhang , University of California at Riverside
Frank Vahid , University of California at Riverside
Roman Lysecky , University of California at Riverside
pp. 10142

Scheduling Reusable Instructions for Power Reduction (Abstract)

J. S. Hu , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
S. Kim , Pennsylvania State University
M. Kandemir , Pennsylvania State University
M. J. Irwin , Pennsylvania State University
pp. 10148
2B: Advanced Formal Verification Techniques

null (PDF)

pp. null

Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor (Abstract)

Klaus Winkelmann , Infineon Technologies AG
Hans-Joachim Trylus , Siemens AG
Dominik Stoffel , Kaiserslautern University
Goerschwin Fey , Bremen University
pp. 10162
2C: New Algorithms for TPG

null (PDF)

pp. null

Graph-Based Functional Test Program Generation for Pipelined Processors (Abstract)

Prabhat Mishra , University of California at Irvine
Nikil Dutt , University of California at Irvine
pp. 10182

Automatic Generation of Validation Stimuli for Application-Specific Processors (Abstract)

O. Goloubeva , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
M. Violante , Politecnico di Torino
pp. 10188

Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques (Abstract)

Michael Dimopoulos , Aristotle University of Thessaloniki
Panagiotis Linardis , Aristotle University of Thessaloniki
pp. 10194
2E: Optimisation of Memory Hierarchies

null (PDF)

pp. null

Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies (Abstract)

Ilya Issenin , University of California at Irvine
Nikil Dutt , University of California at Irvine
pp. 10202

Automatic Tuning of Two-Level Caches to Embedded Applications (Abstract)

Ann Gordon-Ross , University of California at Riverside
Frank Vahid , University of California at Riverside and University of California at Irvine
Nikil Dutt , University of California at Irvine
pp. 10208

Low Static-Power Frequent-Value Data Caches (Abstract)

Chuanjun Zhang , University of California at Riverside
Jun Yang , University of California at Riverside
Frank Vahid , University of California at Riverside
pp. 10214

Using a Victim Buffer in an Application-Specific Memory Hierarchy (Abstract)

Chuanjun Zhang , University of California at Riverside
Frank Vahid , University of California at Riverside and University of California at Irvine
pp. 10220
2F: Hot Topic — High Security Smartcards

null (PDF)

pp. null

High Security Smartcards (Abstract)

M. Renaudin , Tima Laboratory
F. Bouesse , Tima Laboratory
Ph. Proust , Gemplus Corporate R&D Security Technologies
J. P. Tual , Axalto - Schlumberger
L. Sourgen , STMicroelectronics
F. Germain , Central Directorate of Information Systems Security
pp. 10228
3A: New Directions in Low-Power Design

null (PDF)

pp. null

A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation (Abstract)

Kris Tiri , University of California at Los Angeles
Ingrid Verbauwhede , University of California at Los Angeles
pp. 10246

Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling (Abstract)

Wei-Chung Cheng , University of Southern California
Yu Hou , University of Southern California
Massoud Pedram , University of Southern California
pp. 10252
3B: Advances in SAT

null (PDF)

pp. null

Managing Don?t Cares in Boolean Satisfiability (Abstract)

Sean Safarpour , University of Toronto
Andreas Veneris , University of Toronto
Rolf Drechsler , University of Bremen
Joanne Lee , University of Toronto
pp. 10260

A Novel SAT All-Solutions Solver for Efficient Preimage Computation (PDF)

Bin Li , Virginia Tech.
Michael S. Hsiao , Virginia Tech.
Shuo Sheng , Mentor Graphics Corporation
pp. 10272
3C: Analogue and High-Frequency Test

null (PDF)

pp. null

Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and Benefits (Abstract)

Ganesh Srinivasan , Georgia Institute of Technology
Soumendu Bhattacharya , Georgia Institute of Technology
Sasikumar Cherubal , Ardext Technologies
Abhijit Chatterjee , Georgia Institute of Technology
pp. 10280

Random Jitter Extraction Technique in a Multi-Gigahertz Signal (Abstract)

Chee-Kian Ong , University of California at Santa Barbara
Dongwoo Hong , University of California at Santa Barbara
Kwang-Ting (Tim) Cheng , University of California at Santa Barbara
Li-C Wang , University of California at Santa Barbara
pp. 10286

Low Cost Analog Testing of RF Signal Paths (Abstract)

Marcelo Negreiros , Universidade Federal do Rio Grande do Sul
Luigi Carro , Universidade Federal do Rio Grande do Sul
Altamiro A. Susin , Universidade Federal do Rio Grande do Sul
pp. 10292

A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications (Abstract)

Diego V?zquez , Universidad de Sevilla
Gildas Leger , Universidad de Sevilla
Gloria Huertas , Universidad de Sevilla
Adoraci? Rueda , Universidad de Sevilla
Jos? L. Huertas , Universidad de Sevilla
pp. 10298
3E: Energy Efficient Memory Usage

null (PDF)

pp. null

A Novel Implementation of Tile-Based Address Mapping (Abstract)

Sambuddhi Hettiaratchi , Imperial College of Science, Technology and Medicine, London
Peter Y.K. Cheung , Imperial College of Science, Technology and Medicine, London
pp. 10306

Breaking Instance-Independent Symmetries in Exact Graph Coloring (Abstract)

Arathi Ramani , University of Michigan
Fadi A. Aloul , American University in Dubai
Igor L. Markov , University of Michigan
Karem A. Sakallah , University of Michigan
pp. 10324
3F: Hot Topic — How Can System-Level Design Solve the Interconnect Technology Scaling Problem?

null (PDF)

pp. null

How Can System-Level Design Solve the Interconnect Technology Scaling Problem? (Abstract)

Francky Catthoor , IMEC and Katholieke Universiteit Leuven
Andrea Cuomo , St-Microelectronics
Grant Martin , Cadence Berkeley Laboratories
Patrick Groeneveld , Magma Design Automation
Lauwereins Rudy , IMEC and Katholieke Universiteit Leuven
Karen Maex , IMEC and Katholieke Universiteit Leuven
Patrick van de Steeg , Philips Semiconductor, Eindhoven
Ron Wilson , CMP Media
pp. 10332
4A: System Level Design Methodology

null (PDF)

pp. null

System Design Using Kahn Process Networks: The Compaan/Laura Approach (Abstract)

Todor Stefanov , Leiden University
Claudiu Zissulescu , Leiden University
Alexandru Turjan , Leiden University
Bart Kienhuis , Leiden University
Ed Deprettere , Leiden University
pp. 10340

Microarchitecture Development via Metropolis Successive Platform Refinement (Abstract)

Douglas Densmore , University of California at Berkeley
Sanjay Rekhi , Cypress Semiconductor
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
pp. 10346

Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design (Abstract)

Chulho Shin , Samsung Electronics Co., LTD.
Young-Taek Kim , Samsung Electronics Co., LTD.
Eui-Young Chung , Samsung Electronics Co., LTD.
Kyu-Myung Choi , Samsung Electronics Co., LTD.
Jeong-Taek Kong , Samsung Electronics Co., LTD.
Soo-Kwan Eo , Samsung Electronics Co., LTD.
pp. 10352

SoftContract: an Assertion-Based Software Development Process that Enables Design-by-Contract (Abstract)

Jean-Yves Brunel , Cadence Automotive Team
Marco Di Natale , Scuola Superiore Sant?Anna
Alberto Ferrari , PARADES
Paolo Giusto , Cadence Automotive Team
Luciano Lavagno , Cadence Berkeley Labs
pp. 10358

A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors (Abstract)

D. Quinn , ?cole Polytechnique de Montr?al
B. Lavigueur , ?cole Polytechnique de Montr?al
G. Bois , ?cole Polytechnique de Montr?al
M. Aboulhamid , Universit? de Montr?al
pp. 10364
4B: System Level Modelling and Analysis

null (PDF)

pp. null

Refinement of Mixed-Signal Systems with Affine Arithmetic (Abstract)

Ch. Grimm , University Frankfurt
W. Heupke , University Frankfurt
K. Waldschmidt , University Frankfurt
pp. 10372

System-Level Performance Analysis in SystemC (Abstract)

H. Posadas , University of Cantabria
F. Herrera , University of Cantabria
P. S?nchez , University of Cantabria
E. Villar , University of Cantabria
F. Blasco , DS2 Robert Darwin 2, Parque Tecnol?gico
pp. 10378

Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks (PDF)

Mohammad Reza Mousavi , Eindhoven University of Technology
Paul Le Guernic , INRIA/IRISA
Jean-Pierre Talpin , INRIA/IRISA
Sandeep Kumar Shukla , Virginia Tech.
Twan Basten , Eindhoven University of Technology
pp. 10384

Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures (Abstract)

Vijay D?silva , Indian Institute of Technology Bombay
S. Ramesh , Indian Institute of Technology Bombay
Arcot Sowmya , University of New South Wales
pp. 10390

Aspects of Formal and Graphical Design of a Bus System (Abstract)

Tiberiu Seceleanu , University of Turku
Tomi Westerlund , Turku Centre for Computer Science
pp. 10396
4C: Advances in SoC Testing

null (PDF)

pp. null

Scan Power Minimization through Stimulus and Response Transformations (Abstract)

Ozgur Sinanoglu , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 10404

Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s (Abstract)

Matthew W. Heath , University of Massachusetts at Amherst
Wayne P. Burleson , University of Massachusetts at Amherst
Ian G. Harris , University of California at Irvine
pp. 10410

Wrapper Design for Testing IP Cores with Multiple Clock Domains (Abstract)

Qiang Xu , McMaster University
Nicola Nicolici , McMaster University
pp. 10416

An Arithmetic Structure for Test Data Horizontal Compression (Abstract)

Marie-Lise Flottes , Laboratoire d?Informatique, de Robotique et de Microelectronique de Montpellier
Regis Poirier , Laboratoire d?Informatique, de Robotique et de Microelectronique de Montpellier
Bruno Rouzeyre , Laboratoire d?Informatique, de Robotique et de Microelectronique de Montpellier
pp. 10428
4E: New Issues in Analogue System- and Circuit-Level Performance Modelling

null (PDF)

pp. null

Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques (Abstract)

Lutz Näthke , University of Hanover
Volodymyr Burkhay , University of Hanover
Lars Hedrich , University of Hanover
Erich Barke , University of Hanover
pp. 10442

Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines (Abstract)

Tholom Kiely , Katholieke Universiteit Leuven
Georges Gielen , Katholieke Universiteit Leuven
pp. 10448

Extended Subspace Identification of Improper Linear Systems (Abstract)

Gerd Vandersteen , IMEC vzw.
Rik Pintelon , Vrije Universiteit Brussel
Dimitri Linten , IMEC vzw.
Stéphane Donnay , IMEC vzw.
pp. 10454
4F: Fabrics and Scheduling for Reconfigurable Computing

null (PDF)

pp. null

Exploring Logic Block Granularity for Regular Fabrics (Abstract)

A. Koorapaty , Carnegie Mellon University
V. Kheterpal , Carnegie Mellon University
P. Gopalakrishnan , Carnegie Mellon University
M. Fu , Carnegie Mellon University
L. Pileggi , Carnegie Mellon University
pp. 10468

Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures (Abstract)

Nikhil Bansal , University of California at Irvine
Sumit Gupta , University of California at Irvine
Nikil Dutt , University of California at Irvine
Alex Nicolau , University of California at Irvine
Rajesh Gupta , University of California at San Diego
pp. 10474

A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning (Abstract)

Roman Lysecky , University of California at Riverside
Frank Vahid , University of California at Riverside
pp. 10480

Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms (Abstract)

G. Chen , Pennsylvania State University
M. Kandemir , Pennsylvania State University
U. Sezer , University of Wisconsin-Madison
pp. 10486
4G: Power Aware Design and Synthesis

null (PDF)

pp. null

Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization (Abstract)

Dongwoo Lee , University of Michigan
Harmander Deogun , University of Michigan
David Blaauw , University of Michigan
Dennis Sylvester , University of Michigan
pp. 10494

A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks (Abstract)

Pietro Babighian , Politecnico di Torino
Luca Benini , Università di Bologna
Enrico Macii , Politecnico di Torino
pp. 10500

Impact of Data Transformations on Memory Bank Locality (Abstract)

M. Kandemir , Pennsylvania State University
pp. 10506

Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work (Abstract)

Claudia Kretzschmar , Chemnitz University of Technology
André K. Nieuwland , Philips Research Eindhoven
Dietmar Müller , Chemnitz University of Technology
pp. 10512

Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems (Abstract)

Alexandru Andrei , Linköping University
Marcus Schmitz , Linköping University
Petru Eles , Linköping University
Zebo Peng , Linköping University
Bashir M. Al-Hashimi , University of Southampton
pp. 10518
5A: System Level Design: Case Studies, Exploration and Optimisation

null (PDF)

pp. null

Dynamic Power Management Using Data Buffers (Abstract)

Le Cai , Purdue University
Yung-Hsiang Lu , Purdue University
pp. 10526

High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study (Abstract)

Hye-On Jang , Samsung Advanced Institute of Technology
Minsoo Kang , Samsung Electronics Co., Ltd.
Myeong-jin Lee , Samsung Electronics Co., Ltd.
Kwanyeob Chae , Samsung Electronics Co., Ltd.
Kookpyo Lee , Samsung Electronics Co., Ltd.
Kyuhyun Shim , Samsung Electronics Co., Ltd.
pp. 10538

A SystemC-Based Verification Methodology for Complex Wireless Software IP (Abstract)

Guido Post , Synopsys Inc.
P.K. Venkataraghavan , Synopsys Inc.
Tapan Ray , Synopsys Inc.
D.R. Seetharaman , Synopsys Inc.
pp. 10544
5B: Recent Advances in Digital Systems Simulation

null (PDF)

pp. null

A New Optimized Implemention of the SystemC Engine Using Acyclic Scheduling (Abstract)

Daniel Gracia Pérez , ALCHEMY INRIA Futurs & LRI, Paris South University
Gilles Mouchard , CEA LIST
Olivier Temam , ALCHEMY INRIA Futurs & LRI, Paris South University
pp. 10552

Stimuli Generation with Late Binding of Values (Abstract)

Avi Ziv , IBM Research Laboratory in Haifa
pp. 10558

Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC (Abstract)

Franco Fummi , Università di Verona
Stefano Martini , Embedded Systems Design Center
Giovanni Perbellini , Embedded Systems Design Center
Massimo Poncino , Università di Verona
pp. 10564

Extraction of Schematic Array Models for Memory Circuits (Abstract)

Soumitra Bose , Intel Corporation
Amit Nandi , Intel Corporation
pp. 10570
5C: On-Line Testing and Reliability for Nanometer Technologies

null (PDF)

pp. null

Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA (Abstract)

M. Bellato , Istituto Nazionale di Fisica Nucleare
P. Bernardi , Politecnico di Torino
D. Bortolato , Universit? di Padova
A. Candelori , Istituto Nazionale di Fisica Nucleare
M. Ceschia , Universit? di Padova and Istituto Nazionale di Fisica Nucleare
A. Paccagnella , Universit? di Padova and Istituto Nazionale di Fisica Nucleare
M. Rebaudengo , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
M. Violante , Politecnico di Torino
P. Zambolin , Universit? di Padova
pp. 10584

On Concurrent Error Detection with Bounded Latency in FSMs (Abstract)

Sobeeh Almukhaizim , Yale University
Petros Drineas , Rensselaer Polytechnic Institute
Yiorgos Makris , Yale University
pp. 10596
5E: Parasitic-Aware Analogue Design

null (PDF)

pp. null

Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models (Abstract)

Mukesh Ranjan , University of Cincinnati
Wim Verhaegen , Katholieke Universiteit Leuven
Anuradha Agarwal , University of Cincinnati
Hemanth Sampath , University of Cincinnati
Ranga Vemuri , University of Cincinnati
Geoges Gielen , Katholieke Universiteit Leuven
pp. 10604

Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis (Abstract)

Rajeev Murgai , Fujitsu Laboratories of America, Inc.
Subodh M. Reddy , Fujitsu Laboratories of America, Inc.
Takashi Miyoshi , Fujitsu Laboratories of America, Inc.
Takeshi Horie , Fujitsu Laboratories of America, Inc.
Mehdi Baradaran Tahoori , Northeastern University
pp. 10610

SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level (Abstract)

Thomas Brandtner , In.neon Technologies
Robert Weigel , University of Erlangen-Nuremberg
pp. 10616
5F: Hardware/Software System Design and Architecture Exploration

null (PDF)

pp. null

System Design for DSP Applications Using the MASIC Methodology (Abstract)

Abhijit K. Deb , Royal Institute of Technology
Axel Jantsch , Royal Institute of Technology
Johnny ?berg , Royal Institute of Technology
pp. 10630

Flexible Software Protection Using Hardware/Software Codesign Techniques (Abstract)

Joseph Zambreno , Northwestern University
Alok Choudhary , Northwestern University
Rahul Simha , The George Washington University
Bhagirath Narahari , The George Washington University
pp. 10636

Interactive Cosimulation with Partial Evaluation (Abstract)

Patrick Schaumont , University of California at Los Angeles
Ingrid Verbauwhede , University of California at Los Angeles
pp. 10642

Communication Analysis for System-On-Chip Design (Abstract)

A. Siebenborn , FZI Forschungszentrum Informatik
O. Bringmann , FZI Forschungszentrum Informatik
W. Rosenstiel , Universität Tübingen
pp. 10648
5G: Hot Topic — Extremely Low-Power Logic

null (PDF)

pp. null

Extremely Low-Power Logic (Abstract)

Jacques Gautier , CEA-LETI
Christoph Heer , Infineon Technologies
Ian O?Connor , Ecole centrale de Lyon
U. Schlichtmann , Technical University of Munich
pp. 10656
IP1: Interactive Presentations

Decomposition of Instruction Decoder for Low Power Design (PDF)

Wu-An Kuo , Tsing Hua University
TingTing Hwang , Tsing Hua University
Allen C.-H. Wu , Tsing Hua University
pp. 10664

Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors (PDF)

Johann Laurent , South Brittany University
Nathalie Julien , South Brittany University
Eric Senn , South Brittany University
Eric Martin , South Brittany University
pp. 10666

Formal Verification Coverage: Are the RTL-Properties Covering the Design?s Architectural Intent? (PDF)

Prasenjit Basu , Indian Institute of Technology at Kharagpur
Sayantan Das , Indian Institute of Technology at Kharagpur
Pallab Dasgupta , Indian Institute of Technology at Kharagpur
P.P. Chakrabarti , Indian Institute of Technology at Kharagpur
Chunduri Rama Mohan , Intel Corporation
Limor Fix , Intel Corporation
pp. 10668

Functional Coverage Metric Generation from Temporal Event Relation Graph (PDF)

Young-Su Kwon , Korea Advanced Institute of Science and Technology
Chong-Min Kyung , Korea Advanced Institute of Science and Technology
pp. 10670

Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] Modulators (PDF)

H. Aboushady , University of Paris VI
L. de Lamarre , University of Paris VI
N. Beilleau , University of Paris VI
M.M. Louërat , University of Paris VI
pp. 10674

A Methodology for System-Level Analog Design Space Exploration (PDF)

F. De Bernardinis , University of California at Berkeley and Università di Pisa
A. Sangiovanni-Vincentelli , University of California at Berkeley
pp. 10676

Systematic Design for Optimization of High-Resolution Pipelined ADCs (PDF)

Mohammad Taherzadeh-Sani , University of Tehran
Reza Lotfi , University of Tehran
Omid Shoaei , University of Tehran
pp. 10678

A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit (PDF)

José C. García , University of Las Palmas de Gran Canaria
Juan A. Montiel-Nelson , University of Las Palmas de Gran Canaria
J. Sosa , University of Las Palmas de Gran Canaria
Héctor Navarro , University of Las Palmas de Gran Canaria
pp. 10680

Behavioural Bitwise Scheduling Based on Computational Effort Balancing (PDF)

M.C. Molina , Universidad Complutense de Madrid
R. Ruiz-Sautua , Universidad Complutense de Madrid
J.M. Mend?as , Universidad Complutense de Madrid
R. Hermida , Universidad Complutense de Madrid
pp. 10684

A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters (PDF)

A. Del Re , University of Rome "Tor Vergata"
A. Nannarelli , Technical University, Denmark
M. Re , University of Rome "Tor Vergata"
pp. 10686

Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits (PDF)

Tarvo Raudvere , Royal Institute of Technology
Ashish Kumar Singh , Royal Institute of Technology
Ingo Sander , Royal Institute of Technology
Axel Jantsch , Royal Institute of Technology
pp. 10690
IP2: Interactive Presentations

A Game Theoretic Approach to Low Energy Wireless Video Streaming (PDF)

Ali Iranli , University of Southern California
Kihwan Choi , University of Southern California
Massoud Pedram , University of Southern California
pp. 10696

Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning (PDF)

Luca Benini , Università di Bologna
Alessandro Ivaldi , Politecnico di Torino
Alberto Macii , Politecnico di Torino
Enrico Macii , Politecnico di Torino
pp. 10698

A Low Power Strategy for Future Mobile Terminals (PDF)

Mladen Nikitovic , Royal Institute of Technology
Mats Brorsson , Royal Institute of Technology
pp. 10702

A Digital Test for First-Order [Sigma-Delta] Modulators (PDF)

Gildas Leger , Universidad de Sevilla
Adoraci? Rueda , Universidad de Sevilla
pp. 10708

SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance (PDF)

James Chin , University of Texas at Dallas
Mehrdad Nourani , University of Texas at Dallas
pp. 10710

STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores (PDF)

M. Benabdenbi , Laboratoire LIP6
A. Greiner , Laboratoire LIP6
F. Pêcheux , Laboratoire LIP6
E. Viaud , Laboratoire LIP6
M. Tuna , Laboratoire LIP6
pp. 10712

Are Our Design for Testability Features Fault Secure? (PDF)

C. Metra , University of Bologna
T.M. Mak , Intel Corporation
M. Oma? , University of Bologna
pp. 10714

Test Compression and Hardware Decompression for Scan-Based SoCs (PDF)

Francis G. Wolff , Case Western Reserve University
Chris Papachristou , Case Western Reserve University
David R. McIntyre , Cleveland State University
pp. 10716

Concurrent Sizing, Vdd and V<sub>th</sub> Assignment for Low-Power Design (PDF)

Ashish Srivastava , University of Michigan
Dennis Sylvester , University of Michigan
David Blaauw , University of Michigan
pp. 10718

Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating (PDF)

Pietro Babighian , Politecnico di Torino
Luca Benini , Università di Bologna
Enrico Macii , Politecnico di Torino
pp. 10720
IP3: Interactive Presentations

An Asynchronous Synthesis Toolset Using Verilog (PDF)

Frank Burns , University of Newcastle Upon Tyne
Delong Shang , University of Newcastle Upon Tyne
Albert Koelmans , University of Newcastle Upon Tyne
Alex Yakovlev , University of Newcastle Upon Tyne
pp. 10724

Organizing Libraries of DFG Patterns (PDF)

Gero Dittmann , IBM Research, Zurich Research Laboratory
pp. 10726

Compositional Memory Systems for Data Intensive Applications (PDF)

A.M. Molnos , Delft University of Technology and Philips Research Laboratories
M.J.M. Heijligers , Philips Research Laboratories
S.D. Cotofana , Delft University of Technology
J.T.J. van Eijndhoven , Philips Research Laboratories
pp. 10728

Scalar Metric for Temporal Locality and Estimation of Cache Performance (PDF)

Juha Alakarhu , Tampere University of Technology
Jarkko Niittylahti , Tampere University of Technology
pp. 10730

.NET Framework — A Solution for the Next Generation Tools for System-Level Modeling and Simulation (PDF)

J. Lapalme , Universit? de Montr?al
E.M. Aboulhamid , Universit? de Montr?al
G. Nicolescu , Ecole Polytechnique de Montr?al
L. Charest , Universit? de Montr?al
F.R. Boyer , Ecole Polytechnique de Montr?al
J.P David , Universit? de Montr?al
G. Bois , Ecole Polytechnique de Montr?al
pp. 10732

Design and Behavioral Modeling Tools for Optical Network-on-Chip (PDF)

M. Brière , Ecole Centrale de Lyon
L. Carrel , Ecole Centrale de Lyon
T. Michalke , Ecole Centrale de Lyon
F. Mieyeville , Ecole Centrale de Lyon
I. O?Connor , Ecole Centrale de Lyon
F. Gaffiot , Ecole Centrale de Lyon
pp. 10738

Hierarchical Modeling and Simulation of Large Analog Circuits (PDF)

Sheldon X.-D. Tan , University of California at Riverside
Zhenyu Qi , University of California at Riverside
Hang Li , University of California at Riverside
pp. 10740

Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS (PDF)

Peter R. Wilson , University of Southampton
J. Neil Ross , University of Southampton
Andrew D. Brown , University of Southampton
Tom Kazmierski , University of Southampton
Jerzy Baranowski , Warsaw University of Technology
pp. 10742

Enhancing Reliability of Operational Interconnections in FPGAs (PDF)

Alex Fit-Florea , Southern Methodist University
Miroslav Halas , Southern Methodist University
Fatih Kocan , Southern Methodist University
pp. 10746

Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors (PDF)

Miljan Vuletić , Swiss Federal Institute of Technology Lausanne
Ludovic Righetti , Swiss Federal Institute of Technology Lausanne
Laura Pozzi , Swiss Federal Institute of Technology Lausanne
Paolo Ienne , Swiss Federal Institute of Technology Lausanne
pp. 10748
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