Design, Automation & Test in Europe Conference & Exhibition (2004)
Feb. 16, 2004 to Feb. 20, 2004
Manish Handa , University of Cincinnati
Ranga Vemuri , University of Cincinnati
In this paper, we present a fast algorithm for finding empty area on the FPGA surface with some rectangular tasks placed on it. We use a staircase datastructure to report the empty area in the form of a list of maximal empty rectangles. We model the FPGA surface using an innovative encoding scheme that improves runtime and reduces memory requirement of our algorithm.Worst-case time complexity of our algorithm is O(xy) where x is number of columns, y is number of rows and x.y is the total number of cells on the FPGA.
R. Vemuri and M. Handa, "A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement," Design, Automation & Test in Europe Conference & Exhibition(DATE), Paris, France, 2004, pp. 10744.