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Design, Automation & Test in Europe Conference & Exhibition (2004)
Paris, France
Feb. 16, 2004 to Feb. 20, 2004
ISSN: 1530-1591
ISBN: 0-7695-2085-5
pp: 10246
Ingrid Verbauwhede , University of California at Los Angeles
Kris Tiri , University of California at Los Angeles
ABSTRACT
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make ?new? compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.
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CITATION
Ingrid Verbauwhede, Kris Tiri, "A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation", Design, Automation & Test in Europe Conference & Exhibition, vol. 01, no. , pp. 10246, 2004, doi:10.1109/DATE.2004.1268856
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