The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2003)
Munich, Germany
Mar. 3, 2003 to Mar. 7, 2003
ISSN: 1530-1591
ISBN: 0-7695-1870-2
TABLE OF CONTENTS
Introduction

Reviewers (PDF)

pp. xxxv

Welcome to Date 2003 (PDF)

pp. xxxviii

Best Paper Awards (PDF)

pp. xxxix

Tutorials (PDF)

pp. xl

Master Courses (PDF)

pp. xliii
Plenary: Keynote Session

IC Design Challenges for Ambient Intelligence (Abstract)

Raf Roovers , Philips Research Laboratories
Emile Aarts , Philips Research Laboratories
pp. 10002

Semiconductor Challenges (PDF)

Andrea Cuomo , STMicroelectronics
pp. 10008
1A: Hot Topic:Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts

Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts (Abstract)

Rainer Zimmermann , European Commission
Menno Lindwer , Philips Research
Diana Marculescu , Carnegie Mellon University
Twan Basten , Eindhoven University of Technology
Stefan Jung , Infineon Technologies
Eugenio Cantatore , Philips Research
Radu Marculescu , Carnegie Mellon University
pp. 10010
1B: Energy-Efficient Memory Systems

Improving the Efficiency of Memory Partitioning by Address Clustering (Abstract)

Massimo Poncino , Università di Verona
Enrico Macii , Politecnico di Torino
Alberto Macii , Politecnico di Torino
pp. 10018

A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors (Abstract)

Alberto Macii , Politecnico di Torino
Enrico Macii , Politecnico di Torino
Roberto Zafalon , STMicroelectronics
Fabrizio Crudo , STMicroelectronics
pp. 10024

Power Efficiency through Application-Specific Instruction Memory Transformations (Abstract)

Peter Petrov , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 10030

Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures (Abstract)

M. Fernández , Universidad Complutense de Madrid
M. Anido , Federal University do Rio de Janeiro
H. Du , University of California at Irvine
N. Bagherzadeh , University of California at Irvine
M. Sánchez-Élez , Universidad Complutense de Madrid
R. Hermida , Universidad Complutense de Madrid
pp. 10036
1C: Embedded Tutorial: Circuit, Platform Design and Test Challenges in Technologies Beyond 90nm

Circuit and Platform Design Challenges in Technologies beyond 90nm (Abstract)

Bill Grundmann , Intel Corporation
Rajesh Galivanche , Intel Corporation
Sandip Kundu , Intel Corporation
pp. 10044
1F: Uncertainty

Global Wire Bus Configuration with Minimum Delay Uncertainty (Abstract)

Hung-Ming Chen , University of Texas at Austin
D. F. Wong , University of Illinois at Urbana-Champaign
Li-Da Huang , University of Texas at Austin
pp. 10050

Statistical Timing Analysis Using Bounds (Abstract)

Aseem Agarwal , University of Michigan
David Blaauw , University of Michigan
Vladimir Zolotov , Motorola, Inc.
Sarma Vrudhula , University of Arizona
pp. 10062

Reduced Delay Uncertainty in High Performance Clock Distribution Networks (Abstract)

Eby G. Friedman , University of Rochester
Dimitrios Velenis , University of Rochester
Marios C. Papaefthymiou , University of Michigan
pp. 10068
2A: Hot Topic: Scaling into Ambient Intelligence

Scaling into Ambient Intelligence (Abstract)

Feng Zhao , Palo Alto Research Center
Luca Benini , University of Bologna
Rex Min , Massachusetts Institute of Technology
Menno Lindwer , Philips Research Laboratories
Jie Liu , Palo Alto Research Center
Twan Basten , Eindhoven University of Technology
Anantha Chandrakasan , Massachusetts Institute of Technology
pp. 10076
2B: Power-Aware Design and Synthesis

Masking the Energy Behavior of DES Encryption (Abstract)

S. Kim , Pennsylvania State University
W. Zhang , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
M. J. Irwin , Pennsylvania State University
M. Kandemir , Pennsylvania State University
H. Saputra , Pennsylvania State University
R. Brooks , Pennsylvania State University
pp. 10084

Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems (Abstract)

Bashir M. Al-Hashimi , University of Southampton
Dong Wu , University of Southampton
Petru Eles , Link?pings University
pp. 10090
2C: Test Data Compression

Virtual Compression through Test Vector Stitching for Scan Based Designs (Abstract)

Alex Orailoglu , University of California at San Diego
Wenjing Rao , University of California at San Diego
pp. 10104

A Technique for High Ratio LZW Compression (Abstract)

Michael J. Knieser , Indiana University Purdue University Indianapolis
David R. McIntyre , Cleveland State University
Francis G. Wolff , Case Western Reserve University
Daniel J. Weyer , Cisco Systems
Chris A. Papachristou , Case Western Reserve University
pp. 10116

Fast Computation of Data Correlation Using BDDs (Abstract)

Qiushuang Zhang , University of Massachusetts at Amherst
Zhihong Zeng , Avery Design Systems, Inc.
Maciej Ciesielski , University of Massachusetts at Amherst
Ian Harris , University of Massachusetts at Amherst
pp. 10122
2E: Operating System Abstraction and Targeting (Embedded Software Forum)

RTOS Modeling for System Level Design (Abstract)

Haobo Yu , University of California at Irvine
Andreas Gerstlauer , University of California at Irvine
Daniel D. Gajski , University of California at Irvine
pp. 10130

Modeling and Integration of Peripheral Devices in Embedded Systems (Abstract)

Sharad Malik , Princeton University
Shaojie Wang , Princeton University
Reinaldo A. Bergamaschi , IBM T.J.Watson Research Center
pp. 10136

Systemic Embedded Software Generation from SystemC (Abstract)

H. Posadas , University of Cantabria
P. Sánchez , University of Cantabria
F. Herrera , University of Cantabria
E. Villar , University of Cantabria
pp. 10142
2F: Analysis of Jitter and Noise for Analogue Systems and SD Modelling and Simulation

Noise Macromodel for Radio Frequency Integrated Circuits (Abstract)

Peng Li , Carnegie Mellon University
Yang Xu , Carnegie Mellon University
Xin Li , Carnegie Mellon University
Lawrence Pileggi , Carnegie Mellon University
pp. 10150

Approximation Approach for Timing Jitter Characterization in Circuit Simulators (Abstract)

M. M. Zharov , Russian Academy of Sciences
S. G. Rusakov , Russian Academy of Sciences
M. M. Gourary , Russian Academy of Sciences
K. K. Gullapalli , Motorola Inc.
S. L. Ulyanov , Russian Academy of Sciences
B. J. Mulvaney , Motorola Inc.
pp. 10156

A Model of Computation for Continuous-Time Δ-Σ Modulators (Abstract)

Georges Gielen , Katholieke Universiteit Leuven
Ewout Martens , Katholieke Universiteit Leuven
pp. 10162

Behavioural Modelling and Simulation of ΣΔ Modulators Using Hardware Description Languages (Abstract)

F. Medeiro , IMSE-CNM and Escuela Superior de Ingenieros
A. Rodríguez-Vázquez , IMSE-CNM and Escuela Superior de Ingenieros
F. V. Fernández , IMSE-CNM and Escuela Superior de Ingenieros
R. Castro-López , IMSE-CNM
pp. 10168
3A: Hot Topic: Securing Your Mobile Appliance: New Challenges for the System Designer

Securing Mobile Appliances: New Challenges for the System Designer (Abstract)

Sunil Hattangady , Texas Instruments Inc.
Anand Raghunathan , NEC Laboratories America
Srivaths Ravi , NEC Laboratories America
Jean-Jacques Quisquater , Universite Catholique de Louvain
pp. 10176
3B: Scheduling and Analysis of Embedded Systems

Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems (Abstract)

Petru Eles , Link?ping University
Paul Pop , Link?ping University
Zebo Peng , Link?ping University
pp. 10184

A General Framework for Analysing System Properties in Platform-Based Embedded System Designs (Abstract)

Lothar Thiele , Swiss Federal Institute of Technology
Samarjit Chakraborty , Swiss Federal Institute of Technology
Simon Künzli , Swiss Federal Institute of Technology
pp. 10190

Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures (Abstract)

Reinhold Weiss , Technische Universität Graz
Martin Schmid , Technische Universität Graz
Bernhard Rinner , Technische Universität Graz
pp. 10204
3C: Recent Advances in DFT and BIST

DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers (Abstract)

Muhammad Nummer , University of Waterloo
Manoj Sachdev , University of Waterloo
pp. 10212

Extending JTAG for Testing Signal Integrity in SoCs (Abstract)

N. Ahmed , University of Texas at Dallas
M. Nourani , University of Texas at Dallas
M. Tehranipour , University of Texas at Dallas
pp. 10218

EBIST: A Novel Test Generator with Built-In Fault Detection Capability (Abstract)

Chunsheng Liu , Duke University
Dhiraj K. Pradhan , University of Bristol
Krish Chakraborty , Duke University
pp. 10224
3F: Analogue and RF Modelling, Simulation and Optimisation

Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors (Abstract)

Georges Gielen , Katholieke Universiteit Leuven
Piet Vanassche , Katholieke Universiteit Leuven
Willy Sansen , Katholieke Universiteit Leuven
pp. 10238

A New Simulation Technique for Periodic Small-Signal Analysis (Abstract)

B. J. Mulvaney , Motorola Inc.
M. M. Gourary , Russian Academy of Sciences
M. M. Zharov , Russian Academy of Sciences
S. G. Rusakov , Russian Academy of Sciences
S. L. Ulyanov , Russian Academy of Sciences
pp. 10244

Generalized Posynomial Performance Modeling (Abstract)

Walter Daems , Katholieke Universiteit Leuven
Tom Eeckelaert , Katholieke Universiteit Leuven
Willy Sansen , Katholieke Universiteit Leuven
Georges Gielen , Katholieke Universiteit Leuven
pp. 10250
4A: Architectural Level Synthesis

High-Level Allocation to Minimize Internal Hardware Wastage (Abstract)

M. C. Molina , Universidad Complutense de Madrid
R. Hermida , Universidad Complutense de Madrid
J. M. Mendías , Universidad Complutense de Madrid
pp. 10264

Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs (Abstract)

Rajesh Gupta , University of California at San Diego
Nikil Dutt , University of California at Irvine
Alex Nicolau , University of California at Irvine
Sumit Gupta , University of California at Irvine
pp. 10270

Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units (Abstract)

Takashi Nanya , University of Tokyo
Hiroshi Saito , University of Tokyo
Dong-Ik Lee , K-JIST
Euiseok Kim , University of Tokyo and K-JIST
Jeong-Gun Lee , K-JIST
Hiroshi Nakamura , University of Tokyo
pp. 10276

Automated Bus Generation for Multiprocessor SoC Design (Abstract)

Vincent J. Mooney III , Georgia Institute of Technology
Kyeong Keol Ryu , Georgia Institute of Technology
pp. 10282
4B: Scheduling in Reconfigurable Computing

Online Scheduling for Block-Partitioned Reconfigurable Devices (Abstract)

Marco Platzner , Swiss Federal Institute of Technology
Herbert Walder , Swiss Federal Institute of Technology
pp. 10290

Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling (Abstract)

Diederik Verkest , IMEC vzw and Vrije Universiteit Brussel
Serge Vernalde , IMEC vzw
Hugo De Man , IMEC vzw and Katholic Universiteit Leuven
Bingfeng Mei , IMEC vzw and Katholic Universiteit Leuven
Rudy Lauwereins , IMEC vzw and Katholic Universiteit Leuven
pp. 10296
4C: Delay Testing and Diagnosis

A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms (Abstract)

Satoshi Ohtake , Nara Institute of Science and Technology
Kouhei Ohtani , Sanyo Electronics Co., Ltd.
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 10310

Non-Enumerative Path Delay Fault Diagnosis (Abstract)

Spyros Tragoudas , Southern Illinois University
Saravanan Padmanaban , Southern Illinois University
pp. 10322

Delay Defect Diagnosis Based Upon Statistical Timing Models — The First Step (Abstract)

Li-C. Wang , University of California at Santa Barbara
Angela Krstic , University of California at Santa Barbara
Jing-Jia Liou , National Tsing-Hua University
Kwang-Ting Cheng , University of California at Santa Barbara
Magdy S. Abadir , Motorola Inc.
pp. 10328
4E: Embedded Tutorial: Embedded Operating Systems for SoC (Embedded Software Forum)

Embedded Software in Digital AM-FM Chipset (PDF)

J. Quevremont , Thales Communications
M. Sarlotte , Thales Communications
D. Merel , Thales Communications
B. Candaele , Thales Communications
pp. 10340
4F: Networks-on-Chip

Packetized On-Chip Interconnect Communication Analysis for MPSoC (Abstract)

Luca Benini , University of Bologna
Terry Tao Ye , Stanford University
Giovanni De Micheli , Stanford University
pp. 10344

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip (Abstract)

K. G. W. Goossens , Philips Research Laboratories
J. Dielissen , Philips Research Laboratories
J. van Meerbergen , Philips Research Laboratories
E. Rijpkema , Philips Research Laboratories
A. Rădulescu , Philips Research Laboratories
P. Wielage , Philips Research Laboratories
E. Waterlander , Philips Research Laboratories
pp. 10350

Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors (Abstract)

Michael J. Thul , University of Kaiserslautern
Frank Gilbert , University of Kaiserslautern
Norbert Wehn , University of Kaiserslautern
pp. 10356
5A: System Level Modelling

Development and Application of Design Transformations in ForSyDe (Abstract)

Ingo Sander , Royal Institute of Technology
Axel Jantsch , Royal Institute of Technology
Zhonghai Lu , Royal Institute of Technology
pp. 10364

System Level Specification in Lava (Abstract)

Satnam Singh , Xilinx Inc.
pp. 10370

Formal Semantics of Synchronous SystemC (Abstract)

Ashraf Salem , Ain Shams University
pp. 10376

Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated (PDF)

Frederic Doucet , University of California at Irvine
Sandeep Shukla , Virginia Tech
Rajesh Gupta , University of California at San Diego
pp. 10382

SystemC-AMS Requirements, Design Objectives and Rationale (Abstract)

Karsten Einwich , Frauenhofer IIS/EAS
Christoph Grimm , University Frankfurt
Alain Vachoux , Swiss Federal Institute of Technology
pp. 10388
5B: Hot Topic: Runtime Reconfigurable Systems on Chip — An Industry Perspective

Parallel Processing Architectures for Reconfigurable Systems (PDF)

Kees A. Vissers , University of California at Berkeley
pp. 10396

A Lightweight Approach for Embedded Reconfiguration of FPGAs (PDF)

Brandon Blodget , Xilinx Research Labs
Scott McMillan , Xilinx Inc.
Patrick Lysaght , Xilinx Research Labs
pp. 10399
5C: Hot Topic: Creating Value Through Test

Creating Value Through Test (Abstract)

Bart Vermeulen , Philips Research Laboratories
Michael Kessler , IBM Deutschland Entwicklung GmbH
Robert Madge , LSI Logic Corp.
Michael Müller , IBM Deutschland Entwicklung GmbH
Erik Jan Marinissen , Philips Research Laboratories
pp. 10402
5E: Software Optimisation for Embedded Systems (Embedded Software Forum)

Control Flow Driven Splitting of Loop Nests at the Source Code Level (Abstract)

Heiko Falk , University of Dortmund
Peter Marwedel , University of Dortmund
pp. 10410

Data Space Oriented Scheduling in Embedded Systems (Abstract)

G. Chen , Penn State University
M. Kandemir , Penn State University
I. Kolcu , UMIST
W. Zhang , Penn State University
pp. 10416

An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling (Abstract)

Marisa López-Vallejo , Technical University of Madrid
Yosinori Watanabe , Cadence Berkeley Laboratories
Antonio G. Lomeña , Technical University of Madrid
Alex Kondratyev , Cadence Berkeley Laboratories
pp. 10428
5F: Global Approaches to Layout Synthesis

Time Budgeting in a Wireplanning Context (Abstract)

Ralph H.J.M. Otten , Eindhoven University of Technology
Dirk-Jan Jongeneel , Delft University of Technology
Chandu Visweswariah , IBM Thomas J.Watson Research Center
Jurjen Westra , Eindhoven University of Technology
pp. 10436

Interconnect Planning with Local Area Constrained Retiming (Abstract)

Ruibing Lu , Purdue University
Cheng-Kok Koh , Purdue University
pp. 10442

A Novel Metric for Interconnect Architecture Performance (Abstract)

Swamy Muddu , University of California at San Diego
Andrew B. Kahng , University of California at San Diego
Parthasarathi Dasgupta , University of California at San Diego
pp. 10448
6A: Platform Design and IP Reuse Methods

Specification of Non-Functional Intellectual Property Components (Abstract)

Jianwen Zhu , University of Toronto
Wai Sum Mong , University of Toronto
pp. 10456

Profile-Driven Selective Code Compression (Abstract)

Haris Lekatsas , NEC USA
Yuan Xie , Princeton University
Wayne Wolf , Princeton University
pp. 10462

Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver (Abstract)

Chengzhi Pan , University of California at Irvine
Amir Hosein Kamalizad , University of California at Irvine
Nader Bagherzadeh , University of California at Irvine
Arezou Koohi , University of California at Irvine
pp. 10468
6B: Panel: Reconfigurable Computing — Different Perspectives

Panel Title: Reconfigurable Computing — Different Perspectives (PDF)

C. Rowen , Tensilica, US
Y. Tanurhan , Actel, US
W. Rosenstiel , Tuebingen U/FZI, DE
S. Wang , Axis Systems, US
I. Bolsens , Xilinx, US
K. Vissers , Chameleon Systems, US
R. Lauwereins , IMEC, BE
pp. 10476
6C: Analogue and Defect-Oriented Testing

RF-BIST: Loopback Spectral Signature Analysis (Abstract)

Doris Lupea , Technische UniversitäT Dresden
Hans-Joachim Jentschel , Technische UniversitäT Dresden
Udo Pursche , Technische UniversitäT Dresden
pp. 10478

Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation (Abstract)

Zaid Al-Ars , Delft University of Technology
Ad J. van de Goor , Delft University of Technology
Jens Braun , Infineon Technologies AG
Detlev Richter , Infineon Technologies AG
pp. 10484

On Modeling Cross-Talk Faults (Abstract)

Sujit T Zachariah , Intel Corporation
Chandra Tirumurti , Intel Corporation
Sandip Kundu , Intel Corporation
Yi-Shing Chang , Intel Corporation
pp. 10490
6E: Energy Aware Software Techniques (Embedded Software Forum)

Runtime Code Parallelization for On-Chip Multiprocessors (Abstract)

W. Zhang , Penn State University
M. Kandemir , Penn State University
M. Karakoy , Imperial College
pp. 10510

SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms (Abstract)

L. Benini , D.E.I.S. University of Bologna
F. Catthoor , IMEC and K.U. Leuven-ESAT
L. Piñuel , DACYA U.C.M.
P. Marchal , IMEC and K.U. Leuven-ESAT
D. Bruni , D.E.I.S. University of Bologna
H. Corporaal , IMEC and T.U. Eindhoven
J. I. Gomez , DACYA U.C.M.
pp. 10516
6F: Interconnect Modelling and Signal Integrity

Modeling and Evaluation of Substrate Noise Induced by Interconnects (Abstract)

Ferran Martorell , Universitat Polit?cnica de Catalunya
Xavier Aragonès , Universitat Polit?cnica de Catalunya
Diego Mateo , Universitat Polit?cnica de Catalunya
pp. 10524

Model-Order Reduction Based on PRONY?s Method (Abstract)

Amit Mehrotra , University of Illinois at Urbana-Champaign
Makram M. Mansour , University of Illinois at Urbana-Champaign
pp. 10530

Combined FDTD/Macromodel Simulation of Interconnected Digital Devices (Abstract)

S. Grivet-Talocia , Politecnico di Torino
F. G. Canavero , Politecnico di Torino
I. A. Maio , Politecnico di Torino
I. S. Stievano , Politecnico di Torino
pp. 10536

Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses (Abstract)

Tiehan Lv , Princeton University
Wayne Wolf , Princeton University
Haris Lekatsas , NEC, USA
Jörg Henkel , NEC, USA
pp. 10542
7A: System Level Simulation

Instruction Set Emulation for Rapid Prototyping of SoCs (Abstract)

Wolfgang Rosenstiel , FZI Forschungszentrum Informatik and Universit?t T?bingen
Gunter Haug , FZI Forschungszentrum Informatik
Jürgen Schnerr , FZI Forschungszentrum Informatik
pp. 10562
7B: Design Space Exploration for Reconfigurable Computing

Hardware/Software Design Space Exploration for a Reconfigurable Processor (Abstract)

Alberto La Rosa , Politecnico di Torino
Luciano Lavagno , Politecnico di Torino
Claudio Passerone , Politecnico di Torino
pp. 10570

From C Programs to the Configure-Execute Model (Abstract)

Markus Weinhardt , PACT XPP Technologies AG
João M. P. Cardoso , University of Algarve
pp. 10576

FPGA-Based Implementation of a Serial RSA Processor (Abstract)

G. P. Saggese , Universita? degli Studi di Napoli "Federico II"
N. Mazzocca , Seconda Universita? degli Studi di Napoli
A. Mazzeo , Universita? degli Studi di Napoli "Federico II"
L. Romano , Universita? degli Studi di Napoli "Federico II"
pp. 10582
7C: On-Line Testing and Self-Repair

Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair (Abstract)

M. Nicolaidis , iRoC Technologies
S. Boutobza , iRoC Technologies
N. Achouri , iRoC Technologies
pp. 10590

Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric (Abstract)

Mark Zwolinski , University of Southampton
Petros Oikonomakos , University of Southampton
Bashir M. Al-Hashimi , University of Southampton
pp. 10596

High Speed and Highly Testable Parallel Two-Rail Code Checker (Abstract)

Cecilia Metra , University of Bologna
Daniele Rossi , University of Bologna
Martin Omaña , University of Bologna
pp. 10608
7E: Hot Topic: Safe Automotive Software Development (Embedded Software Forum)

Safe Automotive Software Development (Abstract)

Fabian Wolf , Volkswagen AG
Rolf Ernst , Technische Universit?t Braunschweig
Hermann Kopetz , Technische Universit?t Wien
Ken Tindell , LiveDevices
pp. 10616
7F: Mixed-Signal Design Techniques

Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters (Abstract)

José Luis González , Universitat Polit?cnica de Catalunya
Eduard Alarcón , Universitat Polit?cnica de Catalunya
Miquel Albiol , Universitat Polit?cnica de Catalunya
pp. 10636
8A: Design Space Exploration

Analytical Design Space Exploration of Caches for Embedded Systems (Abstract)

Arijit Ghosh , University of California at Irvine
Tony Givargis , University of California at Irvine
pp. 10650

Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs (Abstract)

Vladimir D. Živković , Leiden University
Pieter van der Wolf , Philips Research Laboratories
Erwin de Kock , Philips Research Laboratories
Ed Deprettere , Leiden University
pp. 10656

Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform (Abstract)

Joel Cambonie , STMicroelectronics
Laura Vanzago , STMicroelectronics
Bishnupriya Bhattacharya , Cadence Design Systems
Luciano Lavagno , Politecnico di Torino
pp. 10662

A First Step Towards Hw/Sw Partitioning of UML Specifications (Abstract)

F. Salice , Politecnico di Milano and CEFRIEL
L. Zampella , Politecnico di Milano
P. Micheli , Politecnico di Milano
W. Fornaciari , Politecnico di Milano and CEFRIEL
pp. 10668

Multi-Granularity Metrics for the Era of Strongly Personalized SOCs (Abstract)

Y. Le Moullec , Universit? de Bretagne Sud
M. Abid , ENIS
N. Ben Amor , Universit? de Bretagne Sud and ENIS
J-L. Philippe , Universit? de Bretagne Sud
J-Ph. Diguet , Universit? de Bretagne Sud
pp. 10674
8B: Low Power Architectures

Energy Estimation for Extensible Processors (Abstract)

Srivaths Ravi , NEC Labs
Niraj K. Jha , Princeton University
Yunsi Fei , Princeton University
pp. 10682

Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface (Abstract)

Wei-Chung Cheng , University of Southern California
Massoud Pedram , University of Southern California
pp. 10694

Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems (Abstract)

Anand Raghunathan , NEC USA and Alphion Corp.
Davide Bertozzi , University of Bologna
Srivaths Ravi , NEC USA and Alphion Corp.
Luca Benini , University of Bologna
pp. 10706
8C: System-on-Chip Testing

Low-Cost Software-Based Self-Testing of RISC Processor Cores (Abstract)

A. Paschalis , University of Athens
D. Gizopoulos , University of Piraeus
G. Xenoulis , University of Piraeus
N. Kranitis , University of Athens
Y. Zorian , Virage Logic
pp. 10714

A P1500-Compatible Programmable BIST Aapproach for the Test of Embedded Flash Memories (Abstract)

M. Rebaudengo , Politecnico di Torino
M. Violante , Politecnico di Torino
P. Bernardi , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
pp. 10720

Test Data Compression: The System Integrator?s Perspective (Abstract)

Paul Theo Gonciari , University of Southampton
Nicola Nicolici , McMaster University
Bashir M Al-Hashimi , University of Southampton
pp. 10726

Time Domain Multiplexed TAM:Implementation and Comparison (Abstract)

Zahra Sadat Ebadi , University of British Columbia
Andre Ivanov , University of British Columbia
pp. 10732

Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization (Abstract)

Sandeep Kumar Goel , Philips Research Laboratories
Erik Jan Marinissen , Philips Research Laboratories
pp. 10738

Delay Fault Testing of Core-Based Systems-on-a-Chip (Abstract)

Qiang Xu , McMaster University
Nicola Nicolici , McMaster University
pp. 10744
8D: Synthesis and Analysis of Digital Circuits

Reducing Multi-Valued Algebraic Operations to Binary (Abstract)

Jie-Hong R. Jiang , University of California at Berkeley
Robert K. Brayton , University of California at Berkeley
Alan Mishchenko , Portland State University
pp. 10752

Combination of Lower Bounds in Exact BDD Minimization (Abstract)

Rüdiger Ebendt , University of Kaiserslautern
Wolfgang Günther , Infineon Technologies
Rolf Drechsler , University of Bremen
pp. 10758

Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information (Abstract)

Ulrich Seidl , Technical University of Munich
Klaus Eckl , Synopsys GmbH
Frank Johannes , Technical University of Munich
pp. 10770
8E: Embedded System Architectures (Embedded Software Forum)

Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology (Abstract)

Amit Agarwal , Purdue University
T. N. Vijaykumar , Purdue University
Kaushik Roy , Purdue University
pp. 10778

Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation (Abstract)

S. K. Nandy , Indian Institute of Science
G. Surendra , Indian Institute of Science
Subhasis Banerjee , Indian Institute of Science
pp. 10784

On-Chip Stochastic Communication (Abstract)

Tudor Dumitraş , Carnegie Mellon University
Radu Mărculescu , Carnegie Mellon University
pp. 10790

An Integrated Approach for Improving Cache Behavior (Abstract)

Alok Choudhary , Northwestern University
Gokhan Memik , University of California at Los Angeles
Mahmut Kandemir , Penn State
Ismail Kadayif , Penn State
pp. 10796

Rapid Configuration and Instruction Selection for an ASIP: A Case Study (Abstract)

Newton Cheung , University of New South Wales
Sri Parameswaran , University of New South Wales
Jörg Henkel , NEC Laboratories America
pp. 10802
8F: Specification and Verification in Action

Local Search for Boolean Relations on the Basis of Unit Propagation (Abstract)

Yakov Novikov , National Academy of Sciences of Belarus
pp. 10810

Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis (Abstract)

Randal E. Bryant , Carnegie Mellon University
Amit Goel , Carnegie Mellon University
pp. 10816

Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol (Abstract)

Tulika Mitra , National University of Singapore
S. R. Karri , National University of Singapore
Abhik Roychoudhury , National University of Singapore
pp. 10828
9A: Hot Topic: RF Design Technology for Highly Integrated Communication Systems

Hot Topic Session: RF Design Technology for Highly Integrated Communication Systems (Abstract)

Hans-Joachim Wassener , Atmel Germany GmbH
Michael Schröter , Technical University of Dresden
Jürgen Hartung , Cadence Design Systems
Reimund Wittmann , NOKIA Research Center
Günther Tränkle , Infineon Technologies
pp. 10842
9B: Zoning Chip Estate

Power/Ground Mesh Area Optimization Using Multigrid-Based Technique (Abstract)

Kai Wang , University of California at Santa Barbara
Malgorzata Marek-Sadowska , University of California at Santa Barbara
pp. 10850

A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees (Abstract)

Chris C. N. Chu , Iowa State University
Evangeline F. Y. Young , Chinese University of Hong Kong
Steve T. W. Lai , Chinese University of Hong Kong
pp. 10856

Crosstalk Reduction in Area Routing (Abstract)

Patrick H. Madden , Binghamton University
Bill Swartz , InternetCAD Inc
Ryon M. Smey , Binghamton University
pp. 10862

Area Fill Generation With Inherent Data Volume Reduction (Abstract)

Yu Chen , University of California at Los Angeles
Alexander Zelikovsky , Georgia State University
Andrew B. Kahng , University of California at San Diego
Yuhong Zheng , University of California at San Diego
Gabriel Robins , University of Virginia
pp. 10868
9C: Panel:Transaction Based Design: Another Buzzword or the Solution to a Design Problem?

Transaction Based Design: Another Buzzword or the Solution to a Design Problem? (PDF)

Heinz-Joseph Schlebusch , Synopsys, Germany
Carsten Mielenz , Infineon Technologies, Germany
Donatella Sciuto , Politecnico di Milano, Italy
Gary Smith , Gartner Dataquest, USA
Daniel Gajski , University of California at Irvine
Stuart Swan , Cadence, USA
Joachim Kunkel , Synopsys, USA
Frank Ghenassia , ST Microelectronics, France
Christopher K. Lennard , ARM Ltd., United Kingdom
pp. 10876
9D: Trust in SAT-Based Verification?

Verification of Proofs of Unsatisfiability for CNF Formulas (Abstract)

Yakov Novikov , National Academy of Sciences (Belarus)
Evgueni Goldberg , Cadence Berkeley Labs
pp. 10886

A Circuit SAT Solver With Signal Correlation Guided Learning (Abstract)

Kwang-Ting Cheng , University of California at Santa Barbara
Feng Lu , University of California at Santa Barbara
Li-C. Wang , University of California at Santa Barbara
Ric C-Y Huang , Verplex Systems, Inc.
pp. 10892

Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals (Abstract)

Gianpiero Cabodi , Politecnico di Torino
Sergio Nocco , Politecnico di Torino
Stefano Quer , Politecnico di Torino
pp. 10898
9E: Transformations for Real-Time Software (Embedded Software Forum)

Generalized Data Transformations for Enhancing Cache Behavior (Abstract)

I. Kadayif , Penn State University
V. De La Luz , Penn State University
U. Sezer , University of Wisconsin
M. Kandemir , Penn State University
pp. 10906

Software Streaming via Block Streaming (Abstract)

Pramote Kuacharoen , Georgia Institute of Technology
Vincent J. Mooney , Georgia Institute of Technology
Vijay K. Madisetti , Georgia Institute of Technology
pp. 10912
9F1: Synthesis Tools for Asynchronous Circuits

Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design (Abstract)

Alex Yakovlev , University of Newcastle upon Tyne
Agnes Madalinski , University of Newcastle upon Tyne
Victor Khomenko , University of Newcastle upon Tyne
Alex Bystrov , University of Newcastle upon Tyne
pp. 10926

STG Optimisation in the Direct Mapping of Asynchronous Circuits (Abstract)

D. Sokolov , University of Newcastle upon Tyne
A. Yakovlev , University of Newcastle upon Tyne
A. Bystrov , University of Newcastle upon Tyne
pp. 10932
9F2: Collaborative Design and WWW-Based Tools

Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues (Abstract)

Ricardo Reis , UFRGS
Manfred Glesner , Technical University Darmstadt
Florian Lubitz , Technical University Darmstadt
Leandro Soares Indrusiak , UFRGS and Technical University Darmstadt
pp. 10940

Dynamic Tool Integration in Heterogeneous Computer Networks (Abstract)

Jan Wegner , Zuken - EMC Technology Center
Wolfgang Mueller , Paderborn University
Heinz-Josef Eikerling , Siemens Business Services
Tim Schattkowsky , Paderborn University
pp. 10946
10A: Performance Optimisation in Hardware/Software Codesign

Layered, Multi-Threaded, High-Level Performance Design (Abstract)

Donald E. Thomas , Carnegie Mellon University
JoAnn M. Paul , Carnegie Mellon University
Andrew S. Cassidy , Carnegie Mellon University
pp. 10954

Processor/Memory Co-Exploration on Multiple Abstraction Levels (Abstract)

Heinrich Meyr , Integrated Signal Processing Systems
Rainer Leupers , Integrated Signal Processing Systems
Oliver Schliebusch , Integrated Signal Processing Systems
Achim Nohl , LISATek Inc.
Gunnar Braun , Integrated Signal Processing Systems
Andreas Wieferink , Integrated Signal Processing Systems
pp. 10966
10B: Dynamic Resource Management for Reconfigurable Systems

Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip (Abstract)

P. Coene , IMEC vzw
D. Verkest , IMEC vzw, Katholieke Universiteit Leuven and Vrije Universiteit Brussel
S. Vernalde , IMEC vzw
V. Nollet , IMEC vzw
R. Lauwereins , IMEC vzw and Katholieke Universiteit Leuven
J-Y. Mignolet , IMEC vzw
pp. 10986
10C: Advances in Test Pattern Generation

RTL Test Pattern Generation for High Quality Loosely Deterministic BIST (Abstract)

J. M. Fernandes , IST / INESC-ID
I. C. Teixeira , IST / INESC-ID
J. P. Teixeira , IST / INESC-ID
M. B. Santos , IST / INESC-ID
pp. 10994

Fully Automatic Test Program Generation for Microprocessor Cores (Abstract)

G. Cumani , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
F. Corno , Politecnico di Torino
G. Squillero , Politecnico di Torino
pp. 11006

On the Characterization of Hard-to-Detect Bridging Faults (Abstract)

Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
Sandip Kundu , Intel Corp.
pp. 11012
10D: Analogue and Digital Simulation

The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method (Abstract)

Charlie Chung-Ping Chen , University of Wisconsin at Madison
Yu-Min Lee , University of Wisconsin at Madison
pp. 11020

Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching (Abstract)

Jianwen Zhu , University of Toronto
Zhong Wang , University of Toronto
pp. 11026

A Fast Algorithm for the Layout Based Electro-Thermal Simulation (Abstract)

A. Poppe , Budapest University of Technology and Economics
M. Rencz , Budapest University of Technology and Economics
V. Székely , Budapest University of Technology and Economics
pp. 11032

Platform-Based Testbench Generation (Abstract)

R. Henftling , Infineon Technologies AG
M. Bauer , Infineon Technologies AG
A. Zinn , Infineon Technologies AG
W. Ecker , Infineon Technologies AG
M. Zambaldi , Infineon Technologies AG
pp. 11038
10E: Low Power Software (Embedded Software Forum)

Dynamic Functional Unit Assignment for Low Power (Abstract)

Diana Marculescu , Carnegie Mellon University
Natasha Reeves , University of Maryland at College Park
Rajeev Barua , University of Maryland at College Park
Steve Haga , University of Maryland at College Park
pp. 11052

Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors (Abstract)

Dan Nicolaescu , University of California at Irvine
Alex Veidenbaum , University of California at Irvine
Alex Nicolau , University of California at Irvine
pp. 11064
10F: Application Specific Memory Synthesis

Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations (Abstract)

F. Catthoor , Katholieke University Leuven
H. Corporaal , Technische University Endhoven
pp. 11070

Mesh Partitioning Approach to Energy Efficient Data Layout (Abstract)

Peter Y.K. Cheung , Imperial College of Science, Technology and Medicine
Sambuddhi Hettiaratchi , Imperial College of Science, Technology and Medicine
pp. 11076

On-chip Stack Based Memory Organization for Low Power Embedded Architectures (Abstract)

Mahesh Mamidipaka , University of California at Irvine
Nikil Dutt , University of California at Irvine
pp. 11082
4P: CAD for Analogue Design, Design Methodologies and Physical Design

Figure of Merit Based Selection of A/D Converters (PDF)

Georges Gielen , K.U.Leuven ESAT-MICAS
Martin Vogels , K.U.Leuven ESAT-MICAS
pp. 11090

XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines (PDF)

Martin Padeffke , Friedrich-Alexander-University of Erlangen-Nuremberg
Oliver Kraus , Friedrich-Alexander-University of Erlangen-Nuremberg
pp. 11092

Multithreaded Synchronous Data Flow Simulation (PDF)

Johnson S. Kin , Agilent Technologies, Inc.
José Luis Pino , Agilent Technologies, Inc.
pp. 11094

PLFire: A Visualization Tool for Asynchronous Phased Logic Designs (PDF)

K. Fazel , Southern Methodist University
R. B. Reese , Mississippi State University
M. A. Thornton , Southern Methodist University
pp. 11096

Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering (PDF)

Gaurav Gothoskar , State University of New York at Stony Brook
Alex Doboli , State University of New York at Stony Brook
Simona Doboli , Hofstra University
pp. 11098

Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology (PDF)

Abhijit K. Deb , Royal Institute of Technology
Axel Jantsch , Royal Institute of Technology
Johnny Öberg , Royal Institute of Technology
pp. 11100

A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs (PDF)

Jennifer Y.-L Lo , Tsing Hua University
Wu-An Kuo , Tsing Hua University
Ting Ting Hwang , Tsing Hua University
Allen C.-H. Wu , Tsing Hua University
pp. 11102

LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks (PDF)

Sergio Bampi , Federal University of Rio Grande do Sul
Alesssandro Girardi , Federal University of Rio Grande do Sul
pp. 11106

Symbolic Analysis of Nonlinear Analog Circuits (PDF)

C.-J.Richard Shi , University of Washington
Kartikeya Mayaram , Oregon State University
Alicia Manthe , University of Washington
Zhao Li , University of Washington
pp. 11108

Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects (PDF)

Gerd Mrozynski , University of Paderborn
Oliver Stübbe , University of Paderborn
Jürgen Schrage , Siemens SBS
Jürgen Teich , University of Paderborn
Jens Gerling , Zuken EMC-Technology Center
pp. 11110

A New Crosstalk Noise Model for DOMINO Logic Circuits (PDF)

Kaushik Roy , Purdue University
Seung Hoon Choi , Purdue University
pp. 11112

Modeling Noise Transfer Characteristic of Dynamic Logic Gates (PDF)

Pinaki Mazumder , University of Michigan
Li Ding , University of Michigan
pp. 11114
5P: Reconfigurable Computing and Systems Design

Heterogeneous Programmable Logic Block Architectures (PDF)

L. Pileggi , Carnegie Mellon University
K. Y. Tong , Carnegie Mellon University
C. Patel , Carnegie Mellon University
H. Schmit , Carnegie Mellon University
V. Chandra , Carnegie Mellon University
A. Koorapaty , Carnegie Mellon University
pp. 11118

An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration (PDF)

Alexander Thomas , Universitaet Karlsruhe
Martin Vorbach , PACT XPP Technologies AG
Jürgen Becker , Universitaet Karlsruhe
Volker Baumgarte , PACT XPP Technologies AG
pp. 11120

Mapping Applications to an FPFA Tile (PDF)

Yuanqing Guo , University of Twente
Gerard J.M. Smit , University of Twente
Thijs Krol , University of Twente
Michèl A.J. Rosien , University of Twente
pp. 11124

Load Distribution with the Proximity Congestion Awareness in a Network on Chip (PDF)

Erland Nilsson , Royal Institute of Technology
Mikael Millberg , Royal Institute of Technology
Johnny Öberg , Royal Institute of Technology
Axel Jantsch , Royal Institute of Technology
pp. 11126

Micro-Network for SoC: Implementation of a 32-Port SPIN network (PDF)

Adrijean Andriahantenaina , Pierre and Marie Curie University
Alain Greiner , Pierre and Marie Curie University
pp. 11128

A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems (PDF)

Mauro Zanella , University of Paderborn
Christophe Bobda , University of Paderborn
Thomas Lehmann , University of Paderborn
Achim Rettberg , University of Paderborn
pp. 11130

Library Functions Timing Characterization for Source-Level Analysis (PDF)

C. Brandolese , Politecnico di Milano
D. Sciuto , Politecnico di Milano
F. Salice , Politecnico di Milano
W. Fornaciari , Politecnico di Milano
pp. 11132

G-MAC: An Application-Specific MAC/Co-Processor Synthesizer (PDF)

Allen C.-H. Wu , Tsing Hua University
Alex C.-Y. Chang , Tsing Hua University
TingTing Hwang , Tsing Hua University
Wu-An Kuo , Tsing Hua University
pp. 11134

Power Constrained High-Level Synthesis of Battery Powered Digital Systems (PDF)

J. Madsen , Technical University of Denmark
S. F. Nielsen , Technical University of Denmark
pp. 11136

PARLAK: Parametrized Lock Cache Generator (PDF)

Vincent J. Mooney , Georgia Institute of Technology
Bilge E. S. Akgul , Georgia Institute of Technology
pp. 11138

A Secure Web-Based Framework for Electronic System Level Design (PDF)

Tom Kazmierski , University of Southampton
Xing Q Yang , University of Southampton
pp. 11140
6P: Low Power Design and Estimation, Verification and Testing

Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor (PDF)

P. Op de Beeck , IMEC and Katholieke Universiteit Leuven
G. Deconinck , Katholieke Universiteit Leuven
M. Miranda , IMEC
F. Catthoor , IMEC and Katholieke Universiteit Leuven
C. Ghez , IMEC
pp. 11144

Compiler Support for Reducing Leakage Energy Consumption (PDF)

V. De , Penn State University and Intel Research Labs
W. Zhang , Penn State University
N. Vijaykrishnan , Penn State University
M. J. Irwin , Penn State University
M. Kandemir , Penn State University
pp. 11146

An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries (PDF)

Massoud Pedram , University of Southern California
Peng Rong , University of Southern California
pp. 11148

Decomposition of Extended Finite State Machine for Low Power Design (PDF)

MingHung Lee , National Tsing Hua University
Shi-Yu Huang , National Tsing Hua University
TingTing Hwang , National Tsing Hua University
pp. 11152

Equisolvability of Series vs. Controller?s Topology in Synchronous Language Equations (PDF)

Tiziano Villa , PARADES
Robert K. Brayton , University of California at Berkeley
Nina Yevtushenko , Tomsk State University
Alberto L. Sangiovanni-Vincentelli , University of California at Berkeley
pp. 11154

Using RTL Statespace Information and State Encoding for Induction Based Property Checking (PDF)

Markus Wedler , University of Kaiserslautern
Wolfgang Kunz , University of Kaiserslautern
Dominik Stoffel , University of Kaiserslautern
pp. 11156

Combining Simulation and Guided Traversal for the Verification of Concurrent Systems (PDF)

Enric Pastor , Technical University of Catalonia
Marco A. Peña , Technical University of Catalonia
pp. 11158
7P: System Level Design and Specification and Testing Techniques

SAT-Based Techniques in System Synthesis (PDF)

Jürgen Teich , University of Erlangen-Nuremberg
Christian Haubelt , University of Erlangen-Nuremberg
Burkhard Monien , University of Paderborn
Rainer Feldmann , University of Paderborn
pp. 11168

Refinement of Mixed-Signal Systems with SystemC (PDF)

Ch. Meise , University Frankfurt
K. Waldschmidt , University Frankfurt
Ch. Grimm , University Frankfurt
W. Heupke , University Frankfurt
pp. 11170

Polychrony for Refinement-Based Design (PDF)

Jean-Pierre Talpin , Inria/Irisa
Frédéric Doucet , University of California at San Diego
Paul Guernic , Inria/Irisa
Rajesh Gupta , University of California at San Diego
Sandeep Kumar Shukla , Virgina Tech
pp. 11172

Automatic Generation of Simulation Monitors from Quantitative Constraint Formula (PDF)

Yosinori Watanabe , Cadence Berkeley Laboratories
Felice Balarin , Cadence Berkeley Laboratories
Xi Chen , University of California at Riverside
Harry Hsieh , University of California at Riverside
pp. 11174

Consequences of RAM Bitline Twisting for Test Coverage (PDF)

Ad.J. van de Goor , Delft University of Technology
Ivo Schanstra , Infineon Technologies AG
pp. 11176

An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing Scheme (PDF)

C. Marzocca , Politecnico di Bari
G. Matarrese , Politecnico di Bari
F. Corsi , Politecnico di Bari
pp. 11178

Comparison of Test Pattern Decompression Techniques (PDF)

Ondřej Novák , Technical University Liberec
pp. 11182

Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST (PDF)

Ilia Polian , Albert-Ludwigs-University
Bernd Becker , Albert-Ludwigs-University
Sudhakar M. Reddy , University of Iowa
pp. 11184

Test Data Compression Based on Output Dependence (PDF)

Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
pp. 11186
Author Index

Author Index (PDF)

pp. 11191
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