The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2003)
Munich, Germany
Mar. 3, 2003 to Mar. 7, 2003
ISSN: 1530-1591
ISBN: 0-7695-1870-2
TABLE OF CONTENTS
Introduction

Reviewers (PDF)

pp. xxxv

Welcome to Date 2003 (PDF)

pp. xxxviii

Best Paper Awards (PDF)

pp. xxxix

Tutorials (PDF)

pp. xl

Master Courses (PDF)

pp. xliii
Plenary: Keynote Session

IC Design Challenges for Ambient Intelligence (Abstract)

Emile Aarts , Philips Research Laboratories
Raf Roovers , Philips Research Laboratories
pp. 10002

Semiconductor Challenges (PDF)

Andrea Cuomo , STMicroelectronics
pp. 10008
1A: Hot Topic:Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts

Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts (Abstract)

Menno Lindwer , Philips Research
Diana Marculescu , Carnegie Mellon University
Twan Basten , Eindhoven University of Technology
Rainer Zimmermann , European Commission
Radu Marculescu , Carnegie Mellon University
Stefan Jung , Infineon Technologies
Eugenio Cantatore , Philips Research
pp. 10010
1B: Energy-Efficient Memory Systems

Improving the Efficiency of Memory Partitioning by Address Clustering (Abstract)

Alberto Macii , Politecnico di Torino
Enrico Macii , Politecnico di Torino
Massimo Poncino , Università di Verona
pp. 10018

A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors (Abstract)

Alberto Macii , Politecnico di Torino
Enrico Macii , Politecnico di Torino
Fabrizio Crudo , STMicroelectronics
Roberto Zafalon , STMicroelectronics
pp. 10024

Power Efficiency through Application-Specific Instruction Memory Transformations (Abstract)

Peter Petrov , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 10030

Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures (Abstract)

M. Sánchez-Élez , Universidad Complutense de Madrid
M. Fernández , Universidad Complutense de Madrid
M. Anido , Federal University do Rio de Janeiro
H. Du , University of California at Irvine
N. Bagherzadeh , University of California at Irvine
R. Hermida , Universidad Complutense de Madrid
pp. 10036
1C: Embedded Tutorial: Circuit, Platform Design and Test Challenges in Technologies Beyond 90nm

Circuit and Platform Design Challenges in Technologies beyond 90nm (Abstract)

Bill Grundmann , Intel Corporation
Rajesh Galivanche , Intel Corporation
Sandip Kundu , Intel Corporation
pp. 10044
1F: Uncertainty

Global Wire Bus Configuration with Minimum Delay Uncertainty (Abstract)

Li-Da Huang , University of Texas at Austin
Hung-Ming Chen , University of Texas at Austin
D. F. Wong , University of Illinois at Urbana-Champaign
pp. 10050

Statistical Timing Analysis Using Bounds (Abstract)

Aseem Agarwal , University of Michigan
David Blaauw , University of Michigan
Vladimir Zolotov , Motorola, Inc.
Sarma Vrudhula , University of Arizona
pp. 10062

Reduced Delay Uncertainty in High Performance Clock Distribution Networks (Abstract)

Dimitrios Velenis , University of Rochester
Marios C. Papaefthymiou , University of Michigan
Eby G. Friedman , University of Rochester
pp. 10068
2A: Hot Topic: Scaling into Ambient Intelligence

Scaling into Ambient Intelligence (Abstract)

Twan Basten , Eindhoven University of Technology
Luca Benini , University of Bologna
Anantha Chandrakasan , Massachusetts Institute of Technology
Menno Lindwer , Philips Research Laboratories
Jie Liu , Palo Alto Research Center
Rex Min , Massachusetts Institute of Technology
Feng Zhao , Palo Alto Research Center
pp. 10076

IC design challenges for ambient intelligence (PDF)

E. Aarts , Philips Res. Labs., Eindhoven, Netherlands
R. Roovers , Philips Res. Labs., Eindhoven, Netherlands
pp. 2-7

Improving the efficiency of memory partitioning by address clustering (PDF)

A. Macii , Politecnico di Torino, Italy
E. Macii , Politecnico di Torino, Italy
pp. 18-23

A new algorithm for energy-driven data compression in VLIW embedded processors (PDF)

A. Macii , Politecnico di Torino, Italy
E. Macii , Politecnico di Torino, Italy
pp. 24-29

Power efficiency through application-specific instruction memory transformations (PDF)

P. Petrov , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 30-35

Low energy data management for different on-chip memory levels in multi-context reconfigurable architectures (PDF)

M. Sanchez-Elez , Dept. de Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
M. Fernandez , Dept. de Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
pp. 36-41

Circuit and platform design challenges in technologies beyond 90nm (PDF)

B. Grundmann , Dept. of Design Technol., Intel Corp., Hillsboro, OR, USA
R. Galivanche , Dept. of Design Technol., Intel Corp., Hillsboro, OR, USA
S. Kundu , Dept. of Design Technol., Intel Corp., Hillsboro, OR, USA
pp. 44-47

Global wire bus configuration with minimum delay uncertainty (PDF)

Li-Da Huang , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Hung-Ming Chen , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 50-55

Timing verification with crosstalk for transparently latched circuits (PDF)

Hai Zhou , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 56-61

Statistical timing analysis using bounds [IC verification] (PDF)

A. Agarwal , Michigan Univ., Ann Arbor, MI, USA
D. Blaauw , Michigan Univ., Ann Arbor, MI, USA
pp. 62-67

Masking the energy behavior of DES encryption [smart cards] (PDF)

H. Saputra , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
N. Vijaykrishnan , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 84-89

Scheduling and mapping of conditional task graphs for the synthesis of low power embedded systems (PDF)

Dong Wu , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
B.M. Al-Hashimi , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
pp. 90-95

Synthesis of application-specific highly-efficient multi-mode systems for low-power applications (PDF)

Lih-Yih Chiou , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
S. Bhunia , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 96-101

Virtual compression through test vector stitching for scan based designs (PDF)

Wenjing Rao , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 104-109

Test pattern compression using prelude vectors in fan-out scan chain with feedback architecture (PDF)

Nahmsuk Oh , Synopsys Inc., Mountain View, CA, USA
R. Kapur , Synopsys Inc., Mountain View, CA, USA
T.W. Williams , Synopsys Inc., Mountain View, CA, USA
J. Sproch , Synopsys Inc., Mountain View, CA, USA
pp. 110-115

RTOS modeling for system level design (PDF)

A. Gerstlauer , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
Haobo Yu , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
D.D. Gajski , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 130-135

Systematic embedded software generation from SystemC (PDF)

F. Herrera , TEISA Dept., Cantabria Univ., Santander, Spain
H. Posadas , TEISA Dept., Cantabria Univ., Santander, Spain
P. Sanchez , TEISA Dept., Cantabria Univ., Santander, Spain
E. Villar , TEISA Dept., Cantabria Univ., Santander, Spain
pp. 142-147

Approximation approach for timing jitter characterization in circuit simulators (PDF)

M.M. Gourary , IPPM, Acad. of Sci., Moscow, Russia
S.G. Rusakov , IPPM, Acad. of Sci., Moscow, Russia
S.L. Ulyanov , IPPM, Acad. of Sci., Moscow, Russia
M.M. Zharov , IPPM, Acad. of Sci., Moscow, Russia
pp. 156-161

A model of computation for continuous-time /spl Delta//spl Sigma/ modulators (PDF)

E. Martens , Dept. of Electr. Eng., Katholieke Univ., Leuven, Belgium
G. Gielen , Dept. of Electr. Eng., Katholieke Univ., Leuven, Belgium
pp. 162-167

Behavioural modelling and simulation of /spl Sigma//spl Delta/ modulators using hardware description languages (PDF)

R. Castro-Lopez , IMSE-CNM, Sevilla, Spain
F.V. Ferandez , IMSE-CNM, Sevilla, Spain
F. Medeiro , IMSE-CNM, Sevilla, Spain
A. Rodriguez-Vazquez , IMSE-CNM, Sevilla, Spain
pp. 168-173

Schedulability analysis and optimization for the synthesis of multi-cluster distributed embedded systems (PDF)

P. Pop , Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
P. Eles , Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
Zebo Peng , Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
pp. 184-189

A general framework for analysing system properties in platform-based embedded system designs (PDF)

S. Chakraborty , Swiss Fed. Inst. of Technol., Zurich, Switzerland
S. Kunzli , Swiss Fed. Inst. of Technol., Zurich, Switzerland
L. Thiele , Swiss Fed. Inst. of Technol., Zurich, Switzerland
pp. 190-195

Rapid prototyping of flexible embedded systems on multi-DSP architectures (PDF)

B. Rinner , Inst. fur Technische Informatik, Technische Univ. Graz, Austria
M. Schmid , Inst. fur Technische Informatik, Technische Univ. Graz, Austria
R. Weiss , Inst. fur Technische Informatik, Technische Univ. Graz, Austria
pp. 204-209

DFT for testing high-performance pipelined circuits with slow-speed testers (PDF)

M. Nummer , Waterloo Univ., Ont., Canada
M. Sachdev , Waterloo Univ., Ont., Canada
pp. 212-217

Extending JTAG for testing signal integrity in SoCs (PDF)

N. Ahmed , Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA
M. Tehranipour , Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA
M. Nourani , Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA
pp. 218-223

A partition-based approach for identifying failing scan cells in scan-BIST with applications to system-on-chip fault diagnosis (PDF)

Chunsheng Liu , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
K. Chakrabarty , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 230-235

High-level allocation to minimize internal hardware wastage [high-level synthesis] (PDF)

M.C. Molina , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
J.M. Mendias , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
R. Hermida , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
pp. 264-269

Dynamic conditional branch balancing during the high-level synthesis of control-intensive designs (PDF)

S. Cupta , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
N. Dutt , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 270-275

Distributed synchronous control units for dataflow graphs under allocation of telescopic arithmetic units (PDF)

E. Kim , Dependable & High-Performance Comput. Lab., Univ. of Tokyo, Japan
H. Saito , Dependable & High-Performance Comput. Lab., Univ. of Tokyo, Japan
pp. 276-281

Automated bus generation for multiprocessor SoC design (PDF)

Kyeong Keol Ryu , Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
V.J.I.I.I. Mooney , Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 282-287

Online scheduling for block-partitioned reconfigurable devices (PDF)

H. Walder , Comput. Eng. & Networks Lab, Swiss Fed. Inst. of Technol., Zurich, Switzerland
M. Platzner , Comput. Eng. & Networks Lab, Swiss Fed. Inst. of Technol., Zurich, Switzerland
pp. 290-295

Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling (PDF)

Bingfeng Mei , IMEC vzw, Leuven, Belgium
S. Vernalde , IMEC vzw, Leuven, Belgium
D. Verkest , IMEC vzw, Leuven, Belgium
H. De Man , IMEC vzw, Leuven, Belgium
R. Lauwereins , IMEC vzw, Leuven, Belgium
pp. 296-301

A method of test generation for path delay faults using stuck-at fault test generation algorithms (PDF)

S. Ohtake , Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
pp. 310-315

A novel, low-cost algorithm for sequentially untestable fault identification (PDF)

M. Syal , Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
M.S. Hsiao , Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
pp. 316-321

Non-enumerative path delay fault diagnosis [logic testing] (PDF)

S. Padmanaban , Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
S. Tragoudas , Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
pp. 322-327

Delay defect diagnosis based upon statistical timing models - the first step [logic testing] (PDF)

A. Krstic , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
L.-C. Wang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Kwang-Ting Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 328-333

Hardware/software partitioning of operating systems [SoC applications] (PDF)

V.J. Mooney , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 338-339

Embedded software in digital AM-FM chipset (PDF)

M. Sarlotte , THALES Commun., Gennevilliers, France
B. Candaele , THALES Commun., Gennevilliers, France
J. Quevremont , THALES Commun., Gennevilliers, France
D. Merel , THALES Commun., Gennevilliers, France
pp. 340-341
5E: Software Optimisation for Embedded Systems (Embedded Software Forum)

Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip (PDF)

E. Rijpkema , Philips Res. Labs., Eindhoven, Netherlands
K.G.W. Goossens , Philips Res. Labs., Eindhoven, Netherlands
A. Radulescu , Philips Res. Labs., Eindhoven, Netherlands
J. Dielissen , Philips Res. Labs., Eindhoven, Netherlands
J. van Meerbergen , Philips Res. Labs., Eindhoven, Netherlands
P. Wielage , Philips Res. Labs., Eindhoven, Netherlands
E. Waterlander , Philips Res. Labs., Eindhoven, Netherlands
pp. 350-355

Communication centric architectures for turbo-decoding on embedded multiprocessors (PDF)

F. Gilbert , Microelectron. Syst. Design Res. Group, Kaiserslautern Univ., Germany
M.J. Thul , Microelectron. Syst. Design Res. Group, Kaiserslautern Univ., Germany
N. Wehn , Microelectron. Syst. Design Res. Group, Kaiserslautern Univ., Germany
pp. 356-361

Development and application of design transformations in ForSyDe [high level synthesis] (PDF)

I. Sander , R. Inst. of Technol., Stockholm, Sweden
A. Jantsch , R. Inst. of Technol., Stockholm, Sweden
Zhonghai Lu , R. Inst. of Technol., Stockholm, Sweden
pp. 364-369

System level specification in Lava (PDF)

S. Singh , Xilinx Inc., San Jose, CA, USA
pp. 370-375

Formal semantics of synchronous SystemC (PDF)

A. Salem , Comput. & Syst. Eng. Dept, Ain Shams Univ., Cairo, Egypt
pp. 376-381

SystemC-AMS requirements, design objectives and rationale (PDF)

A. Vachoux , Microelectron. Syst. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
pp. 388-393

Parallel processing architectures for reconfigurable systems (PDF)

K.A. Vissers , CTO, Chameleon Syst. Inc, Berkeley, CA, USA
pp. 396-397

A lightweight approach for embedded reconfiguration of FPGAs (PDF)

B. Blodget , Xilinx Inc., San Jose, CA, USA
S. McMillan , Xilinx Inc., San Jose, CA, USA
P. Lysaght , Xilinx Inc., San Jose, CA, USA
pp. 399-400

Creating value through test (PDF)

E.J. Marinissen , Philips Res. Labs., Eindhoven, Netherlands
B. Vermeulen , Philips Res. Labs., Eindhoven, Netherlands
pp. 402-407

Control flow driven splitting of loop nests at the source code level (PDF)

H. Falk , Dept. of Comput. Sci., Dortmund Univ., Germany
P. Marwedel , Dept. of Comput. Sci., Dortmund Univ., Germany
pp. 410-415

Data space oriented scheduling in embedded systems (PDF)

M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
G. Chen , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
W. Zhang , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 416-421

Compiler-directed ILP extraction for clustered VLIW/EPIC machines: predication, speculation and modulo scheduling (PDF)

S. Pillai , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M.F. Jacome , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 422-427

An efficient hash table based approach to avoid state space explosion in history driven quasi-static scheduling (PDF)

A.G. Lomena , Electron. Eng. Dept., Tech. Univ. of Madrid, Spain
M. Lopez-Vallejo , Electron. Eng. Dept., Tech. Univ. of Madrid, Spain
pp. 428-433

Interconnect planning with local area constrained retiming [logic IC layout] (PDF)

Ruibing Lu , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Cheng-Kok Koh , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 442-447

A novel metric for interconnect architecture performance (PDF)

P. Dasgupta , CSE Dept., California Univ. San Diego, La Jolla, CA, USA
A.B. Kahng , CSE Dept., California Univ. San Diego, La Jolla, CA, USA
pp. 448-453

Specification of non-functional intellectual property components (PDF)

Jianwen Zhu , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Wai Sum Mong , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 456-461

Profile-driven selective code compression [embedded systems] (PDF)

Yuan Xie , Dept. of Electr. Eng., Princeton Univ., NJ, USA
W. Wolf , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 462-467

Design and analysis of a programmable single-chip architecture for DVB-T base-band receiver (PDF)

Chengzhi Pan , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
N. Bagherzadeh , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
A.H. Kamalizad , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
A. Koohi , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
pp. 468-473

RF-BIST: loopback spectral signature analysis (PDF)

D. Lupea , Inst. fur Verkehrsinformationssysteme, Technische Univ. Dresden, Germany
U. Pursche , Inst. fur Verkehrsinformationssysteme, Technische Univ. Dresden, Germany
H.-J. Jentschel , Inst. fur Verkehrsinformationssysteme, Technische Univ. Dresden, Germany
pp. 478-483

Optimizing stresses for testing DRAM cell defects using electrical simulation (PDF)

Z. Al-Ars , Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands
A.J. van de Goor , Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands
pp. 484-489

On modeling cross-talk faults [VLSI circuits] (PDF)

S. Zachariah , Intel Corp., Santa Clara, CA, USA
Yi-Shing Chang , Intel Corp., Santa Clara, CA, USA
S. Kundu , Intel Corp., Santa Clara, CA, USA
C. Tirumurti , Intel Corp., Santa Clara, CA, USA
pp. 490-495

Pre-characterization free, efficient power/performance analysis of embedded and general purpose software applications (PDF)

V.S.R. Rapaka , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D. Marculescu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 504-509

Runtime code parallelization for on-chip multiprocessors (PDF)

M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
W. Zhang , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 510-515

Modeling and evaluation of substrate noise induced by interconnects (PDF)

F. Martorell , Electron. Eng. Dept, Univ. Politecnica de Catalunya, Barcelona, Spain
D. Mateo , Electron. Eng. Dept, Univ. Politecnica de Catalunya, Barcelona, Spain
X. Aragones , Electron. Eng. Dept, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 524-529

Model-order reduction based on Prony's method (PDF)

M.M. Mansour , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
A. Mehrotra , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 530-535

Combined FDTD/macromodel simulation of interconnected digital devices (PDF)

S. Grivet-Talocia , Dipt. Elettronica, Politecnico di Torino, Italy
I.S. Stievano , Dipt. Elettronica, Politecnico di Torino, Italy
I.A. Maio , Dipt. Elettronica, Politecnico di Torino, Italy
F.G. Canavero , Dipt. Elettronica, Politecnico di Torino, Italy
pp. 536-541
7F: Mixed-Signal Design Techniques

Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters (Abstract)

Miquel Albiol , Universitat Polit?cnica de Catalunya
José Luis González , Universitat Polit?cnica de Catalunya
Eduard Alarcón , Universitat Polit?cnica de Catalunya
pp. 10636

Instruction set emulation for rapid prototyping of SoCs (PDF)

J. Schnerr , FZI Forschungszentrum Informatik, Karlsruhe, Germany
G. Haug , FZI Forschungszentrum Informatik, Karlsruhe, Germany
W. Rosenstiel , FZI Forschungszentrum Informatik, Karlsruhe, Germany
pp. 562-567

Hardware/software design space exploration for a reconfigurable processor (PDF)

A. La Rosa , Dipt. di Elettronica, Politecnico di Torino, Italy
L. Lavagno , Dipt. di Elettronica, Politecnico di Torino, Italy
C. Passerone , Dipt. di Elettronica, Politecnico di Torino, Italy
pp. 570-575

From C programs to the configure-execute model (PDF)

J.M.P. Cardoso , Univ. do Algarve, Faro, Portugal
pp. 576-581

Optimal reconfiguration functions for column or data-bit built-in self-repair (PDF)

M. Nicolaidis , iRoC Technol., Grenoble, France
N. Achouri , iRoC Technol., Grenoble, France
S. Boutobza , iRoC Technol., Grenoble, France
pp. 590-595

Versatile high-level synthesis of self-checking datapaths using an on-line testability metric (PDF)

P. Oikonomakos , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
M. Zwolinski , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
B.M. Al-Hashimi , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
pp. 596-601

An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessor (PDF)

M. Rebaudengo , Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
M.S. Reorda , Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
M. Violante , Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
pp. 602-607

High speed and highly testable parallel two-rail code checker (PDF)

M. Omana , DEIS, Bologna Univ., Italy
D. Rossi , DEIS, Bologna Univ., Italy
C. Metra , DEIS, Bologna Univ., Italy
pp. 608-613

Analysis and white-box modeling of weakly nonlinear time-varying circuits (PDF)

P. Dobrovolny , IMEC, Leuven, Belgium
G. Vandersteen , IMEC, Leuven, Belgium
P. Wambacq , IMEC, Leuven, Belgium
S. Donnay , IMEC, Leuven, Belgium
pp. 624-629

Linear model-based error identification and calibration for data converters (PDF)

C. Wegener , Dept. of Microelectron. Eng., Univ. Coll. Cork, Ireland
M.P. Kennedy , Dept. of Microelectron. Eng., Univ. Coll. Cork, Ireland
pp. 630-635

Improved design methodology for high-speed high-accuracy current steering D/A converters (PDF)

M. Albiol , Electron. Eng. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain
J.L. Gonzalez , Electron. Eng. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain
E. Alarcon , Electron. Eng. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 636-641

Behavioral modeling and simulation of a mixed analog/digital automatic gain control loop in a 5 GHz WLAN receiver (PDF)

W. Eberle , IMEC, Leuven, Belgium
G. Vandersteen , IMEC, Leuven, Belgium
P. Wambacq , IMEC, Leuven, Belgium
S. Donnay , IMEC, Leuven, Belgium
pp. 642-647

Analytical design space exploration of caches for embedded systems (PDF)

A. Ghosh , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
T. Givargis , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 650-655

A first step towards Hw/Sw partitioning of UML specifications (PDF)

W. Fornaciari , Politecnico di Milano, Italy
P. Micheli , Politecnico di Milano, Italy
F. Salice , Politecnico di Milano, Italy
L. Zampella , Politecnico di Milano, Italy
pp. 668-673

Multi-granularity metrics for the era of strongly personalized SOCs (PDF)

Y. Le Moullec , Univ. de Bretagne Sud, Lorient, France
N.B. Amor , Univ. de Bretagne Sud, Lorient, France
J.-P. Diguet , Univ. de Bretagne Sud, Lorient, France
pp. 674-679

Energy estimation for extensible processors (PDF)

Yunsi Fei , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 682-687

Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures (PDF)

Jingcao Hu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R. Marculescu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 688-693

Chromatic encoding: a low power encoding technique for digital visual interface (PDF)

Wei-Chung Cheng , Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Univ. of Southern California, Los Angeles, CA, USA
pp. 694-699

MRPF: an architectural transformation for synthesis of high-performance and low-power digital filters (PDF)

Hunsoo Choo , Electr. & Comput. Eng. Dept., Purdue Univ., West Lafayette, IN, USA
pp. 700-705

A P1500-compatible programmable BIST approach for the test of embedded flash memories (PDF)

P. Bernardi , Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
M. Rebaudengo , Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
M.S. Reorda , Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
M. Violante , Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
pp. 720-725

Test data compression: the system integrator's perspective (PDF)

P.T. Gonciari , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
B.M. Al-Hashimi , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
pp. 726-731

Time domain multiplexed TAM: implementation and comparison (PDF)

Z.S. Ebadi , Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada
A. Ivanov , Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada
pp. 732-737

Layout-driven SOC test architecture design for test time and wire length minimization (PDF)

S.K. Goel , Philips Res. Labs., Eindhoven, Netherlands
E.J. Marinissen , Philips Res. Labs., Eindhoven, Netherlands
pp. 738-743

Delay fault testing of core-based systems-on-a-chip (PDF)

Qiang Xu , Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada
N. Nicolici , Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada
pp. 744-749

Reducing multi-valued algebraic operations to binary (PDF)

J.-H.R. Jiang , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 752-757

Combination of lower bounds in exact BDD minimization (PDF)

R. Ebendt , Dept. of Comput. Sci., Kaiserslautern Univ., Germany
pp. 758-763

Exploring high bandwidth pipelined cache architecture for scaled technology (PDF)

A. Agarwal , Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
T.N. Vijaykumar , Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 778-783

Enhancing speedup in network processing applications by exploiting instruction reuse with flow aggregation (PDF)

G. Surendra , CAD Lab., Indian Inst. of Sci., Bangalore, India
S. Banerjee , CAD Lab., Indian Inst. of Sci., Bangalore, India
S.K. Nandy , CAD Lab., Indian Inst. of Sci., Bangalore, India
pp. 784-789

On-chip stochastic communication [SoC applications] (PDF)

T. Dumitras , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R. Marculescu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 790-795

An integrated approach for improving cache behavior (PDF)

G. Memik , Dept. of Electr. Eng., UCLA, Los Angeles, CA, USA
pp. 796-801

Rapid configuration and instruction selection for an ASIP: a case study (PDF)

N. Cheung , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 802-807

Local search for Boolean relations on the basis of unit propagation (PDF)

Y. Novikov , United Inst. of Informatics Problems, Acad. of Sci., Mogilev, Belarus
pp. 810-815

Set manipulation with Boolean functional vectors for symbolic reachability analysis (PDF)

A. Goel , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 816-821

Efficient preimage computation using a novel success-driven ATPG (PDF)

Shuo Sheng , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 822-827

Using formal techniques to debug the AMBA system-on-chip bus protocol (PDF)

A. Roychoudhury , Sch. of Comput., Nat. Univ. of Singapore, Singapore
T. Mitra , Sch. of Comput., Nat. Univ. of Singapore, Singapore
S.R. Karri , Sch. of Comput., Nat. Univ. of Singapore, Singapore
pp. 828-833

Power/ground mesh area optimization using multigrid-based technique [IC design] (PDF)

Kai Wang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
M. Marek-Sadowska , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 850-855

A new and efficient congestion evaluation model in floorplanning: wire density control with twin binary trees (PDF)

S.T.W. Lai , Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, China
E.F.Y. Young , Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, China
pp. 856-861

Crosstalk reduction in area routing (PDF)

R.M. Smey , Binghamton Univ., NY, USA
pp. 862-867

Area fill generation with inherent data volume reduction (PDF)

Yu Chen , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 868-873

A circuit SAT solver with signal correlation guided learning (PDF)

Feng Lu , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
L.-C. Wang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Kwang-Ting Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 892-897

Improving SAT-based bounded model checking by means of BDD-based approximate traversals (PDF)

G. Cabodi , Dip. di Autornatica e Informatica, Politecnico di Torino, Turin, Italy
S. Nocco , Dip. di Autornatica e Informatica, Politecnico di Torino, Turin, Italy
S. Quer , Dip. di Autornatica e Informatica, Politecnico di Torino, Turin, Italy
pp. 898-903

Generalized data transformations for enhancing cache behavior (PDF)

V. De La Luz , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
I. Kadayif , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 906-911

Software streaming via block streaming (PDF)

P. Kuacharoen , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
V.J. Mooney , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
V.K. Madisetti , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 912-917

Energy-aware adaptive checkpointing in embedded real-time systems (PDF)

Ying Zhang , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
K. Chakrabarty , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 918-923

Visualization and resolution of coding conflicts in asynchronous circuit design (PDF)

A. Madalinski , Sch. of Electr., Electron. & Comput. Eng., Newcastle upon Tyne Univ., UK
A. Bystrov , Sch. of Electr., Electron. & Comput. Eng., Newcastle upon Tyne Univ., UK
pp. 926-931

STG optimisation in the direct mapping of asynchronous circuits (PDF)

D. Sokolov , Sch. of Electr., Electron. & Comput. Eng., Newcastle upon Tyne Univ., UK
A. Bystrov , Sch. of Electr., Electron. & Comput. Eng., Newcastle upon Tyne Univ., UK
A. Yakovlev , Sch. of Electr., Electron. & Comput. Eng., Newcastle upon Tyne Univ., UK
pp. 932-937

Ubiquitous access to reconfigurable hardware: application scenarios and implementation issues (PDF)

L.S. Indrusiak , Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 940-945

Dynamic tool integration in heterogeneous computer networks (PDF)

W. Mueller , Paderborn Univ., Germany
T. Schattkowsky , Paderborn Univ., Germany
pp. 946-951

Layered, multi-threaded, high-level performance design (PDF)

A.S. Cassidy , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.M. Paul , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D.E. Thomas , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 954-959

A co-design methodology for energy-efficient multi-mode embedded systems with consideration of mode execution probabilities (PDF)

M.T. Schmitz , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
B.M. Al-Hashimi , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
pp. 960-965

Processor/memory co-exploration on multiple abstraction levels (PDF)

G. Braun , Integrated Signal Process. Syst., Aachen, Germany
A. Wieferink , Integrated Signal Process. Syst., Aachen, Germany
O. Schliebusch , Integrated Signal Process. Syst., Aachen, Germany
R. Leupers , Integrated Signal Process. Syst., Aachen, Germany
H. Meyr , Integrated Signal Process. Syst., Aachen, Germany
pp. 966-971

Run-time management of logic resources on reconfigurable systems (PDF)

M.G. Gericota , Dept. of Electr. Eng., ISEP, Porto, Portugal
G.R. Alves , Dept. of Electr. Eng., ISEP, Porto, Portugal
pp. 974-979

Managing a reconfigurable processor in a general purpose workstation environment (PDF)

M. Dales , Dept. of Comput. Sci., Glasgow Univ., UK
pp. 980-985

Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip (PDF)

J.-Y. Mignolet , IMEC vzw, Leuven, Belgium
V. Nollet , IMEC vzw, Leuven, Belgium
P. Coene , IMEC vzw, Leuven, Belgium
D. Verkest , IMEC vzw, Leuven, Belgium
S. Vernalde , IMEC vzw, Leuven, Belgium
R. Lauwereins , IMEC vzw, Leuven, Belgium
pp. 986-991

RTL test pattern generation for high quality loosely deterministic BIST (PDF)

M.B. Santos , IST / INESC-M, Lisboa, Portugal
J.M. Fernandes , IST / INESC-M, Lisboa, Portugal
I.C. Teixeira , IST / INESC-M, Lisboa, Portugal
J.P. Teixeira , IST / INESC-M, Lisboa, Portugal
pp. 994-999

A new approach to test generation and test compaction for scan circuits (PDF)

I. Pomeranz , Sch. of Electr. & Comput. Eng., Purdue Univ., Lafayette, LA, USA
pp. 1000-1005

Fully automatic test program generation for microprocessor cores (PDF)

F. Corno , Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
G. Cumani , Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
M. Sonza Reorda , Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
G. Squillero , Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
pp. 1006-1011

On the characterization of hard-to-detect bridging faults (PDF)

I. Pomeranz , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 1012-1017

The power grid transient simulation in linear time based on 3D alternating-direction-implicit method (PDF)

Yu-Min Lee , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
C. Chung-Ping Chen , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 1020-1025

Transistor-level static timing analysis by piecewise quadratic waveform matching (PDF)

Zhong Wang , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Jianwen Zhu , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 1026-1031

A fast algorithm for the layout based electro-thermal simulation (PDF)

M. Rencz , Budapest Univ. of Technol. & Econ., Hungary
V. Szekely , Budapest Univ. of Technol. & Econ., Hungary
A. Poppe , Budapest Univ. of Technol. & Econ., Hungary
pp. 1032-1037

Platform-based testbench generation (PDF)

R. Henftling , Corporate Logic, Infineon Technol. AG, Munich, Germany
A. Zinn , Corporate Logic, Infineon Technol. AG, Munich, Germany
M. Bauer , Corporate Logic, Infineon Technol. AG, Munich, Germany
W. Ecker , Corporate Logic, Infineon Technol. AG, Munich, Germany
M. Zambaldi , Corporate Logic, Infineon Technol. AG, Munich, Germany
pp. 1038-1043

Dynamic functional unit assignment for low power (PDF)

S. Haga , Dept of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
N. Reeves , Dept of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
R. Barua , Dept of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
pp. 1052-1057

Implementation and evaluation of an on-demand parameter-passing strategy for reducing energy (PDF)

M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 1058-1063

Reducing power consumption for high-associativity data caches in embedded processors (PDF)

D. Nicolaescu , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
A. Veidenbaum , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
A. Nicolau , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 1064-1068

Layer assignment techniques for low energy in multi-layered memory organisations (PDF)

E. Brockmeyer , Technische Univ. Eindhoven, Netherlands
M. Miranda , Technische Univ. Eindhoven, Netherlands
F. Catthoor , Technische Univ. Eindhoven, Netherlands
pp. 1070-1075

Mesh partitioning approach to energy efficient data layout (PDF)

S. Hettiaratchi , Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
P.Y.K. Cheung , Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
pp. 1076-1081

On-chip stack based memory organization for low power embedded architectures (PDF)

M. Mamidipaka , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
N. Dutt , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 1082-1087

Figure of merit based selection of A/D converters (PDF)

M. Vogels , Katholieke Univ., Leuven, Belgium
G. Gielen , Katholieke Univ., Leuven, Belgium
pp. 1090-1091

PLFire: a visualization tool for asynchronous phased logic designs (PDF)

K. Fazel , Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
M.A. Thornton , Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
pp. 1096-1097

Simulation and analysis of embedded DSP systems using MASIC methodology (PDF)

A.K. Deb , Dept. of Microelectron. & Inf. Technol., R. Inst. of Technol., Kista, Sweden
J. Oberg , Dept. of Microelectron. & Inf. Technol., R. Inst. of Technol., Kista, Sweden
A. Jantsch , Dept. of Microelectron. & Inf. Technol., R. Inst. of Technol., Kista, Sweden
pp. 1100-1101

A custom-cell identification method for high-performance mixed standard/custom-cell designs (PDF)

J.Y.-L. Lo , Comput. Sci. Dept., Tsing Hua Univ., Hsin-Chu, Taiwan
Wu-An Kuo , Comput. Sci. Dept., Tsing Hua Univ., Hsin-Chu, Taiwan
A.C.-H. Wu , Comput. Sci. Dept., Tsing Hua Univ., Hsin-Chu, Taiwan
TingTing Hwang , Comput. Sci. Dept., Tsing Hua Univ., Hsin-Chu, Taiwan
pp. 1102-1103

Hierarchical global floorplacement using simulated annealing and network flow area migration (PDF)

Wonjoon Choi , Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, USA
K. Bazargan , Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, USA
pp. 1104-1105

LIT - an automatic layout generation tool for trapezoidal association of transistors for basic analog building blocks (PDF)

A. Girardi , Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
S. Bampi , Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 1106-1107

Symbolic analysis of nonlinear analog circuits (PDF)

A. Manthe , Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
Zhao Li , Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
C.-J.R. Shi , Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
pp. 1108-1109

A new crosstalk noise model for DOMINO logic circuits (PDF)

Seung Hoon Choi , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 1112-1113

Modeling noise transfer characteristic of dynamic logic gates (PDF)

Li Ding , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
P. Mazumder , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 1114-1115

Heterogeneous programmable logic block architectures (PDF)

A. Koorapaty , Carnegie Mellon Univ., Pittsburgh, PA, USA
V. Chandra , Carnegie Mellon Univ., Pittsburgh, PA, USA
K.Y. Tong , Carnegie Mellon Univ., Pittsburgh, PA, USA
C. Patel , Carnegie Mellon Univ., Pittsburgh, PA, USA
L. Pileggi , Carnegie Mellon Univ., Pittsburgh, PA, USA
H. Schmit , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 1118-1119

An industrial/academic configurable system-on-chip project (CSoC): coarse-grain XPP-/Leon-based architecture integration (PDF)

J. Becker , Inst. fuer Technik der Informationsverarbeitung, Karlsruhe Univ., Germany
A. Thomas , Inst. fuer Technik der Informationsverarbeitung, Karlsruhe Univ., Germany
pp. 1120-1121

Development of a tool-set for remote and partial reconfiguration of FPGAs (PDF)

F. Gehm Moraes , Faculdade de Informatica, PUCRS, Porto Alegre, Brazil
D. Mesquita , Faculdade de Informatica, PUCRS, Porto Alegre, Brazil
J. Carlos Palma , Faculdade de Informatica, PUCRS, Porto Alegre, Brazil
L. Moller , Faculdade de Informatica, PUCRS, Porto Alegre, Brazil
N. Calazans , Faculdade de Informatica, PUCRS, Porto Alegre, Brazil
pp. 1122-1123

Mapping applications to an FPFA tile [field programmable function array] (PDF)

M.A.J. Rosien , Dept. of Comput. Sci., Twente Univ., Enschede, Netherlands
Yuanqing Guo , Dept. of Comput. Sci., Twente Univ., Enschede, Netherlands
G.J.M. Smit , Dept. of Comput. Sci., Twente Univ., Enschede, Netherlands
T. Krol , Dept. of Comput. Sci., Twente Univ., Enschede, Netherlands
pp. 1124-1125

Load distribution with the proximity congestion awareness in a network on chip (PDF)

E. Nilsson , Lab. of Electron. & Comput. Syst., R. Inst. of Technol. (KTH), Stockholm, Sweden
M. Millberg , Lab. of Electron. & Comput. Syst., R. Inst. of Technol. (KTH), Stockholm, Sweden
J. Oberg , Lab. of Electron. & Comput. Syst., R. Inst. of Technol. (KTH), Stockholm, Sweden
A. Jantsch , Lab. of Electron. & Comput. Syst., R. Inst. of Technol. (KTH), Stockholm, Sweden
pp. 1126-1127

Micro-network for SoC: implementation of a 32-port SPIN network (PDF)

A. Andriahantenaina , LIP6 Lab., Univ. Pierre et Marie Curie, Paris, France
A. Greiner , LIP6 Lab., Univ. Pierre et Marie Curie, Paris, France
pp. 1128-1129

A fully self-timed bit-serial pipeline architecture for embedded systems (PDF)

A. Rettberg , Paderborn Univ., Germany
M. Zanella , Paderborn Univ., Germany
C. Bobda , Paderborn Univ., Germany
T. Lehmann , Paderborn Univ., Germany
pp. 1130-1131

Library functions timing characterization for source-level analysis (PDF)

C. Brandolese , Politecnico di Milano, Italy
W. Fornaciari , Politecnico di Milano, Italy
F. Salice , Politecnico di Milano, Italy
D. Sciuto , Politecnico di Milano, Italy
pp. 1132-1133

G-MAC: an application-specific MAC/co-processor synthesizer (PDF)

A.C.-Y. Chang , Comput. Sci. Dept., Tsing Hua Univ., Hsin-Chu, Taiwan
Wu-An Kuo , Comput. Sci. Dept., Tsing Hua Univ., Hsin-Chu, Taiwan
A.C.-H. Wu , Comput. Sci. Dept., Tsing Hua Univ., Hsin-Chu, Taiwan
Ting Ting Hwang , Comput. Sci. Dept., Tsing Hua Univ., Hsin-Chu, Taiwan
pp. 1134-1135

Power constrained high-level synthesis of battery powered digital systems (PDF)

S.F. Nielsen , Dept. of Informatics & Math. Modelling, Tech. Univ. Denmark, Lyngby, Denmark
J. Madsen , Dept. of Informatics & Math. Modelling, Tech. Univ. Denmark, Lyngby, Denmark
pp. 1136-1137

PARLAK: parametrized lock cache generator (PDF)

B.E.S. Akgul , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
V.J. Mooney , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 1138-1139

A secure web-based framework for electronic system level design (PDF)

T. Kazmierski , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
X.Q. Yang , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
pp. 1140-1141

Background data organisation for the low-power implementation in real-time of a digital audio broadcast receiver on a SIMD processor (PDF)

P.O. de Beeck , IMEC, Leuven, Belgium
C. Ghezt , IMEC, Leuven, Belgium
E. Brockmeyer , IMEC, Leuven, Belgium
M. Miranda , IMEC, Leuven, Belgium
F. Catthoor , IMEC, Leuven, Belgium
pp. 1144-1145

Compiler support for reducing leakage energy consumption (PDF)

W. Zhang , Microsyst. Design Lab., Pennsylvania State Univ., USA
M. Kandemir , Microsyst. Design Lab., Pennsylvania State Univ., USA
N. Vijaykrishnan , Microsyst. Design Lab., Pennsylvania State Univ., USA
M.J. Irwin , Microsyst. Design Lab., Pennsylvania State Univ., USA
pp. 1146-1147

An analytical model for predicting the remaining battery capacity of lithium-ion batteries (PDF)

Peng Rong , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 1148-1149

Simultaneous dynamic voltage scaling of processors and communication links in real-time distributed embedded systems (PDF)

Jiong Luo , Dept. of Electr. Eng., Princeton Univ., NJ, USA
Li-Shiuan Peh , Dept. of Electr. Eng., Princeton Univ., NJ, USA
Niraj Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 1150-1151

Decomposition of extended finite state machine for low power design (PDF)

MingHung Lee , Dept. of Comput. Sci., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
TingTing Hwang , Dept. of Comput. Sci., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
Shi-Yu Huang , Dept. of Comput. Sci., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
pp. 1152-1153

Using RTL statespace information and state encoding for induction based property checking (PDF)

M. Wedler , Dept. of Electr. Eng. & IT, Kaiserslautern Univ., Germany
D. Stoffel , Dept. of Electr. Eng. & IT, Kaiserslautern Univ., Germany
W. Kunz , Dept. of Electr. Eng. & IT, Kaiserslautern Univ., Germany
pp. 1156-1157

Combining simulation and guided traversal for the verification of concurrent systems (PDF)

E. Pastor , Dept. of Comput. Archit., Tech. Univ. of Catalonia, Barcelona, Spain
M.A. Pena , Dept. of Comput. Archit., Tech. Univ. of Catalonia, Barcelona, Spain
pp. 1158-1159

Selectively clocked CMOS logic style for low-power noise-immune operations in scaled technologies (PDF)

N. Sirisantana , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 1160-1161

Self-testing embedded checkers for Bose-Lin, Bose, and a class of Borden codes (PDF)

S. Tarnick , Satellitenkommunikationsgesellschaft, SATCON GmbH, Teltow, Germany
pp. 1162-1163

Non-intrusive concurrent error detection in FSMs through state/output compaction and monitoring via parity trees (PDF)

P. Drineas , Departments of CS & EE, Yale Univ., New Haven, CT, USA
Y. Makris , Departments of CS & EE, Yale Univ., New Haven, CT, USA
pp. 1164-1165

SAT-based techniques in system synthesis (PDF)

C. Haubelt , Comput. Sci., Univ. of Erlangen-Nuremberg, Nuremberg, Germany
pp. 1168-1169

Refinement of mixed-signal systems with SystemC (PDF)

Ch. Grimm , Professur Technische Informatik, Univ. Frankfurt, Germany
Ch. Meise , Professur Technische Informatik, Univ. Frankfurt, Germany
W. Heupke , Professur Technische Informatik, Univ. Frankfurt, Germany
K. Waldschmidt , Professur Technische Informatik, Univ. Frankfurt, Germany
pp. 1170-1171

Polychrony for refinement-based design [high-level synthesis] (PDF)

J.-P. Talpin , IRISA, INRIA, Sophia Antipolis, France
P. Le Guernic , IRISA, INRIA, Sophia Antipolis, France
pp. 1172-1173

Automatic generation of simulation monitors from quantitative constraint formula [system-level verification] (PDF)

Xi Chen , Univ. of California, Riverside, CA, USA
H. Hsieh , Univ. of California, Riverside, CA, USA
pp. 1174-1175

Consequences of RAM bitline twisting for test coverage (PDF)

I. Schanstra , Infineon Technol. AG, Munich, Germany
pp. 1176-1177

An approach to the classification of mixed-signal circuits in a pseudorandom testing scheme (PDF)

F. Corsi , Dipt. di Elettrotecnica ed Elettronica, Politecnico di Bari, Italy
C. Marzocca , Dipt. di Elettrotecnica ed Elettronica, Politecnico di Bari, Italy
G. Matarrese , Dipt. di Elettrotecnica ed Elettronica, Politecnico di Bari, Italy
pp. 1178-1179

Test generation for acyclic sequential circuits with single stuck-at fault combinational ATPG (PDF)

H. Ichihara , Fac. of Inf. Sci., Hiroshima City Univ., Japan
T. Inoue , Fac. of Inf. Sci., Hiroshima City Univ., Japan
pp. 1180-1181

Comparison of test pattern decompression techniques (PDF)

O. Novak , TU Liberec, Czech Republic
pp. 1182-1183

Evolutionary optimization of Markov sources for pseudo random scan BIST (PDF)

I. Polian , Albert-Ludwigs-Univ., Freiburg Im Breisgau, Germany
B. Becker , Albert-Ludwigs-Univ., Freiburg Im Breisgau, Germany
pp. 1184-1185

Test data compression based on output dependence (PDF)

I. Pomeranz , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 1186-1187

Single-chip MPEG-2 422P@HL CODEC LSI with multi-chip configuration for large scale processing beyond HDTV level (PDF)

M. Ogura , Cyber Space Labs., NTT Corp., Kanagawa, Japan
I. Iwasaki , Cyber Space Labs., NTT Corp., Kanagawa, Japan
K. Nitta , Cyber Space Labs., NTT Corp., Kanagawa, Japan
K. Nakamura , Cyber Space Labs., NTT Corp., Kanagawa, Japan
T. Yoshitome , Cyber Space Labs., NTT Corp., Kanagawa, Japan
J. Naganuma , Cyber Space Labs., NTT Corp., Kanagawa, Japan
Y. Nakajima , Cyber Space Labs., NTT Corp., Kanagawa, Japan
Y. Tashiro , Cyber Space Labs., NTT Corp., Kanagawa, Japan
T. Onishi , Cyber Space Labs., NTT Corp., Kanagawa, Japan
M. Ikeda , Cyber Space Labs., NTT Corp., Kanagawa, Japan
M. Endo , Cyber Space Labs., NTT Corp., Kanagawa, Japan
pp. 2-7

HiBRID-SoC: a multi-core system-on-chip architecture for multimedia signal processing applications (PDF)

H.-J. Stolberg , Inst. fur Mikroelektronische Syst., Hannover Univ., Germany
M. Berekovic , Inst. fur Mikroelektronische Syst., Hannover Univ., Germany
L. Friebe , Inst. fur Mikroelektronische Syst., Hannover Univ., Germany
S. Moch , Inst. fur Mikroelektronische Syst., Hannover Univ., Germany
S. Flugel , Inst. fur Mikroelektronische Syst., Hannover Univ., Germany
Xun Mao , Inst. fur Mikroelektronische Syst., Hannover Univ., Germany
M.B. Kulaczewski , Inst. fur Mikroelektronische Syst., Hannover Univ., Germany
H. Klussmann , Inst. fur Mikroelektronische Syst., Hannover Univ., Germany
P. Pirsch , Inst. fur Mikroelektronische Syst., Hannover Univ., Germany
pp. 8-13

Lightweight implementation of the POSIX threads API for an on-chip MIPS multiprocessor with VCI interconnect (PDF)

F. Petrot , Univ. Pierre et Marie Curie, Paris, France
P. Gomez , Univ. Pierre et Marie Curie, Paris, France
pp. 51-56

Detecting soft errors by a purely software approach: method, tools and experimental results (PDF)

B. Nicolescu , "Circuit Qualification" Res. Group, TIMA Lab., Grenoble, France
R. Velazco , "Circuit Qualification" Res. Group, TIMA Lab., Grenoble, France
pp. 57-62

Network processing challenges and an experimental NPU platform [network processor unit] (PDF)

P.G. Paulin , STMicroelectronics, Nepean, Ont., Canada
C. Pilkington , STMicroelectronics, Nepean, Ont., Canada
E. Bensoudane , STMicroelectronics, Nepean, Ont., Canada
pp. 64-69

NPSE: a high performance network packet search engine (PDF)

N. Soni , STMicroelectronics, San Diego, CA, USA
N. Richardson , STMicroelectronics, San Diego, CA, USA
Lun-Bin Huang , STMicroelectronics, San Diego, CA, USA
S. Rajgopal , STMicroelectronics, San Diego, CA, USA
G. Vlantis , STMicroelectronics, San Diego, CA, USA
pp. 74-79

Porting a network cryptographic service to the RMC2000: a case study in embedded software development (PDF)

S. Jan , Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
P. de Dios , Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
S.A. Edwards , Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
pp. 150-155

Power-performance system-level exploration of a MicroSPARC2-based embedded architecture (PDF)

C. Palermo , Dipt. di Elettronica e Informazione, Politecnico di Milano, Italy
pp. 182-187

Defining cost functions for robust IC design and optimization [analog ICs] (PDF)

A. Burmen , Fac. of Electr. Eng., Univ. of Ljubljana, Slovenia
J. Puhan , Fac. of Electr. Eng., Univ. of Ljubljana, Slovenia
T. Tuma , Fac. of Electr. Eng., Univ. of Ljubljana, Slovenia
pp. 196-201

Verification of a complex SoC; the PRO/sup 3/ case-study (PDF)

F. Andritsopoulos , Telecommun. Lab., Nat. Tech. Univ. of Athens, Greece
C. Charopoulos , Telecommun. Lab., Nat. Tech. Univ. of Athens, Greece
G. Doumenis , Telecommun. Lab., Nat. Tech. Univ. of Athens, Greece
F. Karoubalis , Telecommun. Lab., Nat. Tech. Univ. of Athens, Greece
Y. Mitsos , Telecommun. Lab., Nat. Tech. Univ. of Athens, Greece
F. Petreas , Telecommun. Lab., Nat. Tech. Univ. of Athens, Greece
I. Theologitou , Telecommun. Lab., Nat. Tech. Univ. of Athens, Greece
pp. 224-229

HW/SW partitioned optimization and VLSI-FPGA implementation of the MPEG-2 video decoder (PDF)

M. Verderber , Fac. of Electr. Eng., Univ. of Ljubljana, Slovenia
A. Zemva , Fac. of Electr. Eng., Univ. of Ljubljana, Slovenia
pp. 238-243

Comparing analytical modeling with simulation for network processors: a case study (PDF)

M. Gries , California Univ., Berkeley, CA, USA
C. Kulkarni , California Univ., Berkeley, CA, USA
pp. 256-261
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