Design, Automation & Test in Europe Conference & Exhibition (2003)
Mar. 3, 2003 to Mar. 7, 2003
Newton Cheung , University of New South Wales
Jörg Henkel , NEC Laboratories America
Sri Parameswaran , University of New South Wales
We present a methodology that maximizes the performance of Tensilica based Application Specific Instruction-set Processor (ASIP) through instruction selection when an area constraint is given. Our approach rapidly selects from a set of pre-fabricated coprocessors/functional units from our library of pre-designed specific instructions (to evaluate our technology we use the Tensilica platform). As a result, we significantly increase application performance while area constraints are satisfied. Our methodology uses a combination of simulation, estimation and a pre-characterised library of instructions, to select the appropriate co-processors and instructions. We report that by selecting the appropriate coprocessors/functional units and specific TIE instructions, the total execution time of complex applications (we study a voice encoder/decoder), an application?s performance can be reduced by up to 85% compared to the base implementation. Our estimator used in the system takes typically less than a second to estimate, with an average error rate of 4% (as compared to full simulation, which takes 45 minutes). The total selection process using our methodology takes 3-4 hours, while a full design space exploration using simulation would take several days.
N. Cheung, S. Parameswaran and J. Henkel, "Rapid Configuration and Instruction Selection for an ASIP: A Case Study," Design, Automation & Test in Europe Conference & Exhibition(DATE), Munich, Germany, 2003, pp. 10802.