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Design, Automation & Test in Europe Conference & Exhibition (2002)
Paris, France
Mar. 4, 2002 to Mar. 8, 2002
ISBN: 0-7695-1471-5
pp: 0368
ABSTRACT
As the complexity of VLSI circuits is increasing due to the exponential rise in transistor count per chip, testing cost is becoming an important factor in the overall integrated circuit (IC) manufacturing cost. This paper addresses the issue of decreasing test cost by lowering the test data bits and the number of clock cycles required to test a chip. We propose a new incremental algorithm for generating tests for Illinois Scan Architecture (ILS) based designs and provide analysis of test data and test time reduction. This algorithm is very efficient in generating tests for a number of ILS designs in order to find the most optimal configuration.
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CITATION

J. Patel and A. Pandey, "An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs," Design, Automation & Test in Europe Conference & Exhibition(DATE), Paris, France, 2002, pp. 0368.
doi:10.1109/DATE.2002.998300
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