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Design, Automation & Test in Europe Conference & Exhibition (2002)
Paris, France
Mar. 4, 2002 to Mar. 8, 2002
ISBN: 0-7695-1471-5
pp: 0255
ABSTRACT
Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have been applied to asynchronous circuits in the past in order to achieve throughput increases. A general method for computing early evaluation functions is presented for this design style. Experimental results are given that show the increase in throughput of various benchmark circuits. The results show that as much as a 30% speedup can be achieved in some cases.
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CITATION

M. Thornton, C. Traver, K. Fazel and R. Reese, "Generalized Early Evaluation in Self-Timed Circuits," Design, Automation & Test in Europe Conference & Exhibition(DATE), Paris, France, 2002, pp. 0255.
doi:10.1109/DATE.2002.998281
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