The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2001)
Munich, Germany
Mar. 13, 2001 to Mar. 16, 2001
ISBN: 0-7695-0993-2
TABLE OF CONTENTS

Reviewers (PDF)

pp. xxx

Best Paper Awards (PDF)

pp. xxxiii

Tutorials (PDF)

pp. xxxiv
1A: Complementary Approaches to Designing Correct Circuits

Abstraction of Word-level Linear Arithmetic Functions from Bit-level Component Descriptions (Abstract)

Pallab Dasgupta , Indian Institute of Technology
P.P. Chakrabarti , Indian Institute of Technology
Amit Nandi , Indian Institute of Technology
Sekar Krishna , Indian Institute of Technology
Arindam Chakrabarti , Indian Institute of Technology
pp. 0004

Biasing Symbolic Search by Means of Dynamic Activity Profiles (Abstract)

Gianpiero Cabodi , Politecnico di Torino
Paolo Camurati , Politecnico di Torino
Stefano Quer , Politecnico di Torino
pp. 0009
1B: New Design Methods with SystemC

A Methodology for Interfacing Open Source SystemC with a Third Party Software (Abstract)

Luc Charest , Universit? de Montr?al
Michel Reid , Universit? de Montr?al
E.Mostapha Aboulhamid , Universit? de Montr?al
Guy Bois , Ecole Polytechnique de Montr?al
pp. 0016

Behavioral Synthesis with SystemC (Abstract)

George Economakos , National Technical University of Athens
Petros Oikonomakos , National Technical University of Athens
Ioannis Panagopoulos , National Technical University of Athens
Ioannis Poulakis , National Technical University of Athens
George Papakonstantinou , National Technical University of Athens
pp. 0021
1C: Embedded Tutorial---TRP: Integrating Embedded Test and ATE

Test Resource Partitioning: A Design and Test Issue (PDF)

J.P. Teixeira , IST / INESC
I.M. Teixeira , IST / INESC
O.P. Dias , IST / INESC
J. Semião , IST / INESC
C.E. Pereira , UFRGS
pp. 0034
1E: Embedded Tutorial---Current Trends in the Design of Automotive Electronic Systems
2A: Platforms and IP-Based Design

Component Selection and Matching for IP-Based Design (Abstract)

Ting Zhang , Stanford University
Luca Benini , Universit? di Bologna
Giovanni de Micheli , Stanford University
pp. 0040

A Universal Communication Model for an Automotive System Integration Platform (Abstract)

Thilo Demmeler , Bayerische Motoren Werke AG
Paolo Giusto , Cadence Design Systems Inc.
pp. 0047
2B: Approaching Semantics of Design Languages

The Simulation Semantics of SystemC (Abstract)

Wolfgang Mueller , C-LAB/Paderborn University
Juergen Ruf , University of Tuebingen
Dirk Hoffmann , University of Tuebingen
Joachim Gerlach , University of Tuebingen
Thomas Kropf , University of Tuebingen
Wolfgang Rosenstiehl , University of Tuebingen
pp. 0064
2C: BIST and Diagnosis

Circuit Partitioning for Efficient Logic BIST Synthesis (Abstract)

Alexander Irion , University of Stuttgart
Gundolf Kiefer , University of Stuttgart
Hans-Joachim Wunderlich , University of Stuttgart
Harald Vranken , Philips Research Laboratories
pp. 0086

Deterministic Software-Based Self-Testing of Embedded Processor Cores (Abstract)

A. Paschalis , University of Athens
D. Gizopoulos , University of Piraeus
N. Kranitis , II&T, NCSR "Demokritos"
M. Psarakis , II&T, NCSR "Demokritos"
Y. Zorian , LogicVision
pp. 0092

Memory Fault Diagnosis by Syndrome Compression (Abstract)

Jin-Fu Li , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
pp. 0097

Diagnosis for Scan-Based BIST: Reaching Deep into the Signatures (Abstract)

Ismet Bayraktaroglu , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 0102
2E: Hot Topic---EUCAR Session
3A: SAT Based Verification Techniques

Using SAT for Combinational Equivalence Checking (Abstract)

Evgueni I. Goldberg , Cadence Design Systems
Mukul R. Prasad , University of California, Berkeley
Robert K. Brayton , University of California, Berkeley
pp. 0114

An Efficient Learning Procedure for Multiple Implication Checks (Abstract)

Yakov Novikov , Academy of Sciences (Belarus)
Evgueni Goldberg , Cadence Berkeley Labs
pp. 0127
3B: Panel Session---C/C ++
3C: Advances in SoC Testing

An Integrated System-On-Chip Test Framework (Abstract)

Erik Larsson , Link?pings Universitet
Zebo Peng , Link?pings Universitet
pp. 0138

On Applying the Set Covering Model to Reseeding (Abstract)

Silvia Chiusano , Politecnico di Torino
Stefano Di Carlo , Politecnico di Torino
Paolo Prinetto , Politecnico di Torino
Hans-Joachim Wunderlich , University of Stuttgart
pp. 0156
3E: Panel Session
4A: Analysis of Communication Systems

Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers (Abstract)

Yves Rolain , Vrije Universiteit Brussel
Johan Schoukens , Vrije Universiteit Brussel
pp. 0164

Efficient Time-Domain Simulation of Telecom Frontends Using a Complex Damped Exponential Signal Model (Abstract)

Piet Vanassche , Katholieke Universiteit Leuven
Georges Gielen , Katholieke Universiteit Leuven
Willy Sansen , Katholieke Universiteit Leuven
pp. 0169
4B: Design of Low Power Systems I

Microprocessor Power Analysis by Labeled Simulation (Abstract)

Cheng-Ta Hsieh , University of Southern California
Lung-sheng Chen , University of Southern California
Massoud Pedram , University of Southern California
pp. 0182

Power Aware Microarchitecture Resource Scaling (Abstract)

Anoop Iyer , Carnegie Mellon University
Diana Marculescu , Carnegie Mellon University
pp. 0190

Extending Lifetime of Portable Systems by Battery Scheduling (Abstract)

L. Benini , Universit? di Bologna
G. Castelli , Politecnico di Torino
A. Macii , Politecnico di Torino
E. Macii , Politecnico di Torino
M. Poncino , Politecnico di Torino
R. Scarsi , Politecnico di Torino
pp. 0197
4C: Test Generation and Evaluation

Efficient Spectral Techniques for Sequential ATPG (Abstract)

Ashish Giani , Rutgers University
Shuo Sheng , Rutgers University
Michael S. Hsiao , Rutgers University
Vishwani D. Agrawal , Bell Labs, Lucent Technologies
pp. 0204

On the Test of Microprocessor IP Cores (Abstract)

F. Corno , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
G. Squillero , Politecnico di Torino
M. Violante , Politecnico di Torino
pp. 0209

SEU Effect Analysis in a Open-Source Router via a Distributed Fault Injection Environment (Abstract)

Alfredo Benso , Politecnico di Torino
Stefano Di Carlo , Politecnico di Torino
Giorgio Di Natale , Politecnico di Torino
Paolo Prinetto , Politecnico di Torino
pp. 0219
4E: Panel Session
4F: Planning Support

Slicing Tree Is a Complete Floorplan Representation (Abstract)

Minghorng Lai , The University of Texas at Austin
D.F. Wong , The University of Texas at Austin
pp. 0228

Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques (Abstract)

Chak-Chung Cheung , The Chinese University of HK
Yu-Liang Wu , The Chinese University of HK
David Ihsin Cheng , Ultima Interconnect Technology
pp. 0233

Clustering Based Fast Clock Scheduling for Light Clock-Tree (Abstract)

Makoto Saitoh , Tokyo Institute of Technology
Masaaki Azuma , Tokyo Institute of Technology
Atsushi Takahashi , Tokyo Institute of Technology
pp. 0240
5A: Low-Power Channel Decoding and VLIW Architectures

Power-Efficient Layered Turbo Decoder Processor (Abstract)

J. Dielissen , Philips Research
J. Van Meerbergen , Philips Research
Marco Bekooij , Philips Research
Françoise Harmsze , Philips Research
Jos Huisken , Philips Research
Albert Van der Werf , Philips Research
Sergej Sawitzki , Technical University Dresden
pp. 0246

Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors (Abstract)

M. Sami , Politecnico di Milano
D. Sciuto , Politecnico di Milano
C. Silvano , Politecnico di Milano
V. Zaccaria , Politecnico di Milano
R. Zafalon , STMicroelectronics
pp. 0252

Design of Low-Power High-Speed Maximum a Priori Decoder Architectures (Abstract)

Alexander Worm , University of Kaiserslautern
Holger Lamm , University of Kaiserslautern
Norbert Wehn , University of Kaiserslautern
pp. 0258
5B: Design of Low-Power Systems II

Low Complexity FIR Filters Using Factorization of Perturbed Coefficients (Abstract)

Cassondra Neau , Purdue University
Kaushik Roy , Purdue University
Khurram Muhammad , Texas Instruments
pp. 0268

An Adaptive Algorithm for Low-Power Streaming Multimedia Processing (Abstract)

Andrea Acquaviva , DEIS - Universit? di Bologna
Luca Benini , DEIS - Universit? di Bologna
Bruno Riccó , DEIS - Universit? di Bologna
pp. 0273

A Static Power Estimation Methodology for IP-Based Design (Abstract)

Xun Liu , University of Michigan
Marios C. Papaefthymiou , University of Michigan
pp. 0280
5C: On-Line Testing Techniques

Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors (Abstract)

M. Favalli , DI - University of Ferrara
C. Metra , DEIS - University of Bologna
pp. 0290

System Safety through Automatic High-Level Code Transformations: an Experimental Evaluation (Abstract)

M. Rebaudengo , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
M. Violante , Politecnico di Torino
P. Cheynet , Institut National Polytechnique Grenoble
B. Nicolescu , Institut National Polytechnique Grenoble
R. Velazco , Institut National Polytechnique Grenoble
pp. 0297

From DFT to Systems Test-A Model Based Cost Optimisation Tool (Abstract)

Michael G. Wahl , Universit?t Siegen,
Christoph Maaß , Universit?t Siegen,
Tony Ambler , University of Texas at Austin,
Mohammed Rahman , Southwest Texas State University
pp. 0302

Efficient On-Line Testing Method for a Floating-Point Adder (Abstract)

A. Drozd , Odessa State Polytechnic University
M. Lobachev , Odessa State Polytechnic University
pp. 0307
5E: Design Methodology for PicoRadio Networks

Design Methodology for PicoRadio Networks (Abstract)

J.L. da Silva Jr , University of California at Berkeley
J. Shamberger , University of California at Berkeley
M.J. Ammer , University of California at Berkeley
C. Guo , University of California at Berkeley
S. Li , University of California at Berkeley
R. Shah , University of California at Berkeley
T. Tuan , University of California at Berkeley
M. Sheets , University of California at Berkeley
J.M. Rabaey , University of California at Berkeley
B. Nikolic , University of California at Berkeley
A. Sangiovanni-Vincentelli , University of California at Berkeley
P. Wright , University of California at Berkeley
pp. 0314
5F: EMC on Chip and High Density Package Level

Crosstalk Noise in Future Digital CMOS Circuits (Abstract)

Chr. Werner , Infineon Technologies
R. Göttsche , Infineon Technologies
A. Wörner , Infineon Technologies
U. Ramacher , Infineon Technologies
pp. 0331

Modeling Electromagnetic Emission of Integrated Circuits for System Analysis (Abstract)

P. Kralicek , Fraunhofer Institute Reliability and Microintegration
W. John , Fraunhofer Institute Reliability and Microintegration
H. Garbe , University of Hannover
pp. 0336

Analysis of EME Produced by a Microcontroller Operations (Abstract)

Franco Fiori , Politecnico di Torino
Francesco Musolino , Politecnico di Torino
pp. 0341
6A: Design Methods for Analog and Mixed Signal Circuits

Top-Down Design of a xDSL 14-bit 4MS/s \Sigma\Delta Modulator in Digital CMOS Technology (Abstract)

R. del Río , Instituto de Microelectr?nica de Sevilla
J.M. de la Rosa , Instituto de Microelectr?nica de Sevilla
F. Medeiro , Instituto de Microelectr?nica de Sevilla
B. Pérez-Verdú , Instituto de Microelectr?nica de Sevilla
A. Rodríguez-Vázquez , Instituto de Microelectr?nica de Sevilla
pp. 0348

Analog Design for Reuse - Case Study: Very Low-voltage DeltaSigma Modulator (Abstract)

Mohamed Dessouky , Universite Paris VI
Marie-Minerve Louerat , Universite Paris VI
Alain Greiner , Universite Paris VI
Andreas Kaiser , IEMN-ISEN
pp. 0353
6B: Issues in Synthesis and Power Optimization

Minimizing Stand-By Leakage Power in Static CMOS Circuits (Abstract)

Srinath R. Naidu , Eindhoven University of Technology
E.T.A.F. Jacobs , Eindhoven University of Technology
pp. 0370

In-Place Delay Constrained Power Optimization Using Functional Symmetries (Abstract)

Chih-Wei (Jim) Chang , University of California, Santa Barbara
Bo Hu , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 0377

High-Quality Sub-Function Construction in Functional Decomposition Based on Information Relationship Measures (Abstract)

Lech Jozwiak , Eindhoven University of Technology
Artur Chojnacki , Eindhoven University of Technology
pp. 0383

Generalized Reasoning Scheme for Redundancy Addition and Removal Logic Optimization (Abstract)

J.A. Espejo , Universidad Carlos III de Madrid
L. Entrena , Universidad Carlos III de Madrid
E. San Millán , Universidad Carlos III de Madrid
E. Olías , Universidad Carlos III de Madrid
pp. 0391
6C: High Level Validation

LPSAT: A Unified Approach to RTL Satisfiability (Abstract)

Zhihong Zeng , University of Massachusetts Amherst
Priyank Kalla , University of Massachusetts Amherst
Maciej Ciesielski , University of Massachusetts Amherst
pp. 0398

Functional Test Generation for Behaviorally Sequential Models (Abstract)

F. Ferrandi , Politecnico di Milano
G. Ferrara , Politecnico di Milano
D. Sciuto , Politecnico di Milano
A. Fin , Universita di Verona
F. Fummi , Universita di Verona
pp. 0403

High Quality Behavioral Verification Using Statistical Stopping Criteria (Abstract)

Amjad Hajjar , Colorado State University
Tom Chen , Colorado State University
Isabelle Munn , Colorado State University
Anneliese Andrews , Colorado State University
Maria Bjorkman , Colorado State University
pp. 0411
6E: Hot Topic---Network Processors: A Perspective on Market Requirements, Processor Architectures and Embedded S/W Tools
6F: Interconnect Extraction and Modelling

Explicit Formulas and Efficient Algorithm for Moment Computation of Coupled RC Trees with Lumped and Distributed Elements (Abstract)

Qingjian Yu , University of California at Berkeley
Ernest S. Kuh , University of California at Berkeley
pp. 0445
7A: Timing and Parallel Simulation

Timing Simulation of Digital Circuits with Binary Decision Diagrams (Abstract)

R. Ubar , Tallinn Technical University,
A. Jutman , Tallinn Technical University,
Z. Peng , Link?ping University
pp. 0460

HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation Delay Model (Abstract)

P. Ruiz de Clavijo Vazquez , Instituto de Microelectronica de Sevilla. CNM
J. Juan-Chico , Instituto de Microelectronica de Sevilla. CNM
M.J. Bellido , Instituto de Microelectronica de Sevilla. CNM
A. Acosta , Instituto de Microelectronica de Sevilla. CNM
M. Valencia , Instituto de Microelectronica de Sevilla. CNM
pp. 0467

dlbSIM -A Parallel Functional Logic Simulator Allowing Dynamic Load Balancing (Abstract)

Klaus Hering , Chemnitz University of Technology
Jork Loser , Dresden University of Technology
Jens Markwardt , Leipzig University
pp. 0472

Architecture Driven Partitioning (Abstract)

Joachim Küter , Infineon Technologies AG
Erich Barke , University of Hannover
pp. 0479
7B: Embedded Tutorial---Low-Power Issues for SOCs

Special Session on Low-Power Systems on Chips (SOCs) (Abstract)

Marc Renaudin , Laboratoire TIMA
Thierry J-F. Omnes , Interuniversity Micro-Electronics Centre (IMEC)
pp. 0488
7C: Defect Oriented Testing

Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs (Abstract)

Zaid Al-Ars , Delft University of Technology
Ad J. van de Goor , Delft University of Technology
pp. 0496

CMOS Open Defect Detection by Supply Current Test (Abstract)

Masaki Hashizume , The Univ. of Tokushima
Masahiro Ichimiya , The Univ. of Tokushima
Hiroyuki Yotsuyanagi , The Univ. of Tokushima
Takeomi Tamesada , The Univ. of Tokushima
pp. 0509

Full Chip False Timing Path Identification: Applications to the PowerPCTM Microprocessors (Abstract)

Jing Zeng , Motorola ASP Somerset Design Center
Jayanta Bhadra , Motorola ASP Somerset Design Center
Magdy S. Abadir , Motorola ASP Somerset Design Center
Jacob A. Abraham , The University of Texas at Austin
pp. 0514
7E: Embedded Tutorial---CAD for RF Integrated Circuits and Systems

CAD for RF Circuits (Abstract)

Joel Phillips , Cadence Berkeley Laboratories
Jaijeet Roychowdhury , Bell Laboratories
David Long , Bell Laboratories
Alper Demir , Bell Laboratories
Baolin Yang , Cadence Design Systems, Inc.
pp. 0520
7F: Routing Enhancements

Modeling Crosstalk Noise for Deep Submicron Verification Tools (Abstract)

Pirouz Bazargan Sabet , University of Paris 6
Fabrice Ilponse , University of Paris 6
pp. 0530

A Graph Based Algorithm for Optimal Buffer Insertion Under Accurate Delay Models (Abstract)

Youxin Gao , Avant! Corporation
D.F. Wong , University of Texas at Austin
pp. 0535
Moderators: V. Meyer zu Bexten, Atmel Germany GmbH, D; E. Barke, Hannover U, D

On-the-Fly Layout Generation for PTL Macrocells (Abstract)

Luca Macchiarulo , Politecnico di Torino
Enrico Macii , Politecnico di Torino
Luca Benini , Universit? di Bologna
pp. 0546

Automatic Datapath Tile Placement and Routing (Abstract)

Tatjana Serdar , University of Washington
Carl Sechen , University of Washington
pp. 0552

A Boolean Satisfiability-Based Incremental Rerouting Approach with Application to FPGAs (Abstract)

Gi-Joon Nam , University of Michigan
Karem Sakallah , University of Michigan
Rob Rutenbar , Carnegie Mellon University
pp. 0560
8B: Modelling and Performance Analysis of Embedded Systems

Probabilistic Application Modeling for System-Level Performance Analysis (Abstract)

Radu Marculescu , Carnegie Mellon University
Amit Nandi , Carnegie Mellon University
pp. 0572

Reliable Estimation of Execution Time of Embedded Software (Abstract)

Paolo Giusto , Cadence Design Systems, Inc.
Grant Martin , Cadence Design Systems, Inc.
Ed Harcourt , Cadence Design Systems, Inc.
pp. 0580
8C: Analog and Mixed Signal Testing

Implementation of a Linear Histogram BIST for ADCs (Abstract)

F. Azaïs , LIRMM - University of Montpellier II
S. Bernard , LIRMM - University of Montpellier II
Y. Bertrand , LIRMM - University of Montpellier II
M. Renovell , LIRMM - University of Montpellier II
pp. 0590

Test Generation Based Diagnosis of Device Parameters for Analog Circuits (Abstract)

Sasikumar Cherubal , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 0596
8E: Panel Session---Managing the SoC Design Challenge with‚ Soft(tm) Hardware
8F: Hardware-Software Architectures and Synthesis

System-on-a-Chip Processor Synchronization Support in Hardware (Abstract)

Bilge E. Saglam , Georgia Institute of Technology
Vincent J. Mooney Iii , Georgia Institute of Technology
pp. 0633
9A: Reconfigurable Computing I

Hierarchical Memory Mapping During Synthesis in FPGA-Based Reconfigurable Computers (Abstract)

Iyad Ouaiss , University of Cincinnati
Ranga Vemuri , University of Cincinnati
pp. 0650
9B: Embedded Software

Generation of Minimal Size Code for Schedule Graphs (Abstract)

Claudio Passerone , Politecnico di Torino
Yosinori Watanabe , Cadence Design Systems
Luciano Lavagno , Universita di Udine
pp. 0668

Generating Production Quality Software Development Tools Using a Machine Description Language (Abstract)

Andreas Hoffmann , Integrated Signal Processing Systems (ISS)
Achim Nohl , Integrated Signal Processing Systems (ISS)
Stefan Pees , Integrated Signal Processing Systems (ISS)
Gunnar Braun , Integrated Signal Processing Systems (ISS)
Heinrich Meyr , Integrated Signal Processing Systems (ISS)
pp. 0674

Cache Conscious Data Layout Organization For Embedded Multimedia Applications (Abstract)

C. Kulkarniz , IMEC and Katholieke Universiteit Leuven
F. Catthoory , IMEC and Katholieke Universiteit Leuven
H. de Many , IMEC and Katholieke Universiteit Leuven
C. Ghez , IMEC
M. Miranda , IMEC
pp. 0686
9C: Panel Session---Design Challenges and Emerging EDA Solutions in Mixed-Signal IC Design
9E: Hot Topic---Game Processors
9F: Decision Diagrams

Streaming BDD Manipulation for Large-Scale Combinatorial Problems (Abstract)

Shin-ichi Minato , NTT Network Innovation Laboratories
Shinya Ishihara , NTT Network Innovation Laboratories
pp. 0702

Binary Decision Diagram with Minimum Expected Path Length (Abstract)

Yi-Yu Liu , National Tsing Hua University
TingTing Hwang , National Tsing Hua University
C. L. Liu , National Tsing Hua University
Kuo-Hua Wang , Fu Jen Catholic University
pp. 0708

Spectral Decision Diagrams Using Graph Transformations (Abstract)

Mitchell Thornton , Mississippi State University
Rolf Drechsler , Siemens AG
pp. 0713
9L: Friday Keynote Session---Electronic System Design Methodology: Europe's Positioning
10A: Reconfigurable Computing II

Precision and Error Analysis of Matlab Applications During Automated Hardware Synthesis for FPGAs (Abstract)

Anshuman Nayak , Northwestern University
Malay Haldar , Northwestern University
Alok Choudhary , Northwestern University
Prith Banerjee , Northwestern University
pp. 0722

A HW/SW Partitioning Algorithm for Dynamically Reconfigurable Architectures (Abstract)

Juanjo Noguera , Universitat Politecnica Catalunya
Rosa M. Badia , Universitat Politecnica Catalunya
pp. 0729
10B: Co-Simulation and System Verification Techniques

Simulation-Guided Property Checking Based on Multi-Valued AR-Automata (Abstract)

Jurgen Ruf , University of Tubingen
Dirk W. Hoffmann , University of Tubingen
Thomas Kropf , University of Tubingen
Wolfgang Rosenstiel , University of Tubingen
pp. 0742

Performance Improvement of Multi-Processor Systems Cosimulation Based on SW Analysis (Abstract)

Jinyong Jung , Seoul National University
Kiyoung Choi , Seoul National University
Sungjoo Yoo , TIMA/INPG
pp. 0749

A Framework for Fast Hardware-Software Co-simulation (Abstract)

Andreas Hoffmann , RWTH Aachen
Tim Kogel , RWTH Aachen
Heinrich Meyr , RWTH Aachen
pp. 0760
10C: Embedded Tutorial ΠAnalog Methods and Tools for SoC Integration
10E: Panel Session---Standard Bus vs. Bus Wrapper: What is the Best Solution for Future SoC Integration?
10F: Architectural Level Synthesis

Access Pattern Based Local Memory Customization for Low Power Embedded Systems (Abstract)

Peter Grun , University of California, Irvine
Nikil Dutt , University of California, Irvine
Alex Nicolau , University of California, Irvine
pp. 0778

Static Memory Allocation by Pointer Analysis and Coloring (Abstract)

Jianwen Zhu , University of Toronto, Ontario
pp. 0785

Heuristic Datapath Allocation for Multiple Wordlength Systems (Abstract)

George A. Constantinides , Imperial College
Peter Y.K. Cheung , Imperial College
Wayne Luk , Imperial College
pp. 0791
Poster Session

Index of Authors (PDF)

pp. 0825
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