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Design, Automation & Test in Europe Conference & Exhibition (2000)
Paris, France
Mar. 27, 2000 to Mar. 30, 2000
ISSN: 1530-1591
ISBN: 0-7695-0537-6
TABLE OF CONTENTS

Reviewers (PDF)

pp. xxvii

Tutorials (PDF)

pp. xxx

Best Paper Awards (PDF)

pp. xxxi
Plenary—Keynote Session
1A: Embedded Software Generation

Free MDD-Based Software Optimization Techniques for Embedded Systems (Abstract)

Chunghee Kim , Hanyang University
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
Luciano Lavagno , Universit? di Udine
pp. 14
1B: Low-Power Issues in System-Level Design

Quantitative Comparison of Power Management Algorithms (Abstract)

Giovanni de Micheli , Stanford University
Tajana Simunic , Stanford University
Eui-Young Chung , Stanford University
Luca Benini , Universita di Bologna
Yung-Hsiang Lu , Stanford University
pp. 20

Efficient Power Co-Estimation Techniques for System-on-Chip Design (Abstract)

Sujit Dey , University of California at San Diego
Marcello Lajolo , Politecnico di Torino
Luciano Lavagno , Universit? di Udine
pp. 27

A Discrete-Time Battery Model for High-Level Power Estimation (Abstract)

A. Macii , Politecnico di Torino
G. Castelli , Politecnico di Torino
L. Benini , Universit? di Bologna
M. Poncino , Politecnico di Torino
E. Macii , Politecnico di Torino
R. Scarsi , Politecnico di Torino
pp. 35
1C: Circuit Analysis and Synthesis

The Generalized Boundary Curve—A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits (Abstract)

K. Antreich , Infineon Technologies
F. Schenkel , Infineon Technologies
H. Graeb , Infineon Technologies
R. Schwencker , Infineon Technologies and Technical University of Munich
pp. 42

A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits (Abstract)

A. Rodríguez-Vázquez , Centro Nacional de Microelectr?nica
O. Guerra , Centro Nacional de Microelectr?nica
E. Roca , Centro Nacional de Microelectr?nica
F.V. Fernández , Centro Nacional de Microelectr?nica
pp. 48

Layout-Oriented Synthesis of High Performance Analog Circuits (Abstract)

Marie-Minerve Louërat , Universit? Paris VI
Jacky Porte , Ecole Nationale Superieure des Telecommunications
Mohamed Dessouky , Universit? Paris VI
pp. 53
1D: Embedded Tutorial — Design Practices for Better Reliability and Yield

Tutorial Statement (Abstract)

Kees Veelenturf , Philips
Yervant Zorian , Logic Vision
pp. 66
2A: Embedded Tutorial — System Level Design Using C++

System Level Design Using C++ (Abstract)

Joachim Kunkel , Synopsys
Frank Schirrmeister , Cadence Design Systems
pp. 74
2B: IP and Design Reuse

Techniques for Reducing Read Latency of Core Bus Wrappers (Abstract)

Tony D. Givargis , University of California at Riverside
Roman L. Lysecky , University of California at Riverside
Frank Vahid , University of California at Riverside
pp. 84

Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications (Abstract)

Francky Catthoor , IMEC and Katholieke Universiteit at Leuven
Frederik Vermeulen , IMEC and Katholieke Universiteit at Leuven
Hugo de Man , IMEC and Katholieke Universiteit at Leuven
pp. 92
2C: Layout

Layout (PDF)

pp. null

Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation (Abstract)

Xiaoping Tang , University of Texas at Austin
D.F. Wong , University of Texas at Austin
Ruiqi Tian , University of Texas at Austin and Motorola Computational Technology Lab
pp. 106

A New Effective And Efficient Multi-Level Partitioning Algorithm (Abstract)

Youssef Saab , University of Missouri at Columbia
pp. 112

Faster Optimal Single-Row Placement with Fixed Ordering (Abstract)

U. Brenner , University of Bonn
J. Vygen , University of Bonn
pp. 117

Layout Compaction for Yield Optimization via Critical Area Minimization (Abstract)

Youcef Bourai , University of Washington
C.-J. Richard Shi , University of Washington
pp. 122
2D: Heterogeneous Aspects in SOC Testing

Test Synthesis for Mixed-Signal SOC Paths (Abstract)

Sule Ozev , University of California at San Diego
Ismet Bayraktaroglu , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 128

Analysis and Minimization of Test Time in a Combined BIST and External Test Approach (Abstract)

Hiroto Yasuura , Kyushu University
Hiroshi Date , Institute of Systems &Information Technologies
Makoto Sugihara , Kyushu University
pp. 134

Design and Test Space Exploration of Transport-Triggered Architectures (Abstract)

V.A. Zivkovic , University of Twente
H.G. Kerkhoff , University of Twente
R.J.W.T. Tangelder , University of Twente
pp. 146
3A: System Specification

Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors (Abstract)

Per Bjuréus , CelsiusTech Electronics AB
Axel Jantsch , Royal Institute of Technology
pp. 154

MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow (Abstract)

Per Bjuréus , CelsiusTech Electronics AB
Axel Jantsch , Royal Institute of Technology
pp. 161

Delay-Insensitive Interface Specification and Synthesis (Abstract)

Mark B. Josephs , South Bank University
Dennis Furey , South Bank University
pp. 169
3B: Implementation of Telecom Systems

A 50 Mbit/s Iterative Turbo-Decoder (Abstract)

F. Viglione , Politecnico di Torino
G. Piccinini , Politecnico di Torino
G. Masera , Politecnico di Torino
M. Ruo Roch , Politecnico di Torino
M. Zamboni , Politecnico di Torino
pp. 176

Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing (Abstract)

A. Picciriello , SIEMENS ICN S.p.A.
U. Girola , SIEMENS ICN S.p.A.
D. Vincenzoni , SIEMENS ICN S.p.A.
pp. 181
3C: Logic Synthesis: Combination

Constructive Library-Aware Synthesis Using Symmetries (Abstract)

Karem A. Sakallah , University of Michigan
Victor N. Kravets , University of Michigan
pp. 208
3D: BIST for Mixed-Signal Applications

A BIST Scheme for On-Chip ADC and DAC Testing (Abstract)

Kwang-Ting Cheng , University of California at Santa Barbara
Chee-Kian Ong , University of California at Santa Barbara
Jiun-Lang Huang , University of California at Santa Barbara
pp. 216

An on Chip ADC Test Structure (Abstract)

Kuen-Jong Lee , National Cheng Kung University
Yun-Che Wen , National Cheng Kung University
pp. 221
4A: Decision Diagram Based Methods

A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm (Abstract)

Chilai Huang , Avery Design Systems Incorporated
Priyank Kalla , University of Massachusetts at Amherst
Zhihong Zeng , University of Massachusetts at Amherst
Maciej Ciesielski , University of Massachusetts at Amherst
pp. 232

Automatic Lighthouse Generation for Directed State Space Search (Abstract)

Vigyan Singhal , Tempus Fugit Incorporated
Praveen Yalagandula , University of Texas at Austin
Adnan Aziz , University of Texas at Austin
pp. 237
4B: Multi-Processor Architectures and Design Methods

Memory Arbitration and Cache Management in Stream-Based Systems (Abstract)

Françoise Harmsze , Eindhoven University of Technology
Adwin Timmer , Eindhoven University of Technology
Jef van Meerbergen , Eindhoven University of Technology
pp. 257
4C: Logic Synthesis: Performance Optimization

Wave Steered FSMs (Abstract)

Luca Macchiarulo , University of California, Santa Barbara
Shih-Ming Shu , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 270
4D: TPG and Diagnosis in BIST

Optimal Hardware Pattern Generation for Functional BIST (Abstract)

Hans-Joachim Wunderlich , University of Stuttgart
Paolo Prinetto , Politecnico di Torino
Silvia Chiusano , Politecnico di Torino
Silvia Cataldo , Politecnico di Torino
pp. 292
5A: Architectural-Level Synthesis

Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation (Abstract)

Wolfgang Rosenstiel , Forschungszentrum Informatik and Universit?t Tuebingen
Carsten Menn , Forschungszentrum Informatik
Oliver Bringmann , Forschungszentrum Informatik and Universit?t Tuebingen
pp. 326

Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip DesignJ?rg Henkel (Abstract)

Frank Vahid , University of California at Riverside
Tony D. Givargis , University of California at Riverside
pp. 333
5B: Analysis of Communication Circuits

A New Approach for Computation of Timing Jitter in Phase Locked Loops (Abstract)

M.M. Gourary , IPPM, Russian Academy of Sciences
M.M. Zharov , IPPM, Russian Academy of Sciences
S.L. Ulyanov , IPPM, Russian Academy of Sciences
K.K. Gullapalli , Motorola Incorporated
B.J. Mulvaney , Motorola Incorporated
S.G. Rusakov , IPPM, Russian Academy of Sciences
pp. 345
5C: Logic Synthesis: Covering and PTL Circuits

On Using Satisfiability-Based Pruning Techniques in Covering Algorithms (Abstract)

Vasco M. Manquinho , Instituto Superior T?cnico
João Marques-Silva , Instituto Superior T?cnico
pp. 356

An Efficient Heuristic Approach to Solve the Unate Covering Problem (Abstract)

Donatella Sciuto , Politecnico di Milano
Fabrizio Ferrandi , Politecnico di Milano
Roberto Wolfler Calvo , Joint Research Center - Ispra
Roberto Cordone , Politecnico di Milano
pp. 364
5D: Delay and Functional Testing

A VHDL Error Simulator for Functional Test Generation (Abstract)

Franco Fummi , Universit? di Verona
Alessandro Fin , Universit? di Verona
pp. 390

Functional Test Generation for Full Scan Circuits (Abstract)

Sudhakar M. Reddy , University of Iowa
Irith Pomeranz , University of Iowa
pp. 396
6A: Co-Synthesis of Embedded Systems

Shared Memory Implementations of Synchronous Dataflow Specifications (Abstract)

Praveen K. Murthy , Angeles Design Systems
Shuvra S. Bhattacharyya , University of Maryland at College Park
pp. 404

Constraint-Driven System Partitioning (Abstract)

Juan Carlos López , Universidad Castilla-La Mancha
Jesus Grajal , Universidad Politecnica Madrid
Maria Luisa López-Vallejo , Universidad Politecnica Madrid
pp. 411

A System-Level Synthesis Algorithm with Guaranteed Solution Quality (Abstract)

U. Nagaraj Shenoy , Northwestern University
Alok Choudhary , Northwestern University
Prith Banerjee , Northwestern University
pp. 417
6B: Hot Topic

Hot Topic (PDF)

pp. null
6C: Wire Performance

Wire Performance (PDF)

pp. null

Meeting Delay Constraints in DSM by Minimal Repeater Insertion (Abstract)

I-Min Liu , University of Texas at Austin
Adnan Aziz , University of Texas at Austin
D.F. Wong , University of Texas at Austin
pp. 436

Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications (Abstract)

T. Adler , Infineon Technologies AG
E. Barke , Infineon Technologies AG
pp. 446
6D: Analogue Aspects of System Testing

Alternative Test Methods Using IEEE 1149.4 (Abstract)

Franc Novak , Jozef Stefan Institute
Srecko Macek , Jozef Stefan Institute
Uros Kac , Jozef Stefan Institute
pp. 463

A Fault Simulation Methodology for MEMS (Abstract)

Richard Rosing , Lancaster University
pp. 476
7A: Abstraction Techniques

Abstraction from Counters: An Application on Real-Time Systems (Abstract)

G. Logothetis , Universit?t Karlsruhe
K. Schneider , Universit?t Karlsruhe
pp. 486
7B: Panel Session — A Design Automation Roadmap for Europe

Panel Session (PDF)

pp. null

A Design Automation Roadmap for Europe Panel discussion (Abstract)

Frank Ghenassia , STMicroelectronics
Anton Sauer , Medea Office
Joseph Borel , STMicroelectronics
Jean-Jacques Bronner , Alcatel Business Systems
pp. 510
7C: Interconnect Modelling and Analysis

Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model (Abstract)

D.F. Wong , University of Texas at Austin
Youxin Gao , University of Texas at Austin
pp. 512

Clocktree RLC Extraction with Efficient Inductance Modeling (Abstract)

Weize Xie , Hewlett-Packard Laboratories
Norman Chang , Hewlett-Packard Laboratories
Lei He , University of Wisconsin at Madison
O. Sam Nakagawa , Hewlett-Packard Laboratories
Shen Lin , Hewlett-Packard Laboratories
pp. 522

All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses (Abstract)

Chauchin Su , National Central University
Gen-Nan Chen , National Central University
Yue-Tsang Chen , National Central University
Chung-Len Lee , National Chiao-Tung University
Mu-Jeng Huang , National Central University
pp. 527
7D: Mixed A/D System Design

A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters (Abstract)

Adoracion Rueda , Universidad de Sevilla
Antonio J. Acosta , Universidad de Sevilla
Eduardo Peralias , Universidad de Sevilla
Jose L. Huertas , Universidad de Sevilla
pp. 534
8A: Scheduling and Timing Analysis for Real-Time Embedded Systems

Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis (Abstract)

Zebo Peng , Link?ping University
Paul Pop , Link?ping University
Petru Eles , Link?ping University
pp. 567
8B: Hot Topic

Hot Topic (PDF)

pp. null
8D: Dependability Issues in Advanced ICs and Systems

Evaluating System Dependability in a Co-Design Framework (Abstract)

M. Lajolo , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
L. Lavagno , Universit? di Udine
M. Violante , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
pp. 586

Detection of Defective Sensor Elements Using -Modulation and a Matched Filter (Abstract)

O. Machul , Fraunhofer Institute of Microelectronic Circuits and Systems
D. Hammerschmidt , Fraunhofer Institute of Microelectronic Circuits and Systems
D. Weiler , Fraunhofer Institute of Microelectronic Circuits and Systems
B. J. Hosticka , Fraunhofer Institute of Microelectronic Circuits and Systems
pp. 599
9A: High-Level Power Optimization

System Level Online Power Management Algorithms (Abstract)

Dinesh Ramanathan , University of California at Irvine
Rajesh Gupta , University of California at Irvine
pp. 606

Architectural Power Optimization by Bus Splitting (Abstract)

Massoud Pedram , University of Southern California
Cheng-Ta Hsieh , University of Southern California
pp. 612

Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths (Abstract)

M. Münch , University of Kaiserslautern
R. Mehra , Synopsys Incorporated
B. Wurth , Infineon Technologies AG
J. Sproch , Synopsys Incorporated
N. Wehn , University of Kaiserslautern
pp. 624
9B: Panel Session

The Future of Flexible HW Platform Architectures Panel Discussion (Abstract)

Oz Levia , Improv Systems Incorporated
Vassiliadis Stamatis , Technical University of Delft
Kees Vissers , Philips Research
Pierre Paulin , STMicroelectronics
Grand Martin , Cadence
Rolf Ernst , Technical University of Braunschweig
pp. 634
9C: Embedded Tutorial

Designing Closer to the Edge (Abstract)

Sani R. Nassif , IBM Austin Research Laboratory
pp. 636
9D: Defect Oriented Test

Parametric Fault Simulation and Test Vector Generation (Abstract)

Bozena Kaminska , Fluence Technology
Naim Ben-Hamida , Fluence Technology
Khaled Saab , Fluence Technology
pp. 650
10A: Simulation and Emulation

Parallel and Distributed VHDL Simulation (Abstract)

C.J. Richard Shi , University of Washington
Dragos Lungeanu , University of Iowa
pp. 658

Fast Hardware-Software Coverification by Optimistic Execution of Real Processor (Abstract)

Kyungseok Rha , Seoul National University
Jong-Eun Lee , Seoul National University
Youngchul Cho , Seoul National University
Jinyong Jung , Seoul National University
Kiyoung Choi , Seoul National University
Sungjoo Yoo , Seoul National University
pp. 663
10B: Embedded System Design Frameworks

An Object Oriented Design Method for Reconfigurable Computing Systems (Abstract)

Martyn Edwards , University of Manchester Institute of Science and Technology
Peter Green , University of Manchester Institute of Science and Technology
pp. 692
10D: Power and Cost Issues in Testing

Cost and Benefit Models for Logic and Memory BIST (Abstract)

Cheng-Wen Wu , National Tsing Hua University
Juin-Ming Lu , National Tsing Hua University
pp. 710
Poster Papers

Dynamic Power Management of Laptop Hard Disk (Abstract)

Peter Glynn , University of Bologna
Tajana Simunic , Stanford University
Luca Benini , Stanford University
Giovanni de Micheli , University of Bologna
pp. 736

XFridge: A SPICE-Based, Portable, User-Friendly Cell-Level Sizing Tool (Abstract)

F.M. Pérez-Montes , Centro Nacional de Microelectr?nica at Sevilla
F.V. Fernández , Centro Nacional de Microelectr?nica at Sevilla
R. Domínguez-Castro , Centro Nacional de Microelectr?nica at Sevilla
A. Rodríguez-Vázquez , Centro Nacional de Microelectr?nica at Sevilla
F. Medeiro , Centro Nacional de Microelectr?nica at Sevilla
pp. 739

Evaluation of Interconnects with TDR (Abstract)

Ulf Pillkahn , Siemens AG Munich
pp. 740

Structural Testing on Real Boards (Abstract)

Michael Bosch , Universit?t des Saarlandes
Peter Bach , Universit?t des Saarlandes
pp. 741

Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams (Abstract)

Jaan Raik , Tallinn Technical University
Adam Morawiec , TIMA Laboratory
Raimund Ubar , Tallinn Technical University
pp. 743

Mixed-Signal BIST Using Correlation and Reconfigurable Hardware (Abstract)

J.S. Duarte , University of Porto
J.S. Matos , University of Porto
J. Machado da Silva , University of Porto
pp. 744

An Experimental Study of Satisfiability Search Heuristics (Abstract)

João P. Marques-Silva , Cadence European Laboratories
Karem A. Sakallah , University of Michigan
Fadi A. Aloul , University of Michigan
pp. 745

A Memory Architecture with 4-Address Configurations for Video Signal Processing (Abstract)

Sunho Chang , Korea Advanced Institute of Science and Technology
Jong-Sun Kim , Korea Advanced Institute of Science and Technology
Lee-Sup Kim , Korea Advanced Institute of Science and Technology
pp. 746

Architecture Exploration of Parameterizable EPIC SOC Architectures (Abstract)

Ashok Halambi , University of California at Irvine
Alex Nicolau , University of California at Irvine
Nikil Dutt , University of California at Irvine
Peter Grun , University of California at Irvine
Radu Cornea , University of California at Irvine
pp. 748

Improving the Schedule Quality of Static-List Time-Constrained Scheduling (Abstract)

Sriram Govindarajan , University of Cincinnati
Ranga Vemuri , University of Cincinnati
pp. 749

Synthesis for Mixed CMOS/PTl Logic (Abstract)

Congguang Yang , University of Massachusetts at Amherst
Maciej Ciesielski , University of Massachusetts at Amherst
pp. 750

TOP: An Algorithm for Three-Level Optimization of PLDs (Abstract)

P. Ellervee , Royal Institute of Technology
D.M. Miller , University of Victoria
J.C. Muzio , University of Victoria
E. Dubrova , Royal Institute of Technology
pp. 751

A Flexible Specification Framework for Hardware-Software Codesign (Abstract)

Santiago Domínguez , Universidad Polit?cnica de Madrid
José Manuel Moya , Universidad de Castilla-La Mancha
Juan Carlos López , Universidad de Castilla-La Mancha
Francisco Moya , Universidad de Castilla-La Mancha
pp. 753

An Integrated Design Environment for Early Stage Conceptual Design (Abstract)

Jingyan Zuo , Motorola Incorporated
Stephen W. Director , University of Michigan
pp. 754

A Web-Based System for Assessing and Searching for Designs (Abstract)

Hilary Kahn , University of Manchester
Nigel Whitaker , University of Manchester
Andy Carpenter , University of Manchester
pp. 755

A Versatile Built-In Self-Test Scheme for Delay Fault Testing (Abstract)

D. Nikolos , University of Patras
A. Arapoyanni , University of Athens
Th. Haniotakis , University of Athens
Y. Tsiatouhas , ISD S.A.
pp. 756

Effective Low Power BIST for Datapaths (Abstract)

D. Gizopoulos , University of Piraeus
A. Paschalis , University of Athens
M. Psarakis , II&T, NCSR "Demokritos"
Y. Zorian , LogicVision
N. Kranitis , II&T, NCSR "Demokritos"
pp. 757

Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level (Abstract)

Jens Schönherr , Fraunhofer-Institut f?r Integrierte Schaltungen
Bernd Straube , Fraunhofer-Institut f?r Integrierte Schaltungen
pp. 759

A Single Phase Latch for High Speed GaAs Domino Circuits (Abstract)

R. Sarmiento , University of Las Palmas de Gran Canaria
J. Sosa , University of Las Palmas de Gran Canaria
S. Nooshabadi , University of Tasmania
A. Núñez , University of Las Palmas de Gran Canaria
J.A. Montiel-Nelson , University of Las Palmas de Gran Canaria
pp. 760

Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit Under Check (Abstract)

Liana B. Mirzoyan , Institute of Informatics & Automation Problems
Valery A. Vardanian , Institute of Informatics & Automation Problems
pp. 762

Efficient Method of Failure Detection in Iterative Array Multiplier (Abstract)

Alexander Drozd , Odessa State Polytechnic University
pp. 764

Index of Authors (PDF)

pp. 767
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