The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (1999)
Munich, Germany
Mar. 9, 1999 to Mar. 12, 1999
ISSN: 1530-1591
ISBN: 0-7695-0078-1
TABLE OF CONTENTS

Reviewers (PDF)

pp. xxv

Best Paper Awards (PDF)

pp. xxvii

Tutorials (PDF)

pp. xxviii
Embedded System Design — The European Technology Driver

null (PDF)

pp. null
1A: Verification of Sequential Circuits

Computing Timed Transition Relations for Sequential Cycle-Based Simulation (Abstract)

Paolo Camurati , Politecnico di Torino
Gianpiero Cabodi , Politecnico di Torino
Stefano Quer , Politecnico di Torino
Claudio Passerone , Politecnico di Torino
pp. 8
1B: Architectural Issues in Low Power Design

FSMD Functional Partitioning for Low Power (Abstract)

Enoch Hwang , University of California at Riverside
Yu-Chin Hsu , University of California at Riverside
Frank Vahid , University of California at Riverside
pp. 22

A New Parameterizable Power Macro-Model for Datapath Components (Abstract)

Lars Kruse , OFFIS Research Institute, Oldenburg
Wolfgang Nebel , OFFIS Research Institute, Oldenburg
Gerd Jochens , OFFIS Research Institute, Oldenburg
Eike Schmidt , OFFIS Research Institute, Oldenburg
pp. 29
1C: Design Reuse Repository and IP Architecture
2A: High Level Verification

Formal Verification of Word-Level Specifications (Abstract)

Stefan Höreth , Siemens Corporate R&D and Darmstadt University of Technology
Rolf Drechsler , Albert-Ludwigs-University
pp. 52

Automatic Verification of Scheduling Results in High-Level Synthesis (Abstract)

Holger Hinrichsen , Darmstadt University of Technology
Hans Eveking , Darmstadt University of Technology
Gerd Ritter , Darmstadt University of Technology
pp. 59
2B: System-Level Power Optimization

Battery-Powered Digital CMOS Design (Abstract)

Massoud Pedram , University of Southern California
Qing Wu , University of Southern California
pp. 72

Dynamic Power Management for non-stationary service requests (Abstract)

Giovanni de Micheli , Computer System Laboratory
Eui-Young Chung , Stanford University
Luca Benini , Universit? di Bologna
Alessandro Bogliolo , Universit? di Bologna
pp. 77

On Reducing Transitions Through Data Modifications (Abstract)

Rajeev Murgai , Fujitsu Laboratories of America, Inc.
Masahiro Fujita , Fujitsu Laboratories of America, Inc.
pp. 82
2C: Reconfigurability and Other Issues in Embedded System Design
2E: Embedded Core Test Approaches

Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks (Abstract)

Y. Tsiatouhas , ISD S.A
D. Nikolos , University of Patras and Computer Technology Institute
Th. Haniotakis , ISD S.A
H. T. Vergos , University of Patras and Computer Technology Institute
pp. 112

An Effective BIST Architecture for Fast Multiplier Cores (Abstract)

N. Kranitis , Institute of Informatics & Telecommunications, NCSR "Demokritos"
D. Gizopoulos , 4PLUS Technologies
M. Psarakis , Institute of Informatics & Telecommunications, NCSR "Demokritos"
Y. Zorian , LogicVision
A. Paschalis , Institute of Informatics & Telecommunications, NCSR "Demokritos"
pp. 117
3A: Use of Combinational Verification

An Efficient Filter-Based Approach for Combinational Verification (Abstract)

Donald S. Fussell , University of Texas at Austin
Jawahar Jain , Fujitsu Laboratories of America
Masahiro Fujita , Fujitsu Laboratories of America
Rajarshi Mukherjee , Fujitsu Laboratories of America
Jacob A. Abraham , University of Texas at Austin
Koichiro Takayama , Fujitsu Laboratories of America
pp. 132

Formally Verified Redundancy Removal (Abstract)

Luc Claesen , IMEC vzw/Katholieke Universiteit Leuven
Stefan Hendricx , IMEC vzw/Katholieke Universiteit Leuven
pp. 150
3B: Gate Level Power Estimation and Optimization

Logic Transformation for Low Power Synthesis (Abstract)

Ki-Wook Kim , University of Illinois at Urbana-Champaign
Sung-Mo Kang , University of Illinois at Urbana-Champaign
Ting Ting Hwang , Tsing Hua University
C.L. Liu , Tsing Hua University
pp. 158

Glitch Power Minimization by Gate Freezing (Abstract)

R. Scarsi , Politecnico di Torino
A. Macii , Politecnico di Torino
G. de Micheli , Stanford University
L. Benini , Universit? di Bologna
E. Macii , Politecnico di Torino
M. Poncino , Politecnico di Torino
pp. 163

Spanning Tree-based State Encoding for Low Power Dissipation (Abstract)

Reiner Kolla , Universitaet Wuerzburg
Winfried Noeth , Universitaet Wuerzburg
pp. 168
3C: Special Session — Virtual Socket Interface Alliance

Special Session (PDF)

pp. null

Virtual Socket Interface Alliance (Abstract)

Ralf Seepold , Forschungszentrum Informatik an der Universit?t Karlsruhe (FZI)
pp. 182
3D: Speakers
3E: Fault Diagnosis Techniques for Analogue Circuits

A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester (Abstract)

Marcelo Lubaszewski , Universidade Federal do Rio Grande do Sul
Erika F. Cota , Universidade Federal do Rio Grande do Sul
Luigi Carro , Universidade Federal do Rio Grande do Sul
pp. 184

Minimal Length Diagnostic Tests for Analog Circuits using Test History (Abstract)

Alfred V. Gomes , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 189

Parametric Fault Diagnosis for Analog Systems Using Functional Mapping 1 (Abstract)

A. Chatterjee , Georgia Institute of Technology
S. Cherubal , Georgia Institute of Technology
pp. 195
4A: Resource Sharing in Architectural Synthesis

Time Constrained Modulo Scheduling with Global Resource Sharing (Abstract)

Friedrich Beckmann , Siemens AG
Christoph Jäschke , University of Bremen
Rainer Laur , University of Bremen
pp. 210

Polynomial Methods for Allocating Complex Components (Abstract)

James Smith , Stanford University
Giovanni de Micheli , Stanford University
pp. 217
4B: Mixed Signal Characterization and Test

Fast, Robust DC and Transient Fault Simulation for Nonlinear Analog Circuits (Abstract)

Z.R. Yang , University of Southampton
M. Zwolinski , University of Southampton
pp. 244

On Analog Signature Analysis (Abstract)

Sandi Klavzar , University of Maribor
Bojan Hvala , University of Maribor
Franc Novak , Jozef Stefan Institute
pp. 249
4C: System Design Methodologies: Modelling, Analysis, Refinement and Synthesis

MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis (Abstract)

Robert P. Dick , Princeton University
Niraj K. Jha , Princeton University
pp. 263
4E: High Level Test Synthesis

Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs (Abstract)

Joan Carletta , Case Western Reserve University
Christos Papachristou , Case Western Reserve University
Mehrdad Nourani , Case Western Reserve University
pp. 278

Channel-Based Behavioral Test Synthesis for Improved Module Reachability (Abstract)

Yiorgos Makris , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 283
5A: High-Level System Simulation

High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalability (Abstract)

Jiro Naganuma , NTT Human Interface Laboratories
Makoto Endo , NTT Human Interface Laboratories
Takeshi Ogura , NTT Human Interface Laboratories
Hiroe Iwasaki , NTT Human Interface Laboratories
Katsuyuki Ochiai , NTT Human Interface Laboratories
pp. 303

Fast Hardware-Software Co-simulation Using VHDL Models (Abstract)

Alberto Sangiovanni-Vincentelli , University of California at Berkeley
Marco Sgroi , University of California at Berkeley
Luciano Lavagno , Cadence Berkeley Labs
Bassam Tabbara , University of California at Berkeley
pp. 309
5B: Analogue Circuit Sizing and Synthesis

Systematic Biasing of Negative Feedback Amplifiers (Abstract)

A. Van Staveren , Delft University of Technology
C. Verhoeven , Delft University of Technology
pp. 318

Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints (Abstract)

K. Antreich , Institute of Electronic Design Automation
R. Schwencker , Institute of Electronic Design Automation and Technical University of Munich
H. Graeb , Institute of Electronic Design Automation
J. Eckmueller , Technical University of Munich
pp. 323
5C: VHDL-AMS and HDL Interoperability
5E: Transistor Level Test

Design For Testability Method for CML Digital Circuits (Abstract)

Nanhan Xiong , Ecole Polytechnique
Saman M.I. Adham , Nortel Networks
Yvon Savaria , Ecole Polytechnique
Bernard Antaki , Ecole Polytechnique
pp. 360

On the Design of Self-Checking Functional Units Based on Shannon Circuits (Abstract)

Michele Favalli , DI - University of Ferrara
Cecilia Metra , DEIS - University of Bologna
pp. 368

Parametric Built-In Self-Test of VLSI Systems (Abstract)

M. Rüffer , University of Hannover
D. Niggemeyer , University of Hannover
pp. 376
6A: Hot Topic — Hardware Synthesis from C/C++ Models

Hot Topic (PDF)

pp. null

Hardware Synthesis from C/C++ Models (Abstract)

Giovanni de Micheli , Stanford University
pp. 382

C for System Level Design (Abstract)

Guido Arnout , CoWare, Inc.
pp. 384

Hardware Synthesis from C/C++ (Abstract)

Abhijit Ghosh , Synopsys Inc.
Joachim Kunkel , Synopsys Inc.
Stan Liao , Synopsys Inc.
pp. 387

C-based Synthesis Experiences with a Behavior Synthesizer, "Cyber" (Abstract)

Kazutoshi Wakabayashi , C&C Media Research Laboratories, NEC Corp.
pp. 390
6B: Analogue Modelling and Simulation

Efficient Techniques for Accurate Extraction and Modeling of Substrate Coupling in Mixed-Signal IC's (Abstract)

L. Miguel Silveira , Instituto Superior Tecnico
Mike Chou , Massachusetts Institute of Technology
Joao Paulo Costa , Instituto Superior Tecnico
pp. 396

A Power Estimation Model for High-Speed CMOS A/D Converters (Abstract)

E. Lauwers , Katholieke Universiteit Leuven
G. Gielen , Katholieke Universiteit Leuven
pp. 401

An Accurate Error Control Mechanism for Simplification Before Generation Algorihms (Abstract)

E. Roca , Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
O. Guerra , Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
F. V. Fernández , Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
A. Rodríguez-Vázquez , Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
J. D. Rodríguez-García , Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
pp. 412
6C: Hot Topic — Chip Package Co-Design
6E: Panel
7A: Functional Verification
7B: Bit-Level Logic and Analogue Simulation

Cycle-based Simulation with Decision Diagrams (Abstract)

Raimund Ubar , Tallinn Technical University
Jaan Raik , Tallinn Technical University
Adam Morawiec , TIMA Laboratory
pp. 454

Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach (Abstract)

U.G. Baitinger , University of Stuttgart
M. Bühler , University of Stuttgart
M. Papesch , University of Stuttgart
K. Kapp , University of Stuttgart
pp. 459
7E: Partial and Boundary Scan Test

Full Scan Fault Coverage With Partial Scan (Abstract)

Xijiang Lin , Mentor Graphics Corporation
Irith Pomeranz , University of Iowa
Sudhakar M. Reddy , University of Iowa
pp. 468
8A: New Languages for System Specification and Design
8B: Circuit Analysis and Design

How to use Knowledge in an Analysis Process (Abstract)

Heiko Holzheuer , C-LAB, Cooperation of Universit?t-GH Paderborn and Siemens AG
pp. 498

Digital MOS Circuit Partitioning with Symbolic Modeling (Abstract)

Jordi Carrabina , Autonomous University of Barcelona (UAB)
Lluis Ribas , Autonomous University of Barcelona (UAB)
pp. 503

High Speed GaAs Subsystem Design using Feed Through Logic (Abstract)

R. Sarmiento , University of Las Palmas de Gran Canaria
A. Nunez , University of Las Palmas de Gran Canaria
V. de Armas , University of Las Palmas de Gran Canaria
J. A. Montiel-Nelson , University of Las Palmas de Gran Canaria
S. Nooshabadi , University of Las Palmas de Gran Canaria
pp. 509
8C: Logic Synthesis

Logic Synthesis (PDF)

pp. null

Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization (Abstract)

José A. Espejo , Universidad Carlos III de Madrid
Luis Entrena , Universidad Carlos III de Madrid
Enrique San Millán , Universidad Carlos III de Madrid
Fulvio Corno , Politecnico di Torino
Silvia Chiusano , Politecnico di Torino
pp. 516

Algorithms for Solving Boolean Satisfiability in Combinational Circuits (Abstract)

Luís Guerra e Silva , Instituto Superior T?cnico
L. Miguel Silveira , Instituto Superior T?cnico
João Marques-Silva , Instituto Superior T?cnico
pp. 526

Wavefront Technology Mapping (Abstract)

Leon Stok , IBM
Mahesh A. Iyer , Synopsys Inc.
pp. 531
8E: IDDX Testing and Defect Modelling

On-Chip Transient Current Monitor for Testing of Low Voltage CMOS IC (Abstract)

V. Stopjaková , Slovak Technical University
H. Manhaeve , Department of Microelectronics, KHBO
M. Sidiropulos , Technical University of Brno
pp. 538
9A: HW/SW Interface Synthesis and Partitioning
9B: Physical Design Issues

Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs (Abstract)

Gabriele Saucier , Institut National Polytechnique de Grenoble
Helena Krupnova , Institut National Polytechnique de Grenoble
pp. 587
9C: Reliability and Symmetry in Architectural Synthesis

Self Recovering Controller and Datapath Codesign (Abstract)

Andre Hertwig , University GH Siegen
Alex Orailoglu , University of California at San Diego
Samuel N. Hamilton , University of California at San Diego
pp. 596

Identification and Exploitation of Symmetries in DSP Algorithms (Abstract)

C.A.J. Van Eijk , Eindhoven University of Technology
A.H. Timmer , Philips Research Laboratories
E.T.A.F. Jacobs , Eindhoven University of Technology
B. Mesman , Eindhoven University of Technology and Philips Research Laboratories
pp. 602

Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation (Abstract)

Luiz C.V. dos Santos , Eindhoven University of Technology
Jochen A.G. Jess , Eindhoven University of Technology
pp. 609
9D: Panel — Single Chip or Hybrid System Integration?

Panel (PDF)

pp. null
9E: Testing Regular Structures and Delay Faults

ATPG Tools for Delay Faults at the Functional Level (Abstract)

M. Michael , The Univerity of Arizona
S. Tragoudas , The Univerity of Arizona
pp. 631
10A: Retiming

Retiming (PDF)

pp. null

Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence (Abstract)

Priyank Kalla , University of Massachusetts at Amherst
Maciej J. Ciesielski , University of Massachusetts at Amherst
pp. 638

Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits (Abstract)

Eby G. Friedman , University of Rochester
Marios C. Papaefthymiou , University of Michigan
Xun Liu , University of Michigan
pp. 643

Retiming Sequential Circuits with Multiple Register Classes (Abstract)

Klaus Eckl , Technical University of Munich
Christian Legl , Technical University of Munich
pp. 650
10B: Modelling of Interconnects

Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs (Abstract)

Frank Cano , Texas Instruments Inc.
Rakesh Chadha , Bell Laboratories
Lun Ye , Bell Laboratories
Peter Feldmann , Bell Laboratories
Foong-Charn Chang , Bell Laboratories
Nagaraj Ns , Texas Instruments Inc.
pp. 658

Coupled Noise Estimation for Distributed RC Interconnect Model (Abstract)

Ernest S. Kuh , University of California at Berkeley
Janet M. Wang , University of California at Berkeley
Qingjian Yu , University of California at Berkeley
pp. 664
10C: Design Reuse Methodologies for Virtual Components and IP

Object-Oriented Reuse Methodology for VHDL (Abstract)

Wolfgang Rosenstiel , Universit?t T?bingen
Cristina Barna , Forschungszentrum Informatik
pp. 689
10D: Embedded Tutorial — Multilanguage System Design

Multi-Language System Design (Abstract)

Ahmed Jerraya , TIMA Laboratory
Rolf Ernst , Technical University Braunschweig
pp. 696
10E: RAM BIST

RAM BIST (PDF)

pp. null
11B: Panel — Java, VHDL-AMS, Ada or C for System Level Specifications?

Panel (PDF)

pp. null

Case Study: System Model of Crane and Embedded Control (Abstract)

Wolfgang Nebel , Universit?t Oldenburg and OFFIS
Eduard Moser , Robert Bosch GmbH, FV/FLI
pp. 721
11C: Hot Topic — IP and Reuse

IP and Reuse (PDF)

pp. null

Virtual Components Application and Customization (Abstract)

Bernard Laurent , ASIC Product Line
Jean-François Agaësse , ASIC Product Line
pp. 726
11D: Special Session—Large European Programs in Microelectronic System and Circuit Design

Special Session (PDF)

pp. null
11E: Speakers
11F: Sequential Circuit Test Generation

Sequential Circuit Test Generation Using Decision Diagram Models (Abstract)

Jaan Raik , Tallinn Technical University
Raimund Ubar , Tallinn Technical University
pp. 736

Illegal State Space Identification for Sequential Circuit Test Generation (Abstract)

M. Konijnenburg , Delft University of Technology
A. van de Goor , Delft University of Technology
J. Van der Linden , Delft University of Technology
pp. 741

FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy (Abstract)

Elizabeth M. Rudnick , University of Illinois
Yanti Santoso , University of Illinois
Miron Abramovici , Bell Labs - Lucent Technologies
Matthew Merten , University of Illinois
pp. 747
Posters

Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms (Abstract)

Matteo Sonza Reorda , Politecnico di Torino
Giovanni Squillero , Politecnico di Torino
Fulvio Corno , Politecnico di Torino
pp. 754

Emulation of a Fast Reactive Embedded System using a Real Time Operating System (Abstract)

Wolfgang Rosenstiel , University of T?bingen
Thorsten Steckstor , University of T?bingen
Karlheinz Weiß , University of T?bingen
pp. 764

ADOLT -- An ADaptable On - Line Testing Scheme for VLSI Circuits (Abstract)

A. Maamar , The University of Newcastle upon Tyne
G. Russell , The University of Newcastle upon Tyne
pp. 770

A Method of Distributed Controller Design for RTL Circuits (Abstract)

Chris Papachristou , Case Western Reserve University
Yusuf Alzazeri , Case Western Reserve University
pp. 774

OTA Amplifiers Design on Digital Sea-of-Transistors Array (Abstract)

Sergio Bampi , Federal University of Rio Grande do Sul - UFRGS
Jung Hyun Choi , Federal University of Rio Grande do Sul - UFRGS
pp. 776

A DAG-Based Design Approach for Reconfigurable VLIW Processors (Abstract)

M. Sami , Politecnico di Milano
L. Pozzi , Politecnico di Milano
C. Alippi , Politecnico di Milano
W. Fornaciari , Politecnico di Milano
pp. 778

A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis (Abstract)

Jue Wu , Sun Microsystems
Elizabeth M. Rudnick , University of Illinois
Gary S. Greenstein , Synopsys, Inc.
pp. 780

Software Bit-Slicing: A Technique for Improving Simulation Performance (Abstract)

William J. Schilp , University of South Florida
Peter M. Maurer , University of South Florida
pp. 786

Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI (Abstract)

Debra Corlette , Cadence Design Systems, Inc.
Charles Dawson , Cadence Design Systems, Inc.
Mike Floyd , Cadence Design Systems, Inc.
Françoise Martinolle , Cadence Design Systems, Inc.
pp. 788

Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL Technique (Abstract)

Andrzej Pulka , Silesian Technical University
Jerzy Dabrowski , Silesian Technical University
pp. 790

Index of Authors (PDF)

pp. 795
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