The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (1998)
Paris, France
Feb. 23, 1998 to Feb. 26, 1998
ISBN: 0-8186-8359-7
TABLE OF CONTENTS

Vendors Committee (PDF)

pp. xxii

Tutorials (PDF)

pp. xxx

List of Reviewers (PDF)

pp. xxxiii
Session 1A: Design Optimization of Building Blocks

Collapsing the Transistor Chain to an Effective Single Equivalent Transistor (Abstract)

S. Nikolaidis , Aristotle University of Thessaloniki
A. Chatzigeorgiou , Aristotle University of Thessaloniki
pp. 2

Design of Fault-Secure Parity-Prediction Booth Multipliers (Abstract)

R.O. Duarte , TIMA Laboratory, France
M. Nicolaidis , TIMA Laboratory, France
pp. 7

PASTEL: A Parameterized Memory Characterization System (Abstract)

Kimihiro Ogawa , Sony, Custom DA Section
Michinari Kohno , Sony, Custom DA Section
Fusako Kitamura , Sony, Custom DA Section
pp. 15
Session 1B: HW/SW Partitioning and Communication Synthesis

Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System (Abstract)

Peter V. Knudsen , Technical University of Denmark
Jan Madsen , Technical University of Denmark
Jesper Grode , Technical University of Denmark
pp. 22

Hardware Software Partitioning with Integrated Hardware Design Space Exploration (Abstract)

Ranga Vemuri , University of Cincinnati
Shankar Radhakrishnan , University of Cincinnati
Vinoo Srinivasan , University of Cincinnati
pp. 28

Generation of Interconnect Topologies for Communication Synthesis (Abstract)

M. Muench , University of Kaiserslautern
M. Glesner , Darmstadt University of Technology
M. Gasteier , Darmstadt University of Technology
pp. 36
Session 1C: Asynchronous and Hybrid VHDL-Based Design

The Design of an Asynchronous VHDL Synthesizer (Abstract)

Wen-Fang Yen , National Taipei University of Technology
Sun-Yen Tan , University of Manchester
Stephen B. Furber , University of Manchester
pp. 44

Repartitioning and Technology-Mapping of Electronic Hybrid Systems (Abstract)

Christoph Grimm , Goethe-University Frankfurt
Klaus Waldschmidt , Goethe-University Frankfurt
pp. 52
Session 1D: Data Path and FPGA Testing

Scheduling and Module Assignment for Reducing Bist Resources (Abstract)

Sandeep K. Gupta , University of Southern California
Ishwar Parulkar , University of Southern California
Melvin A. Breuer , University of Southern California
pp. 66

RAM-Based FPGA's: A Test Approach for the Configurable Logic (Abstract)

J. Figueras , UPC Diagonal
Y. Zorian , Logic Vision Inc.
J. M. Portal , LIRMM-UM2
M. Renovell , LIRMM-UM2
pp. 82
Session 2A: Design Methods for High Performance Applications

ATM Traffic Shaper: ATS (Abstract)

Jesus Crespo , Telefonica Investigacion y Desarrollo, Madrid
Pierre Plaza , Telefonica Investigacion y Desarrollo, Madrid
Juan Carlos Diaz , Telefonica Investigacion y Desarrollo, Madrid
pp. 96

XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers (Abstract)

D. R. Lopez , Instituto de Microelectronica de Sevilla.
E. Lago , Instituto de Microelectronica de Sevilla.
C. J. Jimenez , Instituto de Microelectronica de Sevilla.
A. Barriga , Instituto de Microelectronica de Sevilla.
S. Sanchez-Solano , Instituto de Microelectronica de Sevilla.
pp. 102

High Speed Neural Network Chip for Trigger Purposes in High Energy Physics (Abstract)

W. Eppler , Forschungszentrum Karlsruhe (FZK)
A. Menchikov , Joint Institute for Nuclear Research (JINR)
H. Gemmeke , Forschungszentrum Karlsruhe (FZK)
T. Fischer , Forschungszentrum Karlsruhe (FZK)
pp. 108
Session 2B: Scheduling in Embedded Systems

Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor (Abstract)

Jeroen A.J. Leijten , Philips Research Laboratories
Jochen A.G. Jess , Philips Research Laboratories
Jef L. Van Meerbergen , Philips Research Laboratories
Adwin H. Timmer , Philips Research Laboratories
pp. 125
Session 2C: Advanced Techniques for VHDL Design

Model Abstraction for Formal Verification (Abstract)

Yee-Wing Hsieh , University of Pittsburgh
Steven P. Levitan , University of Pittsburgh
pp. 140

VHDL Modelling and Analysis of Fault Secure Systems (Abstract)

Jason Coppens , Royal Military College of Canada
Come Rozon , Royal Military College of Canada
Dhamin Al-Khalili , Royal Military College of Canada
pp. 148

Register Transfer Level VHDL Models without Clocks (Abstract)

Matthias Mutz , SICAN Braunschweig GmbH, Digital IC Center
pp. 153

Parallel VHDL Simulation (Abstract)

Edwin Naroska , University of Dortmund
pp. 159
Session 2D: Novel BIST Approaches

Testing DSP Cores Based on Self-Test Programs (Abstract)

Wei Zhao , Rockwell Semiconductor Systems Computer Engineering Department
Chris Papachristou , Rockwell Semiconductor Systems Computer Engineering Department
pp. 166

Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs (Abstract)

V. N. Yarmolik , Belarussian State University of Informatics and Radioelectronics
H.-J. Wunderlich , University of Stuttgart
S. Hellebrand , University of Stuttgart
pp. 173

Built-In Self-Test with an Alternating Output (Abstract)

Y. Zorian , Logic Vision Inc.
T. Bogue , University of Waterloo
H. Jürgensen , The University of Western Ontario
M. Gössel , Universit?t Potsdam
pp. 180
Session 3A: Architectures for Image Processing

From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms (Abstract)

Martin Kayss , Siemens Corporate Technology
Thomas Hollstein , Darmstadt University of Technology
Juergen Deicke , Darmstadt University of Technology
Claus Schneider , Siemens Corporate Technology
pp. 186

Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications (Abstract)

T.C.B. Yu , University of Reading
K. Eshrahian , Edith Cowan University
S.W. Lachowicz , Edith Cowan University
A.M. Rassau , University of Reading
H. Cheung , Edith Cowan University
T.D. Wilkinson , University of Cambridge
W.A. Crossland , University of Cambridge
pp. 191

VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform (Abstract)

Jose I. Garcia , University of Zaragoza
Jose I. Artigas , University of Zaragoza
Denis Navarro , University of Zaragoza
Luis A. Barragan , University of Zaragoza
Isidro Urriza , University of Zaragoza
pp. 196
Session 3B: Scheduling and Analysis of HW/SW Systems

A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process (Abstract)

J.A. Maestro , Universidad Complutense - 28040 Madrid, Spain
D. Mozos , Universidad Complutense - 28040 Madrid, Spain
H. Mecha , Universidad Complutense - 28040 Madrid, Spain
pp. 218
Session 3C: Extensions to VHDL

Object-Oriented Modelling of Parallel Hardware Systems (Abstract)

Guido Schumacher , Carl von Ossietzky University Oldenburg
Wolfgang Nebel , Carl von Ossietzky University Oldenburg
pp. 234

A Flexible Message Passing Mechanism for Objective VHDL (Abstract)

Wolfgang Nebel , OFFIS Research Institut, Germany
Wolfram Putzke-Röming , OFFIS Research Institut, Germany
Martin Radetzki , OFFIS Research Institut, Germany
pp. 242

Formal Specification in VHDL for Hardware Verification (Abstract)

Klaus Schneider , Universit? at Karlsruhe
Thomas Kropf , Universit? at Karlsruhe
Ralf Reetz , Verysys GmbH
pp. 257
Session 3D: Error Detection and Design Validation

A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths (Abstract)

Vincenzo Piuri , Politecnico di Milano
Anna Antola , Politecnico di Milano
Mariagiovanna Sami , Politecnico di Milano
pp. 266

Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays (Abstract)

Magdy S. Abadir , Somerset PowerPC Design Center, Motorola, Inc., Austin, Texas
Li-C. Wang , Somerset PowerPC Design Center, Motorola, Inc., Austin, Texas
Jing Zeng , Somerset PowerPC Design Center, IBM, Austin, Texas
pp. 273

Functional Scan Chain Testing (Abstract)

Kwang-Ting Cheng , University of California, Santa Barbara, CA
Malgorzata Marek-Sadowska , University of California, Santa Barbara, CA
Mike Tien-Chien Lee , Avant! Corp.
Douglas Chang , University of California, Santa Barbara, CA
pp. 278
Session 3E: Hot Topic: IP Based System-on-a-Chip Design

Hot Topic (PDF)

pp. null

Design Methodologies for System Level IP (Abstract)

Grant Martin , Cadence Design Systems, Alta Business Unit
pp. 286
Session 4A: Design Reuse Methodologies

A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits (Abstract)

Peter Conradi , Universit?t-GH Siegen
Michael Wahl , Universit?t-GH Siegen
Manfred Koegst , Fraunhofer-Institut f?r Integrierte Schaltungen, EAS Dresden
Dieter Garte , Fraunhofer-Institut f?r Integrierte Schaltungen, EAS Dresden
pp. 292

An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse (Abstract)

Jörg Böttger , Chemnitz University of Technology
Karlheinz Agsteiner , Chemnitz University of Technology
Dieter Monjau , Chemnitz University of Technology
Sören Schulze , Chemnitz University of Technology
pp. 303
Session 4B: Flat and Timing-Driven Processor Design

A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset (Abstract)

Thomas Ludwig , IBM Entwicklung GmbH Boeblingen
Ulrich Baur , IBM Entwicklung GmbH Boeblingen
Thomas Pflueger , IBM Entwicklung GmbH Boeblingen
Bernhard Kick , IBM Entwicklung GmbH Boeblingen
Juergen Koehl , IBM Entwicklung GmbH Boeblingen
pp. 312

Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset (Abstract)

Uwe Fassnacht , IBM Entwicklung GmbH Boeblingen
Juergen Schietke , University of Bonn
pp. 325
Session 4C: Hot Topic: Reconfigurable Systems

An Energy-Conscious Exploration Methodology for Reconfigurable DSPs (Abstract)

Jan Rabaey , University of California, Berkeley
Marlene Wan , University of California, Berkeley
pp. 341

Design Of Future Systems (Abstract)

Ian Page , Oxford University Computing Lab
pp. 343
Session 4D: Digital Simulation and Estimation

AFTA: A Formal Delay Model for Functional Timing Analysis (Abstract)

V. Chandramouli , EECS Department, The University of Michigan,
Jesse P. Whittemore , EECS Department, The University of Michigan,
Karem A. Sakallah , EECS Department, The University of Michigan,
pp. 350

Advanced Optimistic Approaches in Logic Simulation (Abstract)

Y. Tanurhan , Electronic Systems and Microsystems (ESM)
St. Schmerler , Electronic Systems and Microsystems (ESM)
K.D. Miiller-Glaser , Electronic Systems and Microsystems (ESM)
pp. 362
Session 5A: Synthesis of Reprogrammable and Reconfigurable Architectures

A Constraint Driven Approach to Loop Pipelining and Register Binding (Abstract)

Jochen A.G. Jess , Eindhoven University of Technology
Jef L. Van Meerbergen , Philips Research laboratories
Marino T.J. Strik , Philips Research laboratories
Bart Mesman , Philips Research laboratories
Adwin H. Timmer , Philips Research laboratories
pp. 377

Multiple Behavior Module Synthesis Based on Selective Groupings (Abstract)

Ju-Hwan Yi , Korea Advanced Institute of Science and Technology
Seung Ho Hwang , Korea Advanced Institute of Science and Technology
Chong-Min Kyung , Korea Advanced Institute of Science and Technology
In-Cheol Park , Korea Advanced Institute of Science and Technology
Hoon Choi , Korea Advanced Institute of Science and Technology
pp. 384

Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures (Abstract)

Ranga Vemuri , University of Cincinnati
Meenakshi Kaul , University of Cincinnati
pp. 389
Session 5B: Partitioning and Routing

An Effective General Connectivity Concept for Clustering (Abstract)

Jianjian Song , National University of Singapore
Wenjun Zhuang , National University of Singapore
Zhaoxuan Shen , National University of Singapore
pp. 398

Improved Approximation Bounds for the Group Steiner Problem (Abstract)

Alexander Zelikovsky , University of Virginia, Charlottesville
Gabriel Robins , University of Virginia, Charlottesville
C. S. Helvig , University of Virginia, Charlottesville
pp. 406

An Interactive Router for Analog IC Design (Abstract)

Thorsten Adler , University of Hanover
Juergen Schaeuble , Robert Bosch GmbH
pp. 414
Session 5C: Panel - Formal Verification: A New Standard CAD Tool for the Industrial Design Flow

Panel (PDF)

pp. null
Session 5D: Simulation for High-Level Design

A System-Level Co-Verification Environment for ATM Hardware Design (Abstract)

Andrea Mueller , RWTH Aachen, University of Technology
Thorsten Groetker , RWTH Aachen, University of Technology
Guido Post , RWTH Aachen, University of Technology
pp. 424

FRIDGE: A Fixed-Point Design and Simulation Environment (Abstract)

Markus Willems , Aachen University of Technology
Heinrich Meyr , Aachen University of Technology
Martin Coors , Aachen University of Technology
Holger Keding , Aachen University of Technology
pp. 429

Verification by Simulation Comparison using Interface Synthesis (Abstract)

Arno Kunzmann , Universit?t T?bingen
Wolfgang Rosenstiel , Universit?t T?bingen
Cordula Hansen , Universit?t T?bingen
pp. 436
Session 6A: Architectural Synthesis

Layout-Driven High Level Synthesis for FPGA Based Architectures (Abstract)

Fadi J. Kurdahi , University of California, Irvine
Min Xu , University of California, Irvine
pp. 446

Cross-Level Hierarchical High-Level Synthesis (Abstract)

Oliver Bringmann , Forschungszentrum Informatik
Wolfgang Rosenstiel , Universitaet Tuebingen
pp. 451

An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions (Abstract)

Rajesh K. Gupta , University of California, Irvine
Jian Li , University of Illinois at Urbana-Champaign
pp. 457
Session 6B: Timing and Crosstalk in Interconnect

A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction (Abstract)

Ernest Kuh , University of California at Berkeley
Dongsheng Wang , University of California at Berkeley
pp. 466

Interconnect Tuning Strategies for High-Performance Ics (Abstract)

Egino Sarto , Silicon Graphics, Inc.
Sudhakar Muddu , Silicon Graphics, Inc.
Andrew B. Kahng , Silicon Graphics, Inc.
Rahul Sharma , Silicon Graphics, Inc.
pp. 471

A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing (Abstract)

D. F. Wong , University of Texas at Austin
Chris C. N. Chu , University of Texas at Austin
pp. 479
Session 6C: Panel: Next Generation System Design Tools

Panel (PDF)

pp. null
Session 6D: IDDQ and Memory Testing

Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs (Abstract)

R. Rodriguez-Montanes , Universitat Politecnica de Catalunya
J. Figueras , Universitat Politecnica de Catalunya
pp. 490

March Tests for Word-Oriented Memories (Abstract)

I.B.S. Tlili , Delft University of Technology
A.J. van de Goor , Delft University of Technology
pp. 501
Session 7A: Microsystems

Microsystems (PDF)

pp. null

A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation (Abstract)

G. Lorenz P. Schwarz , Robert Bosch GmbH FhG-IIS/EAS
U. Becker , Robert Bosch GmbH FhG-IIS/EAS
J. Haase S. Wünsche , Robert Bosch GmbH FhG-IIS/EAS
R. Neul , Robert Bosch GmbH FhG-IIS/EAS
pp. 510

Fast Field Solvers for Thermal and Electrostatic Analysis (Abstract)

M. Rencz , Technical University of Budapest, Dept. of Electron Devices
V. Szekely , Technical University of Budapest, Dept. of Electron Devices
pp. 518
Session 7B: Interconnect Modeling

Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation (Abstract)

Roland W. Freund , Bell Laboratories, Lucent Technologies
Peter Feldmann , Bell Laboratories, Lucent Technologies
pp. 530

An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models (Abstract)

Mattan Kamon , Massachusetts Institute of Technology
Jacob White , Massachusetts Institute of Technology
L. Miguel Silveira , INESC/Cadence European Laboratories
Nuno Marques , INESC
pp. 538

MCM Interconnect Design Using Two-Pole Approximation (Abstract)

Jianhua Shao , City University of Hong Kong
Richard M.M. Chen , City University of Hong Kong
pp. 544
Session 7C: Design for Manufacturability - Embedded Tutorial

Design-Manufacturing Interface: Part I - Vision (Abstract)

P.K. Nag , Carnegie Mellon University
Hans T. Heineken , Level One Communications
Wojciech Maly , Carnegie Mellon University
J. Khare , Level One Communications
pp. 550

Design-Manufacturing Interface: Part II - Applications (Abstract)

P. Simon , Philips NV, Nijmegen, The Netherlands
C. Ouyang , Carnegie Mellon University
J. Khare , Level One Communications
W. Maly , Carnegie Mellon University
P.K. Nag , Carnegie Mellon University
H.T. Heineken , Level One Communications
pp. 557

Performance - Manufacturability Tradeoffs in IC Design (Abstract)

Hans T. Heineken , Level One Communications
Wojciech Maly , Carnegie Mellon University
pp. 563
Session 7D: Sequential Circuit Testing
Session 8A: Issues in Behavioral Synthesis

Architectural Simulation in the Context of Behavioral Synthesis (Abstract)

A. Jemai , INSAT, Tunis, Tunisia
A.A. Jerraya , TIMA Laboratory, Grenoble, France
P. Kission , ANACAD, Grenoble France
pp. 590

Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols (Abstract)

Anshul Kumar , Indian Institute of Technology
Johnny Öberg , Royal Institute of Technology (KTH)
Ahmed Hemani , Royal Institute of Technology (KTH)
pp. 596

Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs (Abstract)

Alex Orailoglu , University of California, San Diego
Samuel Norman Hamilton , University of California, San Diego
pp. 604
Session 8B: Formal Equivalence Checking Using Decision Diagrams

Dynamic Minimization of Word-Level Decision Diagrams (Abstract)

Rolf Drechsler , Albert-Ludwigs-University
Stefan Horeth , Darmstadt University of Technology
pp. 612

Sequential Equivalence Checking without State Space Traversal (Abstract)

C.A.J. Van Eijk , Eindhoven University of Technology
pp. 618

On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits (Abstract)

Lluis Ribas , Autonomous University of Barcelona (UAB)
Jordi Carrabina , Autonomous University of Barcelona (UAB)
pp. 624
Session 8C: Hot Topic: Silicon Debug of Systems-on-Chips

Hot Topic (PDF)

pp. null
Session 8D: Characterization and Verification of Analogue Circuits

Hierarchical Characterization of Analog Integrated CMOS Circuits (Abstract)

Josef Eckmueller , Siemens AG, Munich
Martin Groepl , Siemens AG, Munich
Helmut E. Graeb , Techn. Univ. Munich
pp. 636

EASY - a System for Computer-Aided Examination of Analog Circuits (Abstract)

G. Droege , SICAN
E.-H. Horneber , Institut fuer Netzwerktheorie und Schaltungstechnik
M. Thole , Institut fuer Netzwerktheorie und Schaltungstechnik
pp. 644
Session 9A: Benchmark Circuits, Technology Mapping and Scan Chains

Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking (Abstract)

Justin Harlow III , National Semiconductor Corporation, Santa Clara
Franc Brglez , CBL (Collaborative Benchmarking Laboratory)
Debabrata Ghosh , CBL (Collaborative Benchmarking Laboratory)
Nevin Kapur , CBL (Collaborative Benchmarking Laboratory)
pp. 656

Technology Mapping for Minimizing Gate and Routing Area (Abstract)

Frank M. Johannes , Technical University of Munich
Guenter Stenz , Technical University of Munich
Aiguo Lu , Technical University of Munich
pp. 664

Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection (Abstract)

Massimo Violante , Politecnico di Torino
Matteo Sonza Reorda , Politecnico di Torino
Fulvio Corno , Politecnico di Torino
Paolo Prinetto , Politecnico di Torino
pp. 670
Session 9B: Physical to Gate Level Design for Low-Power

Temperature Effect on Delay for Low Voltage Applications (Abstract)

J.M. Daga , LIRMM, UMR CNRS
E. Ottaviano , LIRMM, UMR CNRS
D. Auvergne , LIRMM, UMR CNRS
pp. 680

Data Driven Power Optimization of Sequential Circuits (Abstract)

Qi Wang , University of Arizona
Sarma B.K. Vrudhula , University of Arizona
pp. 686

Gated Clock Routing Minimizing the Switched Capacitance (Abstract)

Massoud Pedram , University of Southern California
Jaewon Oh , University of Southern California
pp. 692

Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits (Abstract)

Yi-Min Jiang , University of California, Santa Barbara, CA
Kwang-Ting Cheng , University of California, Santa Barbara, CA
pp. 698
Session 9C: Hot Topic: Embedded Memory and Embedded Logic

Hot Topic (PDF)

pp. null

Embedded DRAM Architectural Trade-Offs (Abstract)

Soeren Hein , Siemens AG
Norbert Wehn , University of Kaiserslautern
pp. 704
Session 9D: Analogue Circuit Modeling and Design Methodology

A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks (Abstract)

R. Rosenberger , Darmstadt University of Technology
S. A. Huss , Darmstadt University of Technology
pp. 721

Switching Response Modeling of the CMOS Inverter for Sub-micron Devices (Abstract)

S. Nikolaidis , Aristotle University of Thessaloniki
L. Bisdounis , University of Patras
C. Goutis , University of Patras
O. Koufopavlou , University of Patras
pp. 729
Session 10A: Combinational Logical Synthesis

An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization (Abstract)

J.W.J.M. Rutten , Eindhoven University of Technology
M.A.J. Kolsteren , Eindhoven University of Technology
C.A.J. Van Eijk , Eindhoven University of Technology
M.R.C.M. Berkelaar , Eindhoven University of Technology
pp. 749

Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions (Abstract)

Hiroshi Sawada , NTT Communication Science Laboratories
Akira Nagoya , NTT Communication Science Laboratories
Shigeru Yamashitam , NTT Communication Science Laboratories
pp. 755
Session 10B: High Level Power Estimation

Power Estimation of Behavioral Descriptions (Abstract)

Enrico Macii , Politecnico di Torino, ITALY
Franco Fummi , Politecnico di Torino, ITALY
Fabrizio Ferrandi , Politecnico di Torino, ITALY
Massimo Poncino , Politecnico di Torino, ITALY
pp. 762

Characterization-Free Behavioral Power Modeling (Abstract)

Luca Benini , CSL - Stanford University
Alessandro Bogliolo , DEIS - University of Bologna
Giovanni de Micheli , CSL - Stanford University
pp. 767

Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation (Abstract)

Radu Marculescu , University of Southern California, Los Angeles, CA 90089
Massoud Pedram , University of Southern California, Los Angeles, CA 90089
Diana Marculescu , University of Southern California, Los Angeles, CA 90089
pp. 774
Session 10C: Petri Nets and Dedicated Formalisms

Efficient Verification using Generalized Partial Order Analysis (Abstract)

Gjalt de Jong , Alcatel Telecom
Bill Lin , University of California, San Diego
pp. 782

Efficient Encoding Schemes for Symbolic Analysis of Petri Nets (Abstract)

Enric Pastor , Universitat Polit`ecnica de Catalunya
Jordi Cortadella , Universitat Polit`ecnica de Catalunya
pp. 790

Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis (Abstract)

Maroun Kassab , Universite de Montreal
Eduard Cerny , Universite de Montreal
Thomas Krodel , Nortel
Sidi Aourid , Universite de Montreal
pp. 796

Combinational Verification based on High-Level Functional Specifications (Abstract)

Evguenii I. Goldberg , Cadence Berkeley Laboratories
Yuji Kukimoto , University of California, Berkeley
Robert K. Brayton , University of California, Berkeley
pp. 803
Session 10D: Mixed-Signal Test and DFT

Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems (Abstract)

Salvador Mir , Universidad de Sevilla
Adoracion Rueda , Universidad de Sevilla
Diego Vazquez , Universidad de Sevilla
Jose Luis Huertas , Universidad de Sevilla
pp. 810

Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults (Abstract)

Thomas J. Vogels , Technical University of Munich
Walter M. Lindermeir , Technical University of Munich
Helmut E. Graeb , Technical University of Munich
pp. 822
Session 11A: Sequential Logic Synthesis

A Dynamic Model for the State Assignment Problem (Abstract)

Jose L. Huertas , Instituto de Microelectronica de Sevilla
Jose M. Quintana , Instituto de Microelectronica de Sevilla
Maria J. Avedillo , Instituto de Microelectronica de Sevilla
Manuel Martinez , Instituto de Microelectronica de Sevilla
pp. 835

Efficient Minarea Retiming of Large Level-Clocked Circuits (Abstract)

Sachin S. Sapatnekar , University of Minnesota, Minneapolis, MN
Naresh Maheshwari , Iowa State University, Ames IA
pp. 840
Session 11B: High-Level Power Optimization

IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits (Abstract)

Ganesh Lakshminarayana , Princeton University, Princeton, NJ 08544
Kamal S. Khouri , Princeton University, Princeton, NJ 08544
Niraj K. Jha , Princeton University, Princeton, NJ 08544
pp. 848

Instruction Scheduling for Power Reduction in Processor-Based System Design (Abstract)

Akihiko Inoue , Kyushu University
Tohru Ishihara , Kyushu University
Hiroyuki Tomiyama , Kyushu University
Hiroto Yasuura , Kyushu University
pp. 855

Address Bus Encoding Techniques for System-Level Power Optimization (Abstract)

Donatella Sciuto , Politecnico di Milano
Enrico Macii , Automatica e Informatica, Torino, Italy
Giovanni de Micheli , Stanford University
Cristina Silvano , Universita` di Brescia
Luca Benini , Stanford University
pp. 861
Session 11C: System Architecture Design

A Scalable Architecture for Multi-threaded JAVA Applications (Abstract)

Michael Mrva , Siemens AG, Corporate Technology, ZT ME 5
Rainer Kress , Siemens AG, Corporate Technology, ZT ME 5
Klaus Buchenrieder , Siemens AG, Corporate Technology, ZT ME 5
pp. 868

Hardware/Software Co-Design of a Fuzzy RISC Processor (Abstract)

Michael Gschwind , Technische Universitaet Wien
Valentina Salapura , Technische Universitaet Wien
pp. 875

Innovative System-level Design Environment Based on FORM for Transport Processing System (Abstract)

Kazuhiro Shirakawa , NTT Optical Network Systems Laboratories
Kazushige Higuchi , NTT Optical Network Systems Laboratories
pp. 883
Session 11D: Simulation and Test Tools for Analogue Circuits

Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's (Abstract)

Mike Chou , Massachusetts Institute of Technology
L. Miguel Silveira , INESC/Cadence European Laboratories
pp. 892

Efficient DC Fault Simulation of Nonlinear Analog Circuits (Abstract)

Michael W. Tian , University of Iowa, Iowa City
C.-J. Richard Shi , University of Iowa, Iowa City
pp. 899
Poster Session

Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems (Abstract)

R. Niemann , University of Dortmund
P. Marwedel , University of Dortmund
pp. 912

A Formal Description of VHDL-AMS Analogue Systems (Abstract)

Tom Kazmierski , University of Southampton
pp. 916

Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique (Abstract)

M.L. Flottes , Micro?lectronique de Montpellier,U.M. CNRS 9928
R. Pires , Micro?lectronique de Montpellier,U.M. CNRS 9928
B. Rouzeyre , Micro?lectronique de Montpellier,U.M. CNRS 9928
L. Volpe , Micro?lectronique de Montpellier,U.M. CNRS 9928
pp. 921

Universal Strong Encryption FPGA Core Implementation (Abstract)

Mario Kovac , University of Zagreb
Davor Runje , University of Zagreb
pp. 923

Data Cache Sizing for Embedded Processor Applications (Abstract)

Alexandru Nicolau , University of California, Irvine
Preeti Ranjan Panda , University of California, Irvine
Nikil D. Dutt , University of California, Irvine
pp. 925

A Programmable Multi-Language Generator for CoDesign (Abstract)

O. Pasquier , IRESTE, University of NANTES, FRANCE
D. Heller , IRESTE, University of NANTES, FRANCE
F. Muller , IRESTE, University of NANTES, FRANCE
J.P. Calvez , IRESTE, University of NANTES, FRANCE
pp. 927

Register-Constrained Address Computation in DSP Programs (Abstract)

Anupam Basu , University of Dortmund, Germany
Rainer Leupers , University of Dortmund, Germany
Peter Marwedel , University of Dortmund, Germany
pp. 929

Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base (Abstract)

Thomas Mueller-Wipperfuerth , Johannes Kepler University Linz, Austria
Richard Hagelauer , Johannes Kepler University Linz, Austria
pp. 931

AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems (Abstract)

George Economakos , National Technical University of Athens
Panayotis Tsanakas , National Technical University of Athens
George Papakonstantinou , National Technical University of Athens
pp. 933

A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor (Abstract)

Holger Völkel , Universit?t Siegen SP3D Chipdesign
Michael G. Wahl , Universit?t Siegen SP3D Chipdesign
pp. 937

A Comparing Study of Technology Mapping for FPGA (Abstract)

Wolfgang Rosenstiel , University of T?bingen
Hans-Georg Martin , University of T?bingen
pp. 939

Tom J. Kazmierski (Abstract)

pp. 941

Optimized Timed Hardware Software Cosimulation without Roll-back (Abstract)

Wonyong Sung , Seoul National University
Soonhoi Ha , Seoul National University
pp. 945

A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design (Abstract)

R. Sarmiento , University of Las Palmas de Gran Canaria
J. A. Montiel-Nelson , University of Las Palmas de Gran Canaria
A. Nunez , University of Las Palmas de Gran Canaria
V. de Armas , University of Las Palmas de Gran Canaria
pp. 947

Architectural Rule Checking for High-level Synthesis (Abstract)

Kayhan Kucukcakar , Unified Design System Laboratory
Jie Gong , Unified Design System Laboratory
Chih-Tung Chen , Unified Design System Laboratory
pp. 949

A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator (Abstract)

Hideaki Kimura , NTT Access Network Systems Laboratories
Norihito Iyenaga , NTT Access Network Systems Laboratories
pp. 951

Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models (Abstract)

Y. Torroja , Universidad Politecnica de Madrid
J. Uceda , Universidad Politecnica de Madrid
E. de la Torre , Universidad Politecnica de Madrid
T. Riesgo , Universidad Politecnica de Madrid
pp. 955

Fault Analysis in Networks with Concurrent Error Detection Properties (Abstract)

Cristiana Bolchini , Dipartimento di Elettronica e Informazione
Donatella Sciuto , Dipartimento di Elettronica e Informazione
Fabio Salice , Dipartimento di Elettronica e Informazione
pp. 957

IOCIMU - An Integrated Off-Chip IDDQ Measurement Unit (Abstract)

M. Svajda , Technical University of Brno
H. Manhaeve , KHBO, Microelectronics Department, Oostende, Belgium
B. Straka , CEDO, Brno
pp. 959

Automatic Topology Optimization for Analog Module Generators (Abstract)

U. Kleine , Otto-von-Guericke-University of Magdeburg
M. Wolf , Otto-von-Guericke-University of Magdeburg
pp. 961

Asynchronous Scheduling and Allocation (Abstract)

Anatoly Prihozhy , State University of Informatics and Radioelectronics of Belarus
pp. 963

Path Verification Using Boolean Satisfiability (Abstract)

Thomas Lindenkreuz , Robert Bosch GmbH
Erich Barke , University of Hanover
Matthias Ringe , Robert Bosch GmbH
pp. 965

PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions (Abstract)

Harm Arts , Ambit Design Systems
Sumit Roy , Ambit Design Systems
Prithviraj Banerjee , Northwestern University, USA
pp. 967

Constraints Space Management for the Layout of Analog IC's (Abstract)

Ralph H.J.M. Otten , Delft University of Technology
Bogdan G. Arsintescu , Delft University of Technology
pp. 971

A Synthesis Procedure for Flexible Logic Functions (Abstract)

Sudhakar M. Reddy , University of Iowa
Irith Pomeranz , University of Iowa
pp. 973

Correct High-Level Synthesis: a Formal Perspective (Abstract)

R. Hermida , Universidad Complutense de Madrid
J.M. Mendias , Universidad Complutense de Madrid
pp. 977

CMOS Combinational Circuit Sizing by Stage-wise Tapering (Abstract)

Satyamurthy Pullela , Monterey Design Systems, San Jose, CA
Rajendran Panda , Motorola Inc., Austin, TX
Abhijit Dharchoudhury , Motorola Inc., Austin, TX
Gopal Vija , Motorola Inc., Austin, TX
pp. 985

Fault Detection for Linear Analog Circuits Using Current Injection (Abstract)

M. Nicolaidis , Reliable Integrated Systems Group, TIMA/INPG
J. Velasco-Medina , Reliable Integrated Systems Group, TIMA/INPG
Th. Calin , Reliable Integrated Systems Group, TIMA/INPG
pp. 987

Author Index (PDF)

pp. 989
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