The Community for Technology Leaders
Design Automation Conference (2004)
San Diego, California, USA
June 7, 2004 to June 11, 2004
ISBN: 1-58113-828-8
TABLE OF CONTENTS
Panel: CEO PANEL: EDA: This is Serious Business
Special Session: HOT Leakage

Design Optimizations for Microprocessors at Low Temperature (Abstract)

Manoj Sachdev , University of Waterloo, Canada
Siva Narendra , Circuits Research
Seri Lee , Platform Technology
Gerhard Schrom , Circuits Research
Yibin Ye , Circuits Research
Greg Chrysler , Advanced Technology, Intel Labs
Vivek De , Circuits Research
Ali Keshavarzi , Circuits Research
Arman Vassighi , Circuits Research
pp. 2-5

Leakage in Nano-Scale Technologies: Mechanisms, Impact and Design Considerations (Abstract)

Amit Agarwal , Purdue University, West Lafayette, IN
Saibal Mukhopadhyay , Purdue University, West Lafayette, IN
Chris H. Kim , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 6-11

System Level Leakage Reduction Considering the Interdependence of Temperature and Leakage (Abstract)

Mircea R. Stan , University of Virginia, Charlottesville
Weiping Liao , University of California, Los Angeles
Lei He , University of California, Los Angeles
pp. 12-17
Clock Routing and Buffering

Reducing Clock Skew Variability via Cross Links (Abstract)

Rabi Mahapatra , Texas A&M University, College Station, TX
Anand Rajaram , Texas A&M University, College Station, TX
Jiang Hu , Texas A&M University, College Station, TX
pp. 18-23

Fast and Flexible Buffer Trees that Navigate the Physical Layout Environment (Abstract)

Stephen T. Quay , IBM Corp., Austin, Texas
Charles J. Alpert , IBM Corp., Austin, Texas
Milos Hrkic , University of Illinois at Chicago
Jiang Hu , Texas A&M University
pp. 24-29

Practical Repeater Insertion For Low Power: What Repeater Library Do We Need? (Abstract)

Xun Liu , North Carolina State University, Raleigh
Marios C. Papaefthymiou , University of Michigan, Ann Arbor
Yuantao Peng , North Carolina State University, Raleigh
pp. 30-35
Tools and Strategies for Dynamic Verification

Industrial Experience with Test Generation Languages for Processor Verification (Abstract)

Michal Rimon , IBM Research Laboratory, Haifa, Israel
Michael Vinov , IBM Research Laboratory, Haifa, Israel
John Ludden , IBM Development Center, Austin, Texas
Michael Behm , IBM Development Center, Austin, Texas
Yossi Lichtenstein , IBM Research Laboratory, Haifa, Israel
pp. 36-40

Defining Coverage Views to Improve Functional Coverage Analysis (Abstract)

Avi Ziv , IBM Research Laboratory in Haifa, Israel
Sigal Asaf , IBM Research Laboratory in Haifa, Israel
Eitan Marcus , IBM Research Laboratory in Haifa, Israel
pp. 41-44

Probabilistic Regression Suites for Functional Verification (Abstract)

Shai Fine , IBM Research Laboratory in Haifa
Shmuel Ur , IBM Research Laboratory in Haifa
Avi Ziv , IBM Research Laboratory in Haifa
pp. 49-54
Timing-Driven System Synthesis

Modular Scheduling of Guarded Atomic Actions (Abstract)

Arvind , Massachusetts Institute of Technology, Cambridge, MA
Daniel L. Rosenband , Massachusetts Institute of Technology, Cambridge, MA
pp. 55-60

Automatic Correct Scheduling of Control Flow Intensive Behavioral Descriptions in Formal Synthesis (Abstract)

Kai Kapp , University of Karlsruhe, Germany
Viktor Sabelfeld , University of Karlsruhe, Germany
pp. 61-66

A Timing-Driven Module-Based Chip Design Flow (Abstract)

Fan Mo , University of California, Berkeley
Robert K. Brayton , University of California, Berkeley
pp. 67-70

Timing Closure through a Globally Synchronous, Timing Partitioned Design Methodology (Abstract)

Christer Svensson , Link?ping University, Sweden
Anders Edman , Link?ping University, Sweden
pp. 71-74
Special Session: Reliable System-on-a-Chip Design in the Nanometer Era

Design and Reliability Challenges in Nanometer Technologies (PDF)

Shekhar Borkar , Circuit Research, Intel Labs, Hillsboro, OR
Vivek De , Circuit Research, Intel Labs, Hillsboro, OR
Tanay Karnik , Circuit Research, Intel Labs, Hillsboro, OR
pp. 75

A Communication-Theoretic Design Paradigm for Reliable SOCs (PDF)

Naresh R. Shanbhag , University of Illinois at Urbana-Champaign
pp. 76

Designing Robust Microarchitectures (PDF)

Todd M. Austin , University of Michigan
pp. 78

Hierarchical Application Aware Error Detection and Recovery (PDF)

Ravishankar K. Iyer , University of Illinois at Urbana-Champaign
pp. 79
Panel: When IC Yield Missed the Target, Who is at Fault?
Power Modeling and Optimization for Embedded Systems

Memory Access Scheduling and Binding Considering Energy Minimization in Multi-Bank Memory Systems (Abstract)

Taewhan Kim , Seoul National University, Korea
Chun-Gi Lyuh , Electronics and Telecommunications Research Institute, Daejeon, Korea
pp. 81-86

Profile-Based Optimal Intra-Task Voltage Scheduling for Hard Real-Time Applications (Abstract)

Jaewon Seo , CS, KAIST
Taewhan Kim , EE, Seoul National Univ.
Ki-Seok Chung , CIC, Hanyang University
pp. 87-92

Requirement-Based Design Methods for Adaptive Communications Links (Abstract)

Juan Antonio Carballo , IBM Austin Research Laboratory, Austin, TX
Clay Cranford , IBM Systems and Technology, Raleigh, NC
Robert Norman , IBM Systems and Technology, Raleigh, NC
Seung-Moon Yoo , IBM Austin Research Laboratory, Austin, TX
Kevin Nowka , IBM Austin Research Laboratory, Austin, TX
Ivan Vo , IBM Austin Research Laboratory, Austin, TX
pp. 93-98

Automated Energy/Performance Macromodeling of Embedded Software (Abstract)

Niraj K. Jha , Princeton University, NJ
Srivaths Ravi , NEC Labs, Princeton, NJ
Anand Raghunathan , NEC Labs, Princeton, NJ
Anish Muttreja , Princeton University, NJ
pp. 99-102

Coding for System-on-Chip Networks: A Unified Framework (Abstract)

Srinivasa R. Sridhara , University of Illinois at Urbana-Champaign
Naresh R. Shanbhag , University of Illinois at Urbana-Champaign
pp. 103-106
Performance Evaluation and Run Time Support

Abstraction of Assembler Programs for Symbolic Worst Case Execution Time Analysis (Abstract)

Klaus Schneider , University of Kaiserslautern, Germany
Tobias Schuele , University of Kaiserslautern, Germany
pp. 107-112

Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration (Abstract)

Sudeep Pasricha , University of California, Irvine, CA
Nikil Dutt , University of California, Irvine, CA
Mohamed Ben-Romdhane , Conexant Systems Inc., Newport Beach, CA
pp. 113-118

Specific Scheduling Support to Minimize the Reconfiguration Overhead of Dynamically Reconfigurable Hardware (Abstract)

Javier Resano , Universidad Complutense de Madrid, Spain
Diederik Verkest , IMEC vzw, Leuven, Belgium IMEC
Serge Vernalde , IMEC vzw, Leuven, Belgium IMEC
Daniel Mozos , Universidad Complutense de Madrid, Spain
Francky Catthoor , IMEC vzw, Leuven, Belgium IMEC
pp. 119-124

LODS: Locality-Oriented Dynamic Scheduling for On-Chip Multiprocessors (Abstract)

Mahmut Kandemir , The Pennsylvania State University, University Park, PA
pp. 125-128

An Area Estimation Methodology for FPGA Based Designs at SystemC-Level (Abstract)

William Fornaciari , Politecnico di Milano - DEI, Italy
Carlo Brandolese , Politecnico di Milano - DEI, Italy
Fabio Salice , Politecnico di Milano - DEI, Italy
pp. 129-132
Advances in Analog Circuit and Layout Synthesis

Automated Design of Operational Transconductance Amplifiers using Reversed Geometric Programming (Abstract)

Robert W. Brodersen , University of California at Berkeley
Johan P. Vanderhaegen , University of California at Berkeley
pp. 133-138

Correct-by-Construction Layout-Centric Retargeting of Large Analog Designs (Abstract)

Nuttorn Jangkrajarng , University of Washington, Seatlle
Sambuddha Bhattacharya , University of Washington, Seatlle
Roy Hartono , University of Washington, Seatlle
C-J. Richard Shi , University of Washington, Seatlle
pp. 139-144

Fast and Accurate Parasitic Capacitance Models for Layout-Aware Synthesis of Analog Circuits (Abstract)

Hemanth Sampath , University of Cincinnati, OH
Anuradha Agarwal , University of Cincinnati, OH
Veena Yelamanchili , University of Cincinnati, OH
Ranga Vemuri , University of Cincinnati, OH
pp. 145-150

ORACLE: Optimization with Recourse of Analog Circuits including Layout Extraction (Abstract)

Stephen P. Boyd , Stanford University, CA
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Yang Xu , Carnegie Mellon University, Pittsburgh, PA
pp. 151-154

A Synthesis Flow Toward Fast Parasitic Closure For Radio-Frequency Integrated Circuits (Abstract)

L. Richard Carley , Carnegie Mellon University, Pittsbugh, PA
Ronald A. Rohrer , Neolinear Inc., Pittsburgh, PA
Gang Zhang , Carnegie Mellon University, Pittsbugh, PA
Aykut Dengi , Neolinear Inc., Pittsburgh, PA
Rob A. Rutenbar , Carnegie Mellon University, Pittsbugh, PA
pp. 155-158
Power Grid Design and Analysis Techniques

Buffer Sizing for Clock Power Minimization Subject to General Skew Constraints (Abstract)

Kai Wang , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 159-164

Optimal Placement of Power Supply Pads and Pins (Abstract)

Vladimir Zolotov , Motorola, Inc., Austin, TX
Min Zhao , Motorola, Inc., Austin, TX
Rajendran Panda , Motorola, Inc., Austin, TX
Yuhong Fu , Motorola, Inc., Austin, TX
Savithri Sundareswaran , Motorola, Inc., Austin, TX
pp. 165-170

A Stochastic Approach To Power Grid Analysis (Abstract)

Vladimir Zolotov , Motorola Inc., Austin, Texas
David Blaauw , University of Michigan, Ann Arbor, MI
Rajendran Panda , Motorola Inc., Austin, Texas
Sanjay Pant , University of Michigan, Ann Arbor, MI
Savithri Sundareswaran , Motorola Inc., Austin, Texas
pp. 171-176

Efficient Power/Ground Network Analysis for Power Integrity-Driven Design Methodology (Abstract)

Yao-Wen Chang , National Taiwan University, Taipei, Taiwan
Su-Wei Wu , Elan Microelectronics Corporation, Hsinchu, Taiwan
pp. 177-180

Reliability-Driven Layout Decompaction for Electromigration Failure Avoidance in Complex Mixed-Signal IC Designs (Abstract)

J? Scheible , Automotive Electronics Division AE/DIC, Germany
G?ran Jerke , Automotive Electronics Division AE/DIC, Germany
Jens Lienig , Dresden Univ. of Technology, Germany
pp. 181-184
Panel: What Happened to ASIC? Go (Recon)figure?
Methods for a Priori Feasible Layout Generation

Optical Proximity Correction (OPC)-Friendly Maze Routing (Abstract)

Li-Da Huang , University of Texas at Austin
Martin D. F. Wong , University of Illinois at Urbana-Champaign
pp. 186-191

Design Automation for Mask Programmable Fabrics (Abstract)

Jamil Kawa , Advanced Technology Group, Synopsys Inc., Mountain View, CA
Narendra V. Shenoy , Advanced Technology Group, Synopsys Inc., Mountain View, CA
Raul Camposano , Advanced Technology Group, Synopsys Inc., Mountain View, CA
pp. 192-197

On Designing Via-Configurable Cell Blocks for Regular Fabrics (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara
Yajun Ran , University of California, Santa Barbara
pp. 198-203

Routing Architecture Exploration for Regular Fabrics (Abstract)

V. Kheterpal , Carnegie Mellon University, Pittsburgh, PA
L. Pileggi , Carnegie Mellon University, Pittsburgh, PA
A. J. Strojwas , Carnegie Mellon University, Pittsburgh, PA
pp. 204-207

Accurate Pre-Layout Estimation of Standard Cell Characteristics (Abstract)

Vamsi Boppana , Zenasis Technologies, Inc., Campbell, CA
Kaushik De , Zenasis Technologies, Inc., Campbell, CA
Hiroaki Yoshida , Zenasis Technologies, Inc., Campbell, CA
pp. 208-211
Abstraction Techniques for Functional Verification

An Efficient Finite-Domain Constraint Solver for Circuits (Abstract)

Li-C. Wang , University of California, Santa Barbara
G. Parthasarathy , University of California, Santa Barbara
M. K. Iyer , University of California, Santa Barbara
K.-T. Cheng , University of California, Santa Barbara
pp. 212-217

Automatic Abstraction and Verification of Verilog Models (Abstract)

Zaher S. Andraus , University of Michigan, Ann Arbor
Karem A. Sakallah , University of Michigan, Ann Arbor
pp. 218-223

Abstraction Refinement by Controllability and Cooperativeness Analysis (Abstract)

Freddy Y. C. Mang , Advanced Technology Group, Synopsys, Inc.
Pei-Hsin Ho , Advanced Technology Group, Synopsys, Inc.
pp. 224-229

Verifying A Gigabit Ethernet Switch Using SMV (Abstract)

Yuan Lu , Broadcom Corporation
Mike Jorda , Broadcom Corporation
pp. 230-233

A General Decomposition Strategy for Verifying Register Renaming (Abstract)

Hazem I. Shehata , University of Waterloo, Canada
Mark D. Aagaard , University of Waterloo, Canada
pp. 234-237
Memory and Network Optimization in Embedded Designs

An Integrated Hardware/Software Approach For Run-Time Scratchpad Management (Abstract)

Jose M. Mendias , DACYA/UCM, Spain
Francky Catthoor , IMEC vzw, Belgium
Poletti Francesco , University of Bologna, Italy
David Atienza , DACYA/UCM, Spain
Paul Marchal , IMEC vzw, Belgium
Luca Benini , University of Bologna, Italy
pp. 238-243

Multi-Profile Based Code Compression (Abstract)

R. Azevedo , IC/UNICAMP
G. Araujo , IC/UNICAMP
P. Centoducatte , IC/UNICAMP
E. Wanderley Netto , CEFET/RN IC/UNICAMP
pp. 244-249

An Efficient Scalable and Flexible Data Transfer Architecture for Multiprocessor SoC with Massive Distributed Memory (Abstract)

Sang-Il Han , Seoul National Univ., Seoul, Korea; TIMA Laboratory, Grenoble, France
Ahmed A. Jerraya , TIMA Laboratory, Grenoble, France
Amer Baghdadi , ENST Bretagne, Brest, France
Soo-Ik Chae , Seoul National Univ., Seoul, Korea
Marius Bonaciu , TIMA Laboratory, Grenoble, France
pp. 250-255

Operating-System Controlled Network on Chip (Abstract)

Th?odore Marescaux , IMEC vzw., Belgium
Diederik Verkest , IMEC vzw., Belgium
Vincent Nollet , IMEC vzw., Belgium
pp. 256-259

DyAD - Smart Routing for Networks-on-Chip (Abstract)

Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
Jingcao Hu , Carnegie Mellon University, Pittsburgh, PA
pp. 260-263
Special Session: The Future of Timing Closure

Timing Closure for Low-FO4 Microprocessor Design (PDF)

David S. Kung , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 265-266

Forest vs. Trees: Where's the Slack? (PDF)

Paul Rodman , CTO, ReShape, Inc.
pp. 267

Efficient Timing Closure Without Timing Driven Placement and Routing (Abstract)

Miodrag Vujkovic , University of Washington, Seattle
David Wadkins , University of Washington, Seattle
Carl Sechen , University of Washington, Seattle
Bill Swartz , InternetCAD.com, Inc., Dallas, TX
pp. 268-273
Panel: Verification, What Works and What Doesn't
Design Space Exploration and Scheduling for Embedded Software

Leakage Aware Dynamic Voltage Scaling for Real-Time Embedded Systems (Abstract)

Ravindra Jejurikar , University of California at Irvine
Rajesh Gupta , University of California at San Diego
Cristiano Pereira , University of California at San Diego
pp. 275-280

Retargetable Profiling for Rapid, Early System-Level Design Space Exploration (Abstract)

Daniel Gajski , University of California, Irvine
Andreas Gerstlauer , University of California, Irvine
Lukai Cai , University of California, Irvine
pp. 281-286

High Level Cache Simulation for Heterogeneous Multiprocessors (Abstract)

Faraydon Karim , STMicroelectronics
Donald E. Thomas , Carnegie Mellon University
Joshua J. Pieper , Carnegie Mellon University
Alain Mellan , STMicroelectronics
JoAnn M. Paul , Carnegie Mellon University
pp. 287-292
Advances in Accelerated Simulation

Communication-Efficient Hardware Acceleration for Fast Functional Simulation (Abstract)

Wooseung Yang , Korea Advanced Institute of Science and Technology
Young-Il Kim , Korea Advanced Institute of Science and Technology
Young-Su Kwon , Korea Advanced Institute of Science and Technology
Chong-Min Kyung , Korea Advanced Institute of Science and Technology
pp. 293-298

Circuit-Aware Architectural Simulation (Abstract)

Todd Austin , The University of Michigan, Ann Arbor
Trevor Mudge , The University of Michigan, Ann Arbor
Shidhartha Das , The University of Michigan, Ann Arbor
David Blaauw , The University of Michigan, Ann Arbor
Seokwoo Lee , The University of Michigan, Ann Arbor
Valeria Bertacco , The University of Michigan, Ann Arbor
pp. 305-310
Design for Manufacturability

Toward a Methodology for Manufacturability-Driven Design Rule Exploration (Abstract)

L. Capodieci , Advanced Micro Devices, Sunnyvale, California
D. Sylvester , University of Michigan at Ann Arbor
J. Yang , University of Michigan at Ann Arbor
A. B. Kahng , University of California at San Diego
P. Gupta , University of California at San Diego
pp. 311-316

Phase Correct Routing For Alternating Phase Shift Masks (Abstract)

Kevin McCullen , IBM Microelectronics Division, Essex Junction, VT
pp. 317-320

Toward a Systematic-Variation Aware Timing Methodology (Abstract)

Fook-Luen Heng , IBM T.J. Watson Research Center, Yorktown Heights, NY
Puneet Gupta , UC San Diego, CA
pp. 321-326

Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control (Abstract)

Andrew B. Kahng , University of California at San Diego
Dennis Sylvester , University of Michigan, Ann Arbor
Puneet Sharma , University of California at San Diego
Puneet Gupta , University of California at San Diego
pp. 327-330
Statistical Timing Analysis

First-Order Incremental Block-Based Statistical Timing Analysis (Abstract)

C. Visweswariah , IBM Research T. J. Watson Research Center, Yorktown Heights, NY
S. G. Walker , IBM Research T. J. Watson Research Center, Yorktown Heights, NY
S. Narayan , IBM Microelectronics, East Fishkill, NY and Burlington, VT
K. Ravindran , University of California, Berkeley, CA
K. Kalafala , IBM Microelectronics, East Fishkill, NY and Burlington, VT
pp. 331-336

Fast Statistical Timing Analysis Handling Arbitrary Delay Correlations (Abstract)

Michael Orshansky , The University of Texas at Austin
Arnab Bandyopadhyay , The University of Texas at Austin
pp. 337-342

STAC: Statistical Timing Analysis with Correlation (Abstract)

Jiayong Le , CMU, Pittsburgh, PA
Lawrence T. Pileggi , CMU, Pittsburgh, PA
Xin Li , CMU, Pittsburgh, PA
pp. 343-348
Panel: System-Level Design: Six Success Stories in Search of an Industry
New Ideas in Placement

Large-Scale Placement by Grid-Warping (Abstract)

James D. Ma , Carnegie Mellon University, Pittsburgh, Pennsylvania
Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, Pennsylvania
Suzanne M. Fowler , Intel Corp., Chandler, Arizona
Zhong Xiu , Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 351-356

Placement Feedback: A Concept and Method for Better Min-Cut Placements (Abstract)

Andrew B. Kahng , University of CA, San Diego
Sherief Reda , University of CA, San Diego
pp. 357-362

Quantum-Dot Cellular Automata (QCA) Circuit Partitioning: Problem Modeling and Solutions (Abstract)

Peter M. Kogge , University of Notre Dame, IN
Danny Z. Chen , University of Notre Dame, IN
Dominic A. Antonelli , University of Notre Dame, IN
Andrew B. Kahng , University of California, San Diego
Timothy J. Dysart , University of Notre Dame, IN
Xiaobo S. Hu , University of Notre Dame, IN
Richard C. Murphy , University of Notre Dame, IN
Michael T. Niemier , University of Notre Dame, IN
pp. 363-368
Model Order Reduction and Variational Techniques for Parasitic Analysis

Passivity-Preserving Model Reduction Via A Computationally Efficient Project-And-Balance Scheme (Abstract)

N. Wong , The University of Hong Kong
C.-K. Koh , Purdue University, West Lafayette, IN
V. Balakrishnan , Purdue University, West Lafayette, IN
pp. 369-374

A Linear Fractional Transform (LFT) Based Model For Interconnect Parametric Uncertainty (Abstract)

Janet M. Wang , University of Arizona at Tucson
Omar A. Hafiz , University of Arizona at Tucson
Jun Li , ETOP Design Technology, Sunnyvale, California
pp. 375-380

Variational Delay Metrics for Interconnect Timing Analysis (Abstract)

Sarma Vrudhula , University of Arizona, Tucson
Kanak Agarwal , University of Michigan, Ann Arbor
David Blaauw , University of Michigan, Ann Arbor
Sani Nassif , IBM Research, Austin
Frank Liu , IBM Research, Austin
Dennis Sylvester , University of Michigan, Ann Arbor
pp. 381-384

Exploiting Input Information in a Model reduction Algorithm for Massively Coupled Parasitic Networks (Abstract)

Joel R. Phillips , Cadence Design Systems, San Jose, CA
L. Miguel Silveira , Technical University of Lisbon, Portugal
pp. 385-388
Compilation Techniques for Embedded Applications

Automatic Translation of Software Binaries onto FPGAs (Abstract)

David C. Zaretsky , Northwestern University, Evanston, IL
Gaurav Mittal , Northwestern University, Evanston, IL
Xiaoyong Tang , Northwestern University, Evanston, IL
P. Banerjee , Northwestern University, Evanston, IL
pp. 389-394

Area-Efficient Instruction Set Synthesis for Reconfigurable System-on-Chip Designs (Abstract)

Philip Brisk , University of California, Los Angeles
Adam Kaplan , University of California, Los Angeles
Majid Sarrafzadeh , University of California, Los Angeles
pp. 395-400

Data Compression for Improving SPM Behavior (Abstract)

M. Kandemir , Pennsylvania State University, University Park, PA
M. J. Irwin , Pennsylvania State University, University Park, PA
O. Ozturk , Pennsylvania State University, University Park, PA
G. Chen , Syracuse University, Syracuse, NY
pp. 401-406
Special Session: Platform-Based System Design

Nomadic Platform Approach for Wireless Mobile Multimedia (PDF)

Mark Hopkins , STMicroelectronics, Inc., San Diego, CA
pp. 408

Benefits and Challenges for Platform-Based Design (Abstract)

Luca Carloni , University of California, Berkeley
Marco Sgroi , DoCoMo Euro-Labs, Munich, Germany
Alberto Sangiovanni-Vincentelli , University of California, Berkeley
Fernando De Bernardinis , University of California, Berkeley; Universit? di Pisa, Italy
pp. 409-414
Innovations in Logic Synthesis

A Recursive Paradigm To Solve Boolean Relations (Abstract)

Mike Kishinevsky , Strategic CAD Lab, Intel Corp., Hillsboro, OR
Jordi Cortadella , Univ. Polit?cnica de Catalunya, Barcelona, Spain
David Ba?eres , Univ. Polit?cnica de Catalunya, Barcelona, Spain
pp. 416-421

A Method to Decompose Multiple-Output Logic Functions (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology, Japan
Munehiro Matsuura , Kyushu Institute of Technology, Japan
pp. 428-433

Symmetry Detection for Incompletely Specified Functions (Abstract)

Jia-Hung Chen , Fu Jen Catholic University, Taipei, Taiwan
Kuo-Hua Wang , Fu Jen Catholic University, Taipei, Taiwan
pp. 434-437

Implicit Enumeration of Structural Changes in Circuit Optimization (Abstract)

Victor N. Kravets , IBM T. J. Watson Research Center, Yorktown Heights, NY
Prabhakar Kudva , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 438-441
Yield Estimation and Optimization

Parametric Yield Estimation Considering Leakage Variability (Abstract)

Anirudh Devgan , IBM Corporation, Austin, TX
Rajeev R. Rao , University of Michigan, Ann Arbor, MI
Dennis Sylvester , University of Michigan, Ann Arbor, MI
David Blaauw , University of Michigan, Ann Arbor, MI
pp. 442-447

A Methodology to Improve Timing Yield in the Presence of Process Variations (Abstract)

Janet Wang , University of Arizona
Sarma B. K. Vrudhula , University of Arizona
Sreeja Raj , University of Arizona
pp. 448-453

Novel Sizing Algorithm for Yield Improvement under Process Variation in Nanometer Technology (Abstract)

Bipul C. Paul , Purdue University, W. Lafayette, IN
Seung Hoon Choi , Intel Corporation, Hillsboro, OR
Kaushik Roy , Purdue University, W. Lafayette, IN
pp. 454-459

Statistical Timing Analysis Based on a Timing Yield Model (Abstract)

Farid N. Najm , University of Toronto, Canada
Noel Menezes , Intel Corporation, Hillsboro, Oregon
pp. 460-465
High-Level Techniques for Signal Processing

System Design for DSP Applications in Transaction Level Modeling Paradigm (Abstract)

Johnny ?berg , Royal Institute of Technology, Sweden
Axel Jantsch , Royal Institute of Technology, Sweden
Abhijit K. Deb , Royal Institute of Technology, Sweden
pp. 466-471

An Analytical Approach for Dynamic Range Estimation (Abstract)

Jianwen Zhu , University of Toronto, Canada
Bin Wu , University of Toronto, Canada
Farid N. Najm , University of Toronto, Canada
pp. 472-477

Automated Fixed-Point Data-Type Optimization Tool for Signal Processing and Communication Systems (Abstract)

Changchun Shi , University of California at Berkeley
Robert W. Brodersen , University of California at Berkeley
pp. 478-483

An Algorithm for Converting Floating-Point Computations to Fixed-Point in MATLAB based FPGA design (Abstract)

Prith Banerjee , Northwestern University, Evanston, IL
Sanghamitra Roy , Northwestern University, Evanston, IL
pp. 484-487

Synthesizing Interconnect-Efficient Low Density Parity Check Codes (Abstract)

Marghoob Mohiyuddin , The University of Texas at Austin
Wayne Wolf , Princeton University
Amit Prakash , The University of Texas at Austin
Adnan Aziz , The University of Texas at Austin
pp. 488-491
Advanced Test Solutions

On Path-Based Learning And Its Applications In Delay Test And Diagnosis (Abstract)

Li-C. Wang , UC-Santa Barbara
Magdy S. Abadir , Motorola, Inc, Austin, TX
Kwang-Ting Cheng , UC-Santa Barbara
T. M. Mak , Intel Corporation, Santa Clara, CA
pp. 492-497

Efficient On-Line Testing of FPGAs with Provable Diagnosabilities (Abstract)

Shantanu Dutt , University of Illinois at Chicago
Vinay Verma , Xilinx Inc., San Jose, CA
Vishal Suthar , University of Illinois at Chicago
pp. 498-503

On Test Generation for Transition Faults with Minimized Peak Power Dissipation (Abstract)

Irith Pomeranz , Purdue University, West Lafayette, IN
Sudhakar M. Reddy , Univ. of Iowa, Iowa City
Wei Li , Univ. of Iowa, Iowa City
pp. 504-509

A New State Assignment Technique for Testing and Low Power (Abstract)

Seiyang Yang , Pusan University, Korea
Maciej Ciesielski , University of Massachusetts
Sangwook Cho , Hanyang University at Ansan, Korea
Sungju Park , Hanyang University at Ansan, Korea
pp. 510-513

Automatic Generation of Breakpoint Hardware for Silicon Debug (Abstract)

Bart Vermeulen , Philips Research Laboratories Eindhoven, The Netherlands
Sandeep K. Goel , Philips Research Laboratories, Eindhoven, The Netherlands
Mohammad Z. Urfianto , Royal Institute of Technology, Kista, Sweden
pp. 514-517
Advances in Boolean Analysis Techniques

AMUSE: A Minimally-Unsatisfiable Subformula Extractor (Abstract)

Karem A. Sakallah , University of Michigan, Ann Arbor, MI
Maher N. Mneimneh , University of Michigan, Ann Arbor, MI
Igor L. Markov , University of Michigan, Ann Arbor, MI
Yoonna Oh , University of Michigan, Ann Arbor, MI
Zaher S. Andraus , University of Michigan, Ann Arbor, MI
pp. 518-523

A SAT-Based Algorithm for Reparameterization in Symbolic Simulation (Abstract)

Pankaj Chauhan , Carnegie Mellon University, Pittsburgh, PA
Edmund M. Clarke , Carnegie Mellon University, Pittsburgh, PA
Daniel Kroening , Carnegie Mellon University, Pittsburgh, PA
pp. 524-529

Exploiting Structure in Symmetry Detection for CNF (Abstract)

Igor L. Markov , The University of Michigan
Karem A. Sakallah , The University of Michigan
Paul T. Darga , The University of Michigan
Mark H. Liffiton , The University of Michigan
pp. 530-534

Refining the SAT Decision Ordering for Bounded Model Checking (Abstract)

Gary D. Hachtel , University of Colorado at Boulder
HoonSang Jin , University of Colorado at Boulder
Chao Wang , University of Colorado at Boulder
Fabio Somenzi , University of Colorado at Boulder
pp. 535-538

Efficient Equivalence Checking with Partitions and Hierarchical Cut-Points (Abstract)

Demosthenes Anastasakis , Synopsys, Inc., Hillsboro, OR
Slawomir Pilarski , University of Washington, Tacoma
Lisa McIlwain , Synopsys, Inc., Hillsboro, OR
pp. 539-542
Panel: Were the Good Old Days all that Good? EDA Then and Now
Power Optimization for Real-Time and Media-Rich Embedded Systems

Off-Chip Latency-Driven Dynamic Voltage and Frequency Scaling for an MPEG Decoding (Abstract)

Massoud Pedram , Univ. of Southern California, Los Angeles
Kihwan Choi , Univ. of Southern California, Los Angeles
Ramakrishna Soma , Univ. of Southern California, Los Angeles
pp. 544-549

Energy-Aware Deterministic Fault Tolerance in Distributed Real-Time Embedded Systems (Abstract)

Krishnendu Chakrabarty , Duke University, Durham, NC
Robert Dick , Northwestern University, Evanston, IL
Ying Zhang , Duke University, Durham, NC
pp. 550-555

Proxy-based Task Partitioning of Watermarking Algorithms for Reducing Energy Consumption in Mobile Devices (Abstract)

Nikil Dutt , University of California at Irvine
Sumit Gupta , University of California at Irvine
Rajesh Gupta , University of California at San Diego
Alexandru Nicolau , University of California at Irvine
Arun Kejariwal , University of California at Irvine
pp. 556-561

Adaptive Data Partitioning for Ambient Multimedia (Abstract)

Xiaoping Hu , Carnegie Mellon University, Pittsburgh, PA
Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
pp. 562-565

Energy Characterization of Filesystems for Diskless Embedded Systems (Abstract)

Rabi N. Mahapatra , Texas A & M University
Siddharth Choudhuri , University of California, Irvine
pp. 566-569
Latency Tolerance and Asynchronous Design

A Method for Correcting the Functionality of a Wire-Pipelined Circuit (Abstract)

Vidyasagar Nookala , University of Minnesota, Minneapolis
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
pp. 570-575

A New Approach to Latency Insensitive Design (Abstract)

Luca Macchiarulo , Politecnico di Torino/CERCOM, Italy
Mario R. Casu , Politecnico di Torino/CERCOM, Italy
pp. 576-581

Pre-layout Wire Length and Congestion Estimation (Abstract)

Qinghua Liu , Univ. of California, Santa Barbara
Malgorzata Marek-Sadowska , Univ. of California, Santa Barbara
pp. 582-587

The Best of Both Worlds: The Efficient Asynchronous Implementation of Synchronous Specifications (Abstract)

Alberto Sangiovanni-Vincentelli , UC Berkeley, Berkeley, CA
Kelvin Lwin , Cadence Design Systems, San Jose, CA
Alex Kondratyev , Cadence Berkeley Labs, Berkeley, CA
Abhijit Davare , UC Berkeley, Berkeley, CA
pp. 588-591

Fast Hazard Detection in Combinational Circuits (Abstract)

Cheoljoo Jeong , Columbia University, New York, NY
Steven M. Nowick , Columbia University, New York, NY
pp. 592-595
New Technologies in System Design

In Designing Asynchronous Circuits it is Critical to Ensure that Circuits Nanotechnologies (Abstract)

Stephen Bijansky , The University of Texas at Austin
Margarida Jacome , The University of Texas at Austin
Chen He , The University of Texas at Austin
Gustavo de Veciana , The University of Texas at Austin
pp. 596-601

Architecture-Level Synthesis for Automatic Interconnect Pipelining (Abstract)

Zhiru Zhang , University of California, Los Angeles
Yiping Fan , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 602-607

Divide-and-Concatenate: An Architecture Level Optimization Technique for Universal Hash Functions (Abstract)

Ramesh Karri , Polytechnic University, Brooklyn, NY
Bo Yang , Polytechnic University, Brooklyn, NY
David A. McGrew , Cisco Systems, Inc., San Jose, CA
pp. 614-617

Performance Analysis of Different Arbitration Algorithms of the AMBA AHB Bus (Abstract)

Massimo Conti , Universit? Politecnica delle Marche, Italy
Simone Orcioni , Universit? Politecnica delle Marche, Italy
Giovanni B. Vece , Universit? Politecnica delle Marche, Italy
Claudio Turchetti , Universit? Politecnica delle Marche, Italy
Marco Caldari , Universit? Politecnica delle Marche, Italy
pp. 618-621
Special Session: BioMEMS

Design Tools for BioMEMS (Abstract)

Ken Greiner , Coventor, Inc., Cambridge, Massachusetts
Tom Korsmeyer , Coventor, Inc., Cambridge, Massachusetts
Jun Zeng , Coventor, Inc., Cambridge, Massachusetts
pp. 622-627

CAD Challenges in BioMEMS Design (Abstract)

Jacob White , Massachusetts Institute of Technology, Cambridge, MA
pp. 629-632
Panel: Will Moore's Law Rule in the Land of Analog?
Floorplanning

Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design (Abstract)

Mongkol Ekpanyapong , Georgia Institute of Technology, Atlanta, GA
Hsien-Hsin S. Lee , Georgia Institute of Technology, Atlanta, GA
Jacob R. Minz , Georgia Institute of Technology, Atlanta, GA
Thaisiri Watewai , University of California, Berkeley, CA
Sung Kyu Lim , Georgia Institute of Technology, Atlanta, GA
pp. 634-639

Floorplanning Optimization with Trajectory Piecewise-Linear Model for Pipelined Interconnects (Abstract)

Lucanus J. Simonson , University of California, Los Angeles
Lei He , University of California, Los Angeles
Weiping Liao , University of California, Los Angeles
Changbo Long , University of California, Los Angeles
pp. 640-645

A Packing Algorithm for Non-Manhattan Hexagon/Triangle Placement Design by Using an Adaptive O-Tree Representation (Abstract)

Tan Yan , Science and Technology of China
Bo Yang , Science and Technology of China
Juebang Yu , Science and Technology of China
Chunhui Li , Cadence, San Jose, CA
Jing Li , Science and Technology of China
pp. 646-651
Issues in Timing Analysis

Worst-Case Circuit Delay Taking into Account Power Supply Variations (Abstract)

Rubil Ahmadi , University of Toronto, Canada
Dionysios Kouroussis , University of Toronto, Canada
Farid N. Najm , University of Toronto, Canada
pp. 652-657

Statistical Gate Delay Model Considering Multiple Input Switching (Abstract)

Aseem Agarwal , University of Michigan, Ann Arbor, MI
Florentin Dartu , Intel Corporation, Hillsboro, OR
David Blaauw , University of Michigan, Ann Arbor, MI
pp. 658-663

Static Timing Analysis using Backward Signal Propagation (Abstract)

David Blaauw , University of Michigan, Ann Arbor, MI
Vladimir Zolotov , Motorola Inc. Austin, TX
Dongwoo Lee , University of Michigan, Ann Arbor, MI
pp. 664-669
Special Session: ISSCC Highlights

Design and Implementation of the POWER5™ Microprocessor (Abstract)

Larry Powell , Kalla, Joseph McGill, Steve Dodson
Joseph McGill , IBM Systems Group, Poughkeepsie, NY
Phillip Restle , IBM Research, Yorktown Heights, NY
Donald Plass , IBM Systems Group, Poughkeepsie, NY
James Dawson , IBM Systems Group, Poughkeepsie, NY
Mark Sweet , Kalla, Joseph McGill, Steve Dodson
James Wagoner , Kalla, Joseph McGill, Steve Dodson
Joachim Clabes , Kalla, Joseph McGill, Steve Dodson
Gary Gorman , Kalla, Joseph McGill, Steve Dodson
Steve Runyon , Kalla, Joseph McGill, Steve Dodson
Mike Lee , Kalla, Joseph McGill, Steve Dodson
Balaram Sinharoy , IBM Systems Group, Poughkeepsie, NY
Joshua Friedrich , Kalla, Joseph McGill, Steve Dodson
Michael Goulet , Kalla, Joseph McGill, Steve Dodson
Michael Floyd , Kalla, Joseph McGill, Steve Dodson
Steve Dodson , IBM Systems Group, Poughkeepsie, NY
Ronald Kalla , IBM Systems Group, Poughkeepsie, NY
Jack DiLullo , Kalla, Joseph McGill, Steve Dodson
Paul Muench , IBM Systems Group, Poughkeepsie, NY
Nicole Schwartz , Kalla, Joseph McGill, Steve Dodson
Sam Chu , Kalla, Joseph McGill, Steve Dodson
pp. 670-672

A Dual-Core 64b UltraSPARC Microprocessor for Dense Server Applications (Abstract)

Bruce Petrick , Sun Microsystems, Inc., Sunnyvale, CA
Jinuk Luke Shin , Sun Microsystems, Inc., Sunnyvale, CA
Ana Sonia Leon , Sun Microsystems, Inc., Sunnyvale, CA
Jeffrey Su , Sun Microsystems, Inc., Sunnyvale, CA
Toshinari Takayanagi , Sun Microsystems, Inc., Sunnyvale, CA
pp. 673-677

Low Voltage Swing Logic Circuits for a Pentium? 4 Processor Integer Core (Abstract)

Anant P. Singh , Intel Corporation, Hillsboro, Oregon
Sapumal Wijeratne , Intel Corporation, Hillsboro, Oregon
Micah Barany , Intel Corporation, Hillsboro, Oregon
Kurt Kreitzer , Intel Corporation, Hillsboro, Oregon
George Geannopoulos , Intel Corporation, Hillsboro, Oregon
Daniel J. Deleganes , Intel Corporation, Hillsboro, Oregon
pp. 678-680
Special Session: Multiprocessor SoC MPSoC Solutions/Nightmare

The Future of Multiprocessor Systems-on-Chips (Abstract)

Wayne Wolf , Princeton University, Princeton NJ
pp. 681-685

Flexible Architectures for Engineering Successful SOCs (Abstract)

Steve Leibson , Tensilica, Inc., San Jose, CA
Chris Rowen , Tensilica, Inc., San Jose, CA
pp. 692-697
Panel: Is Statistical Timing Statistically Significant?
Timing Issues in Placement

Modeling Repeaters Explicitly Within Analytical Placement (Abstract)

Prashant Saxena , Intel Labs (CAD Research), Hillsboro, OR
Bill Halpin , Synplicity, Inc., Sunnyvale, CA
pp. 699-704

Quadratic Placement Using an Improved Timing Model (Abstract)

Frank M. Johannes , Technical University of Munich
Bernd Obermeier , Technical University of Munich
pp. 705-710

An Approach to Placement-Coupled Logic Replication (Abstract)

John Lillis , University of Illinois at Chicago
Milos Hrkic , University of Illinois at Chicago
Giancarlo Beraudo , University of Illinois at Chicago
pp. 711-716
Design Methodologies for ASIPs

A Novel Approach for Flexible and Consistent ADL-driven ASIP Design (Abstract)

Jianjiang Ceng , Institute for Integrated Systems, Aachen, Germany
Achim Nohl , CoWare, Inc., Aachen, Germany
Manuel Hohenauer , Institute for Integrated Systems, Aachen, Germany
Gunnar Braun , CoWare, Inc., Aachen, Germany
Weihua Sheng , Institute for Integrated Systems, Aachen, Germany
Rainer Leupers , Institute for Integrated Systems, Aachen, Germany
Heinrich Meyr , Institute for Integrated Systems, Aachen, Germany
Hanno Scharw?chter , Institute for Integrated Systems, Aachen, Germany
pp. 717-722

Characterizing Embedded Applications for Instruction-Set Extensible Processors (Abstract)

Tulika Mitra , National University of Singapore
Pan Yu , National University of Singapore
pp. 723-728

Introduction of Local Memory Elements in Instruction Set Extensions (Abstract)

Kubilay Atasu , Swiss Federal Institute of Technology, Lausanne, Switzerland
Vinay Choudhary , Swiss Federal Institute of Technology, Lausanne, Switzerland
Paolo Ienne , Swiss Federal Institute of Technology, Lausanne, Switzerland
Nikil Dutt , University of California, Irvine
Laura Pozzi , Swiss Federal Institute of Technology, Lausanne, Switzerland
Partha Biswas , University of California, Irvine
pp. 729-734
FPGA-Based Systems

FPGA Power Reduction Using Configurable Dual-Vdd (Abstract)

Lei He , University of California, Los Angeles
Fei Li , University of California, Los Angeles
Yan Lin , University of California, Los Angeles
pp. 735-740

Multi-Resource Aware Partitioning Algorithms for FPGAs with Heterogeneous Resources (Abstract)

Abhishek Ranjan , HierDesign Inc
Navaratnasothie Selvakkumaran , University of Minnesota
George Karypis , University of Minnesota
Salil Raje , HierDesign Inc
pp. 741-746
Special Session: Security as a New Dimension in Embedded System Design

Security as a New Dimension in Embedded System Design (Abstract)

Ruby Lee , Princeton University, Princeton, NJ
Gary McGraw , Cigital, Dulles, VA
Paul Kocher , Cryptography Research, San Francisco, CA
Srivaths Ravi , NEC Laboratories America, Princeton, NJ
Anand Raghunathan , NEC Laboratories America, Princeton, NJ
pp. 753-760
Leakage Power Optimization

Tradeoffs between Gate Oxide Leakage and Delay for Dual T{ox} Circuits (Abstract)

Anup Kumar Sultania , University of Minnesota, Minneapolis, MN
Dennis Sylvester , University of Michigan, Ann Arbor, MI
Sachin S. Sapatnekar , University of Minnesota, Minneapolis, MN
pp. 761-766

Statistical Optimization of Leakage Power Considering Process Variations using Dual-Vth and Sizing (Abstract)

Ashish Srivastava , University of Michigan, Ann Arbor, MI
David Blaauw , University of Michigan, Ann Arbor, MI
Dennis Sylvester , University of Michigan, Ann Arbor, MI
pp. 773-778

Leakage-and Crosstalk-Aware Bus Encoding for Total Power Reduction (Abstract)

Harmander S. Deogun , University of Michigan - Ann Arbor
David Blaauw , University of Michigan - Ann Arbor
Rajeev R. Rao , University of Michigan - Ann Arbor
Dennis Sylvester , University of Michigan - Ann Arbor
pp. 779-782

Power Minimization using Simultaneous Gate Sizing, Dual-Vdd and Dual-Vth Assignment (Abstract)

Ashish Srivastava , University of Michigan, Ann Arbor, MI
David Blaauw , University of Michigan, Ann Arbor, MI
Dennis Sylvester , University of Michigan, Ann Arbor, MI
pp. 783-787
Interconnect Extraction

Sparse Transformations and Preconditioners for Hierarchical 3-D Capacitance Extraction with Multiple Dielectrics (Abstract)

Vivek Sarin , Texas A&M University, College Station
Shu Yan , Texas A&M University, College Station
Weiping Shi , Texas A&M University, College Station
pp. 788-793

A Fast Parasitic Extractor Based on Low-Rank Multilevel Matrix Compression for Conductor and Dielectric Modeling in Microelectronics and MEMS (Abstract)

Dipanjan Gope , University of Washington, Seattle, WA
Swagato Chakraborty , University of Washington, Seattle, WA
Vikram Jandhyala , University of Washington, Seattle, WA
pp. 794-799

CHIME: Coupled Hierarchical Inductance Model Evaluation (Abstract)

Satrajit Gupta , Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
pp. 800-805

Large-Scale Full-Wave Simulation (Abstract)

David E. Long , Integrand Software, Inc.
Sharad Kapur , Integrand Software, Inc.
pp. 806-809

Closed-Form Expressions of Distributed RLC Interconnects for Analysis of On-Chip Inductance Effects (Abstract)

Yuichi Tanji , Kagawa University, Takamatsu, Japan
Hideki Asai , Shizuoka University, Hamamatsu, Japan
pp. 810-813
New Frontiers in Logic Synthesis

Re-Synthesis for Delay Variation Tolerance (Abstract)

Shih-Chieh Chang , National Tsing Hua University, Hsinchu, Taiwan
Kai-Chiang Wu , National Tsing Hua University, Hsinchu, Taiwan
Cheng-Tao Hsieh , National Tsing Hua University, Hsinchu, Taiwan
pp. 814-819

Post-Layout Logic Optimization of Domino Circuits (Abstract)

Aiqun Cao , Purdue University, West Lafayette, IN
Cheng-Kok Koh , Purdue University, West Lafayette, IN
pp. 820-825

Multiple Constant Multiplication By Time-Multiplexed Mapping of Addition Chains (Abstract)

Markus P?schel , Carnegie Mellon University
James C. Hoe , Carnegie Mellon University
Peter Tummeltshammer , University of Technology, Vienna, Austria
pp. 826-829

A New Heuristic Algorithm for Reversible Logic Synthesis (Abstract)

Pawel Kerntopf , Warsaw University of Technology, Poland
pp. 834-837

Quantum Logic Synthesis by Symbolic Reachability Analysis (Abstract)

Marek Perkowski , Portland State University, Portland, Oregon
Xiaoyu Song , Portland State University, Portland, Oregon
William N. N. Hung , Intel Corporation, Hillsboro, Oregon
Jin Yang , Intel Corporation, Hillsboro, Oregon
Guowu Yang , Portland State University, Portland, Oregon
pp. 838-841
Numerical Techniques for Simulation

A Frequency Relaxation Approach for Analog/RF System-Level Simulation (Abstract)

Peng Li , Carnegie Mellon University, Pittsburgh, PA
Yang Xu , Carnegie Mellon University, Pittsburgh, PA
Xin Li , Carnegie Mellon University, Pittsburgh, PA
Padmini Gopalakrishnan , Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
pp. 842-847

Robust, Stable Time.Domain Methods for Solving MPDEs of Fast/Slow Systems (Abstract)

Todd S. Coffey , Sandia National Laboratories, Albuquerque, NM
Ting Mei , University of Minnesota, Minneapolis
Jaijeet Roychowdhury , University of Minnesota, Minneapolis
David M. Day , Sandia National Laboratories, Albuquerque, NM
Scott A. Hutchinson , Sandia National Laboratories, Albuquerque, NM
pp. 848-853

High-Level Simulation of Substrate Noise in High-Ohmic Substrates with Interconnect and Supply Effects (Abstract)

P. Dobrovolny , IMEC, Leuven, Belgium
H. De Man , IMEC, Leuven, Belgium; ESAT, K.U. Leuven, Belgium
G. Van der Plas , IMEC, Leuven, Belgium
G. Vandersteen , IMEC, Leuven, Belgium
P. Wambacq , IMEC, Leuven, Belgium
S. Donnay , IMEC, Leuven, Belgium
M. Badaroglu , IMEC, Leuven, Belgium
G. Gielen , ESAT, K.U. Leuven, Belgium
pp. 854-859

Hierarchical Approach to Exact Symbolic Analysis of Large Analog Circuits (Abstract)

Sheldon X.-D. Tan , University of California, Riverside
Zhenyu Qi , University of California, Riverside
Weikun Guo , University of California, Riverside
pp. 860-863

An Essentially Non-Oscillatory (ENO) High-Order Accurate Adaptive Table Model for Device Modeling (Abstract)

Bruce McGaughy , Cadence Design Systems, Inc.
Baolin Yang , Cadence Design Systems, Inc.
pp. 864-867
Energy and Thermal-Aware Design

Theoretical and Practical Limits of Dynamic Voltage Scaling (Abstract)

Dennis Sylvester , University of Michigan, Ann Arbor, MI
Bo Zhai , University of Michigan, Ann Arbor, MI
David Blaauw , University of Michigan, Ann Arbor, MI
Krisztian Flautner , ARM Ltd., Cambridge, UK
pp. 868-873

Enabling Energy Efficiency in Via-Patterned Gate Array Devices (Abstract)

Herman Schmit , Tabula, Inc., Mountain View, CA
R. Reed Taylor , Carnegie Mellon University, Pittsburgh, PA
pp. 874-877

Compact Thermal Modeling for Temperature-Aware Design (Abstract)

Shougata Ghosh , University of Virginia, Charlottesville
Sivakumar Velusamy , University of Virginia, Charlottesville
Karthik Sankaranarayanan , University of Virginia, Charlottesville
Mircea R. Stan , University of Virginia, Charlottesville
Kevin Skadron , University of Virginia, Charlottesville
Wei Huang , University of Virginia, Charlottesville
pp. 878-883

Simultaneous Optimization of Supply and Threshold Voltages for Low-Power and High-Performance Circuits in the Leakage Dominant Era (Abstract)

Anirban Basu , University of California, Santa Barbara, CA
Sheng-Chih Lin , University of California, Santa Barbara, CA
Vineet Wason , University of California, Santa Barbara, CA
Kaustav Banerjee , University of California, Santa Barbara, CA
Amit Mehrotra , Berkeley Design Automation Inc., Santa Clara, CA
pp. 884-887
Noise-Tolerant Design and Analysis Techniques

Noise Characterization of Static CMOS Gates (Abstract)

Timothy Lehner , IBM Corporation, Hopewell Junction, New York
Rouwaida Kanj , University of Illinois at Urbana-Champaign
Elyse Rosenbaum , University of Illinois at Urbana-Champaign
Bhavna Agrawal , IBM Corporation, Hopewell Junction, New York
pp. 888-893

A Scalable Soft Spot Analysis Methodology for Compound Noise Effects in Nano-meter Circuits (Abstract)

Chong Zhao , Univ. of California, San Diego
Sujit Dey , Univ. of California, San Diego
Xiaoliang Bai , Univ. of California, San Diego
pp. 894-899

A Novel Technique to Improve Noise Immunity of CMOS Dynamic Logic Circuits (Abstract)

Pinaki Mazumder , University of Michigan, Ann Arbor
Li Ding , University of Michigan, Ann Arbor
pp. 900-903

Statistical Timing Analysis in Sequential Circuit for On-Chip Global Interconnect Pipelining (Abstract)

Yuhen Hu , University of Wisconsin, Madison, WI
Charlie Chungping Chen , National Taiwan University, Taipei
Lizheng Zhang , University of Wisconsin, Madison, WI
pp. 904-907
New Tools and Methods for Future Embedded SoC

Debugging HW/SW Interface for MPSoC: Video Encoder System Design Case Study (Abstract)

Ahmed A. Jerraya , TIMA Laboratory, Grenoble, France
Arif Sasongko , TIMA Laboratory, Grenoble, France
Mohamed-Wassim Youssef , TIMA Laboratory, Grenoble, France
Yanick Paviot , TIMA Laboratory, Grenoble, France
Sungjoo Yoo , TIMA Laboratory, Grenoble, France
pp. 908-913

SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs (Abstract)

Giovanni De Micheli , Stanford University, CA
Srinivasan Murali , Stanford University, CA
pp. 914-919

FITS: Framework-Based Instruction-Set Tuning Synthesis for Embedded Application Specific Processors (Abstract)

Gary Tyson , Florida State University, Tallahassee
Trevor Mudge , The University of Michigan, Ann Arbor
Allen Cheng , The University of Michigan, Ann Arbor
pp. 920-923

Mapping a Domain Specific Language to a Platform FPGA (Abstract)

Graham Schelle , University of Colorado, Boulder, Co
Gordon Brebner , Xilinx Inc, San Jose, Ca
Chidamber Kulkarni , Xilinx Inc, San Jose, Ca
pp. 924-927
New Scan-Based Test Techniques

Scalable Selector Architecture for X-Tolerant Deterministic BIST (Abstract)

Peter Wohl , Synopsys Inc., Williston, VT
John A. Waicukauski , Synopsys Inc., Tualatin, OR
Sanjay Patel , Synopsys Inc., Beaverton, OR
pp. 934-939

Scan-BIST Based on Transition Probabilities (Abstract)

Irith Pomeranz , Purdue University, W. Lafayette, IN
pp. 940-943

Combining Dictionary Coding And LFSR Reseeding For Test Data Compression (Abstract)

Bapiraju Vinnakota , University of Minnesota, MN
Xiaoyun Sun , University of Minnesota, MN
Larry Kinney , University of Minnesota, MN
pp. 944-947
CAD for Reconfigurable Computing

Virtual Memory Window for Application-Specific Reconfigurable Coprocessors (Abstract)

Laura Pozzi , Swiss Federal Institute of Technology Lausanne, Switzerland
Paolo Ienne , Swiss Federal Institute of Technology Lausanne, Switzerland
Miljan Vuletic , Swiss Federal Institute of Technology Lausanne, Switzerland
pp. 948-953

Dynamic FPGA Routing for Just-in-Time FPGA Compilation (Abstract)

Frank Vahid , University of California, Riverside
Sheldon X.-D. Tan , University of California, Riverside
Roman Lysecky , University of California, Riverside
pp. 954-959

An Efficient Algorithm for Finding Empty Space for Online FPGA Placement (Abstract)

Manish Handa , University of Cincinnati, OH
Ranga Vemuri , University of Cincinnati, OH
pp. 960-965
90 ms
(Ver )