The Community for Technology Leaders
Design Automation Conference (2003)
Anaheim, CA
June 2, 2003 to June 6, 2003
ISBN: 1-58113-688-9
TABLE OF CONTENTS

High-level formal verification of next-generation microprocessors (PDF)

T. Schubert , DPG CPU Design Validation, Intel Corp., Hillsboro, OR, USA
pp. 1-6

Verification strategy for integration 3G baseband SoC (PDF)

Y. Mathys , Motorola Inc., Geneva, Switzerland
A. Chatelain , Motorola Inc., Geneva, Switzerland
pp. 7-10

Reshaping EDA for power (PDF)

J. Rabaey , University of California at Berkeley
pp. 15

A cost-driven lithographic correction methodology based on off-the-shelf sizing tools (PDF)

P. Gupta , ECE Dept., Univ. of California, San Diego, CA, USA
A.B. Kahng , ECE Dept., Univ. of California, San Diego, CA, USA
pp. 16-21

Improved global routing through congestion estimation (PDF)

R.T. Hadsell , SUNY, Binghamton, NY, USA
P.H. Madden , SUNY, Binghamton, NY, USA
pp. 28-31

Microarchitecture evaluation with physical planning (PDF)

J. Cong , Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
A. Jagannathan , Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
G. Reinman , Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
M. Romesis , Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
pp. 32-35

A fully programmable memory management system optimizing queue handling at multi gigabit rates (PDF)

G. Kornaros , Ellemedia Technol., Athens, Greece
I. Papaefstathiou , Ellemedia Technol., Athens, Greece
A. Nikologiannis , Ellemedia Technol., Athens, Greece
N. Zervos , Ellemedia Technol., Athens, Greece
pp. 54-59

Design flow for HW/SW acceleration transparency in the thumbpod secure embedded system (PDF)

D. Hwang , Electr. Eng. Dept., UCLA, Los Angeles, CA, USA
Bo-Cheng Lai , Electr. Eng. Dept., UCLA, Los Angeles, CA, USA
P. Schaumont , Electr. Eng. Dept., UCLA, Los Angeles, CA, USA
K. Sakiyama , Electr. Eng. Dept., UCLA, Los Angeles, CA, USA
Yi Fan , Electr. Eng. Dept., UCLA, Los Angeles, CA, USA
Shenglin Yang , Electr. Eng. Dept., UCLA, Los Angeles, CA, USA
A. Hodjat , Electr. Eng. Dept., UCLA, Los Angeles, CA, USA
I. Verbauwhede , Electr. Eng. Dept., UCLA, Los Angeles, CA, USA
pp. 60-65

Design techniques for sensor appliances: foundations and light compass case study (PDF)

J.L. Wong , Univ. of California, Los Angeles, CA, USA
S. Megerian , Univ. of California, Los Angeles, CA, USA
M. Potkonjank , Univ. of California, Los Angeles, CA, USA
pp. 66-71

RF front end application and technology trends (PDF)

P.W. Hooijmans , Philips Res. Labs., Eindhoven, Netherlands
pp. 73-78

4G terminals: how are we going to design them? (PDF)

J. Craninckx , IMEC, Leuven, Belgium
S. Donnay , IMEC, Leuven, Belgium
pp. 79-84

COT - customer owned trouble (PDF)

B. Dahlberg , Reshape Inc.
pp. 91-92
SESSION 3: Design for Manufacturability and Global Routing

A Cost-Driven Lithographic Correction Methodology Based on Off-the-Shelf Sizing Tools (Abstract)

P. Gupta , University of California at San Diego
A. B. Kahng , University of California at San Diego
D. Sylvester , University of Michigan at Ann Arbor
J. Yang , University of Michigan at Ann Arbor
pp. 16

A static pattern-independent technique for power grid voltage integrity verification (PDF)

D. Kouroussis , ECE Dept., Univ. of Toronto, Ont., Canada
F.N. Najm , ECE Dept., Univ. of Toronto, Ont., Canada
pp. 99-104
SESSION 3: Design for Manufacturability and Global Routing

Improved Global Routing through Congestion Estimation (Abstract)

Raia T. Hadsell , SUNY Binghamton CSD, Binghamton NY
Patrick H. Madden , SUNY Binghamton CSD, Binghamton NY
pp. 28

Microarchitecture Evaluation With Physical Planning (Abstract)

Jason Cong , University of California, Los Angeles
Ashok Jagannathan , University of California, Los Angeles
Glenn Reinman , University of California, Los Angeles
Michail Romesis , University of California, Los Angeles
pp. 32
SESSION 4: Design Analysis Techniques

Energy-Aware Design Techniques for Differential Power Analysis Protection (Abstract)

Luca Benini , Univ. di Bologna, Italy
Alberto Macii , Politecnico di Torino, Italy
Enrico Macii , Politecnico di Torino, Italy
Elvira Omerbegovic , BullDAST s.r.l., Torino, Italy
Massimo Poncino , Univ. di Verona, Italy
Fabrizio Pro , BullDAST s.r.l., Torino, Italy
pp. 36

A Timing-Accurate Modeling and Simulation Environment for Networked Embedded Systems (Abstract)

Franco Fummi , Universit? di Verona, Italy
Paolo Gallo , Telecom Italia Lab, Torino, Italy
Stefano Martini , Universit? di Verona, Italy
Giovanni Perbellini , Universit? di Verona, Italy
Massimo Poncino , Universit? di Verona, Italy
Fabio Ricciato , Telecom Italia Lab, Torino, Italy
pp. 42

Application of Design Patterns for Hardware Design (Abstract)

Robertas Damasevicius , Kaunas University of Technology
Giedrius Majauskas , Kaunas University of Technology
Vytautas Stuikys , Kaunas University of Technology
pp. 48
SESSION 5: Embedded Hardware Design Case Studies

A Fully-Programmable Memory Management System Optimizing Queue Handling at Multi Gigabit Rates (Abstract)

G. Kornaros , Ellemedia Technologies, Athens, Greece
I. Papaefstathiou , Ellemedia Technologies, Athens, Greece
A. Nikologiannis , Ellemedia Technologies, Athens, Greece
N. Zervos , Ellemedia Technologies, Athens, Greece
pp. 54

Design Flow for HW / SW Acceleration Transparency in the ThumbPod Secure Embedded System (Abstract)

David Hwang , UCLA Electrical Engineering Department
Bo-Cheng Lai , UCLA Electrical Engineering Department
Patrick Schaumont , UCLA Electrical Engineering Department
Kazuo Sakiyama , UCLA Electrical Engineering Department
Yi Fan , UCLA Electrical Engineering Department
Shenglin Yang , UCLA Electrical Engineering Department
Alireza Hodjat , UCLA Electrical Engineering Department
Ingrid Verbauwhede , UCLA Electrical Engineering Department
pp. 60

Design Techniques for Sensor Appliances: Foundations and Light Compass Case Study (Abstract)

Jennifer L. Wong , University of California, Los Angeles
Seapahn Megerian , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 66
SESSION 6: Special Session - Emerging Design and Tool Challenges in RF and Wireless Applications

RF Front End Application and Technology Trends (Abstract)

Pieter W. Hooijmans , Philips Research Laboratories, The Netherlands
pp. 73

4G Terminals: How are We Going to Design Them? (Abstract)

Jan Craninckx , IMEC, Leuven, Belgium
St?phane Donnay , IMEC, Leuven, Belgium
pp. 79

New Techniques for Non-Linear Behavioral Modeling of Microwave/RF ICs from Simulation and Nonlinear Microwave Measurements (Abstract)

David E. Root , Agilent Technologies, Santa Rosa, CA
John Wood , Agilent Technologies, Santa Rosa, CA
Nick Tufillaro , Agilent Laboratories, Palo Alt, CA
pp. 85
SESSION 7: Panel - COT-Customer Owned Trouble
SESSION 8: Power Grid Analysis and Optimization

Random Walks in a Supply Network (Abstract)

Haifeng Qian , University of Minnesota, Minneapolis
Sani R. Nassif , IBM Austin Research Labs, Austin, TX
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
pp. 93

A Static Pattern-Independent Technique for Power Grid Voltage Integrity Verification (Abstract)

Dionysios Kouroussis , University of Toronto, Ontario, Canada
Farid N. Najm , University of Toronto, Ontario, Canada
pp. 99
SESSION 8: Power Grid Analysis and Optimization

Power Grid Reduction Based on Algebraic Multigrid Principles (Abstract)

Haihua Su , IBM Austin Research Lab, Austin, TX
Emrah Acar , IBM Austin Research Lab, Austin, TX
Sani R. Nassif , IBM Austin Research Lab, Austin, TX
pp. 109

On-chip Power Supply Network Optimization using Multigrid-based Technique (Abstract)

Kai Wang , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 113

Timing optimization of FPGA placements by logic replication (PDF)

G. Beraudo , ECE Dept., Univ. of Illinois, Chicago, IL, USA
pp. 196-201
SESSION 9: Low-Power Embedded System Design

Optimal Voltage Allocation Techniques for Dynamically Variable Voltage Processors (Abstract)

Woo-Cheol Kwon , Samsung Electronics Co., Ltd., Kyounggi-Do, Korea
Taewhan Kim , Korea Advanced Institute of Science & Technology, Korea
pp. 125

Multilevel global placement with retiming (PDF)

J. Cong , Dept. of Comput. Sci., Univ. of California, Los Angeles, CA, USA
Xin Yuan , Dept. of Comput. Sci., Univ. of California, Los Angeles, CA, USA
pp. 208-213
SESSION 9: Low-Power Embedded System Design

Xtream-Fit: An Energy-Delay Efficient Data Memory Subsystem for Embedded Media Processing (Abstract)

Anand Ramachandran , The University of Texas at Austin
Margarida F. Jacome , The University of Texas at Austin
pp. 137
SESSION 10: Cyclic and Non-Cyclic Combinational Circuit Synthesis

A New Enhanced Constructive Decomposition and Mapping Algorithm (Abstract)

Alan Mishchenko , University of California, Berkeley
Xinning Wang , Intel Corporation, Hillsboro, OR
Timothy Kam , Intel Corporation, Hillsboro, OR
pp. 143

Realizable RLCK circuit crunching (PDF)

C.S. Amin , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
M.H. Chowdhury , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Y.I. Ismail , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 226-231
SESSION 10: Cyclic and Non-Cyclic Combinational Circuit Synthesis

Generalized Cofactoring for Logic Function Evaluation (Abstract)

Yunjian Jiang , University of California, Berkeley
Slobodan Matic , University of California, Berkeley
Robert K. Brayton , University of California, Berkeley
pp. 155

Model order reduction of nonuniform transmission lines using integrated congruence transform (PDF)

E. Gad , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
M. Nakhla , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
pp. 238-243

Partial task assignment of task graphs under heterogeneous resource constraints (PDF)

R. Szymanek , Dept. of Comput. Sci., Lund Univ., Sweden
K. Kuchcinski , Dept. of Comput. Sci., Lund Univ., Sweden
pp. 244-249

Dynamic hardware/software partitioning: a first approach (PDF)

G. Stitt , Dept. of Comput. Sci. & Eng., Univ. of California, Riverside, CA, USA
R. Lysecky , Dept. of Comput. Sci. & Eng., Univ. of California, Riverside, CA, USA
F. Vahid , Dept. of Comput. Sci. & Eng., Univ. of California, Riverside, CA, USA
pp. 250-255

Automatic application-specific instruction-set extensions under microarchitectural constraints (PDF)

K. Atasu , Processor Archit. Lab., Swiss Fed. Inst. of Technol. Lausanne, Switzerland
L. Pozzi , Processor Archit. Lab., Swiss Fed. Inst. of Technol. Lausanne, Switzerland
P. Ienne , Processor Archit. Lab., Swiss Fed. Inst. of Technol. Lausanne, Switzerland
pp. 256-261

Instruction encoding synthesis for architecture exploration using hierarchical processor models (PDF)

A. Nohl , CoWare Inc., San Jose, CA, USA
V. Greive , CoWare Inc., San Jose, CA, USA
G. Braun , CoWare Inc., San Jose, CA, USA
A. Hoffman , CoWare Inc., San Jose, CA, USA
pp. 262-267

Quantum-dot cellular automata: computing by field polarization (PDF)

G.H. Bernstein , Center for Nano Sci. & Technoogy, Univ. of Notre Dame, IN, USA
pp. 268-273

Recent advances and future prospects in single-electronics (PDF)

C. Wasshuber , Texas Instruments, Dallas, TX, USA
pp. 274-275

Coverage-oriented verification of Banias (PDF)

A. Gluska , Sci. Industries Center, Intel, Haifa, Israel
pp. 280-285

Coverage directed test generation for functional verification using Bayesian networks (PDF)

S. Fine , IBM Res. Lab., Haifa, Israel
A. Ziv , IBM Res. Lab., Haifa, Israel
pp. 286-291
SESSION 13: Timing-Oriented Placement

Multilevel Global Placement with Retiming (Abstract)

Jason Cong , University of California, Los Angeles
Xin Yuan , University of California, Los Angeles
pp. 208

Force Directed Mongrel with Physical Net Constraints (Abstract)

Sung-Woo Hur , Donga University
Tung Cao , Intel Corporation
Karthik Rajagopal , Intel Corporation
Yegna Parasuram , Intel Corporation
Amit Chowdhary , Intel Corporation
Vladimir Tiourin , Intel Corporation
Bill Halpin , Syracuse Univ. and Intel Corporation
pp. 214

Automatic communication refinement for system level design (PDF)

S. Abdi , Center for Embedded Comput. Syst., Univ. of California, Irvine, CA, USA
D. Shin , Center for Embedded Comput. Syst., Univ. of California, Irvine, CA, USA
D. Gajski , Center for Embedded Comput. Syst., Univ. of California, Irvine, CA, USA
pp. 300-305

CoCo: a hardware/software platform for rapid prototyping of code compression technique (PDF)

H. Lekatsas , NEC Labs America, Princeton, NJ, USA
J. Henkel , NEC Labs America, Princeton, NJ, USA
S. Chakradhar , NEC Labs America, Princeton, NJ, USA
V. Jakkula , NEC Labs America, Princeton, NJ, USA
M. Sankaradass , NEC Labs America, Princeton, NJ, USA
pp. 306-311

A tool for describing and evaluating hierarchical real-time bus scheduling policies (PDF)

T. Meyerowitz , UC, Berkeley, CA, USA
C. Pinello , UC, Berkeley, CA, USA
A. Sangiovanni-Vincetelli , UC, Berkeley, CA, USA
pp. 312-317

A transformation based algorithm for reversible logic synthesis (PDF)

D.M. Miller , Dept. of Comput. Sci., Univ. of Victoria, BC, Canada
pp. 318-323
SESSION 15: Issues in Partitioning & Design Space Exploration for Codesign

Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction (PDF)

A. Saifhashemi , Dept. of Comput. Eng., Amirkabir Univ. of Technol., Tehran, Iran
H. Pedram , Dept. of Comput. Eng., Amirkabir Univ. of Technol., Tehran, Iran
pp. 330-333

On-chip logic minimization (PDF)

R. Lysecky , Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
F. Vahid , Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
pp. 334-337

Parameter variations and impact on circuits and microarchitecture (PDF)

S. Borkar , Circuit Res., Intel Labs, Hillsboro, OR, USA
T. Karnik , Circuit Res., Intel Labs, Hillsboro, OR, USA
S. Narendra , Circuit Res., Intel Labs, Hillsboro, OR, USA
J. Tschanz , Circuit Res., Intel Labs, Hillsboro, OR, USA
A. Keshavarzi , Circuit Res., Intel Labs, Hillsboro, OR, USA
V. De , Circuit Res., Intel Labs, Hillsboro, OR, USA
pp. 338-342

Death, taxes and failing chips (PDF)

C. Visweswariah , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 343-347

Computation and refinement of statistical bounds on circuit delay (PDF)

A. Agarwal , Michigan Univ., Ann Arbor, MI, USA
D. Blaauw , Michigan Univ., Ann Arbor, MI, USA
pp. 348-353
SESSION 18: Simulation Coverage and Generation for Verification

Coverage-Oriented Verification of Banias (Abstract)

Alon Gluska , Intel Israel, Haifa
pp. 280

Re-use-centric architecture for a fully accelerated testbench environment (PDF)

R. Henftling , Infineon Technol. AG, Munich, Germany
A. Zinn , Infineon Technol. AG, Munich, Germany
M. Bauer , Infineon Technol. AG, Munich, Germany
M. Zambaldi , Infineon Technol. AG, Munich, Germany
W. Ecker , Infineon Technol. AG, Munich, Germany
pp. 372-375

An effective capacitance based driver output model for on-chip RLC interconnects (PDF)

K. Agarwal , Michigan Univ., USA
D. Sylvester , Michigan Univ., USA
D. Blaauw , Michigan Univ., USA
pp. 376-381

Delay and slew metrics using the lognormal distribution (PDF)

C.J. Alpert , IBM Corp., Austin, TX, USA
F. Liu , IBM Corp., Austin, TX, USA
C. Kashyap , IBM Corp., Austin, TX, USA
A. Devgan , IBM Corp., Austin, TX, USA
pp. 382-385

Non-iterative switching window computation for delay-noise (PDF)

B. Thudi , Michigan Univ., Ann Arbor, MI, USA
D. Blaauw , Michigan Univ., Ann Arbor, MI, USA
pp. 390-395

Architecture-level performance evaluation of component-based embedded systems (PDF)

J.T. Russell , Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M.F. Jacome , Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 396-401

An IDF-based trace transformation method for communication refinement (PDF)

A.D. Pimentel , Dept. of Comput. Sci., Amsterdam Univ., Netherlands
C. Erbas , Dept. of Comput. Sci., Amsterdam Univ., Netherlands
pp. 402-407

Schedulers as model-based design elements in programmable heterogeneous multiprocessors (PDF)

J.M. Paul , Electr. & Comput. Eng. Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
A. Bobrek , Electr. & Comput. Eng. Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.E. Nelson , Electr. & Comput. Eng. Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.J. Pieper , Electr. & Comput. Eng. Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
D.E. Thomas , Electr. & Comput. Eng. Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 408-411
SESSION 20: New Topics in Logic Synthesis

On-Chip Logic Minimization (Abstract)

Roman Lysecky , University of California, Riverside
Frank Vahid , University of California, Riverside
pp. 334
SESSION 21: Special Session - Coping with Variability: The End of Deterministic Design

Parameter Variations and Impact on Circuits and Microarchitecture (Abstract)

Shekhar Borkar , Circuit Research, Intel Labs, Hillsboro, OR
Tanay Karnik , Circuit Research, Intel Labs, Hillsboro, OR
Siva Narendra , Circuit Research, Intel Labs, Hillsboro, OR
Jim Tschanz , Circuit Research, Intel Labs, Hillsboro, OR
Ali Keshavarzi , Circuit Research, Intel Labs, Hillsboro, OR
Vivek De , Circuit Research, Intel Labs, Hillsboro, OR
pp. 338

How to make efficient communication, collaboration, and optimization from system to chip (PDF)

A. Matsuzawa , Dept. of Phys. Electron., Tokyo Inst. of Technol., Japan
pp. 417-418

System-on-chip beyond the nanometer wall (PDF)

P. Magarshack , Central R & D, STMicroelectronics, Crolles, France
pp. 419-424

A hybrid SAT-based decision procedure for separation logic with uninterpreted functions (PDF)

S.A. Seshia , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
S.K. Lahiri , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.E. Bryant , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 425-430

Symbolic representation with ordered function templates (PDF)

A. Goel , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 431-435
SESSION 23: Testbench, Verification and Debugging: Practical Considerations

Advanced Techniques for RTL Debugging (Abstract)

Yu-Chin Hsu , Novas Software Inc., San Jose, CA
Bassam Tabbara , Novas Software Inc., San Jose, CA
Yirng-An Chen , Novas Software Inc., San Jose, CA
Furshing Tsai , Novas Software Inc., San Jose, CA
pp. 362

Solving the latch mapping problem in an industrial setting (PDF)

K. Ng , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 442-447

Static analysis of transaction-level models (PDF)

G. Agosta , Politecnico di Milano, Italy
F. Bruschi , Politecnico di Milano, Italy
D. Sciuto , Politecnico di Milano, Italy
pp. 448-453

Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals (PDF)

M. Jersak , Tech. Univ. of Braunschweig, Inst. of Comput. & Commun. Network Eng., Braunschweig, Germany
R. Ernst , Tech. Univ. of Braunschweig, Inst. of Comput. & Commun. Network Eng., Braunschweig, Germany
pp. 454-459
SESSION 24: Delay and Noise Modeling in the Nanometer Regime

Delay and Slew Metrics Using the Lognormal Distribution (Abstract)

Charles J. Alpert , IBM Corp., Austin, Texas
Frank Liu , IBM Corp., Austin, Texas
Chandramouli Kashyap , IBM Corp., Austin, Texas
Anirudh Devgan , IBM Corp., Austin, Texas
pp. 382

Blade and Razor: Cell and Interconnect Delay Analysis Using Current-Based Models (Abstract)

John F. Croix , Silicon Metrics Corporation, Austin, Texas
D. F. Wong , University of Illinois at Urbana-Champaign
pp. 386

Non-Iterative Switching Window Computation for Delay-Noise (Abstract)

Bhavana Thudi , University of Michigan, Ann Arbor, MI
David Blaauw , University of Michigan, Ann Arbor, MI
pp. 390
SESSION 25: Modeling Issues in the Design of Embedded Systems

Architecture-Level Performance Evaluation of Component-Based Embedded Systems (Abstract)

Jeffry T Russell , University of Texas at Austin
Margarida F Jacome , University of Texas at Austin
pp. 396

Piecewise polynomial nonlinear model reduction (PDF)

Ning Dong , Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, USA
J. Roychowdhury , Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, USA
pp. 484-489

A TBR-based trajectory piecewise-linear algorithm for generating accurate low-order models for nonlinear analog circuits and MEMS (PDF)

D. Vasilyev , Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
M. Rewienski , Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
J. White , Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
pp. 490-495

Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling (PDF)

C. Fang Fang , Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.A. Rutenbar , Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
M. Puschel , Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Tsuhan Chen , Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 496-501
SESSION 26: Special Session - How Application/Technology Evolutions Will Shape Classical EDA?

High-level synthesis of asynchronous systems by data-driven decomposition (PDF)

C.G. Wong , Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA, USA
A.J. Martin , Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA, USA
pp. 508-513

Using estimates from behavioral synthesis tools in compiler-directed design space exploration (PDF)

B. So , Inf. Sci. Inst., Southern California Univ., Marina del Rey, CA, USA
P.C. Diniz , Inf. Sci. Inst., Southern California Univ., Marina del Rey, CA, USA
M.W. Hall , Inf. Sci. Inst., Southern California Univ., Marina del Rey, CA, USA
pp. 514-519
SESSION 26: Special Session - How Application/Technology Evolutions Will Shape Classical EDA?

Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm (PDF)

C.Y. Lau , Microsystems Technol. Lab., Massachusetts Inst. of Technol., Cambridge, MA, USA
M.H. Perrott , Microsystems Technol. Lab., Massachusetts Inst. of Technol., Cambridge, MA, USA
pp. 526-531
SESSION 27: SAT and BDD Algorithms for Verification Tools

Symbolic Representation with Ordered Function Templates (Abstract)

Amit Goel , Carnegie Mellon University, Pittsburgh, PA
Gagan Hasteer , Innologic Systems, San Jose, CA
Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
pp. 431

Symbolic analysis of analog circuits with hard nonlinearity (PDF)

A. Manthe , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Zhao Li , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
C.-J. Richard Shi , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 542-545

Nanometer design: place your bets (PDF)

A.B. Kahng , University of California at San Diego
pp. 546-547
SESSION 28: Elements of Functional and Performance Analysis

Enabling Scheduling Analysis of Heterogeneous Systems with Multi-Rate Data Dependencies and Rate Intervals (Abstract)

Marek Jersak , Technical University of Braunschweig, Germany
Rolf Ernst , Technical University of Braunschweig, Germany
pp. 454

Automatic Trace Analysis for Logic of Constraints (Abstract)

Xi Chen , University of California at Riverside
Harry Hsieh , University of California at Riverside
Felice Balarin , Cadence Berkeley Laboratories, Berkeley, CA
Yosinori Watanabe , Cadence Berkeley Laboratories, Berkeley, CA
pp. 460

Seed encoding with LFSRs and cellular automata (PDF)

A.A. Al-Yamani , Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 560-565

Ultimate low cost analog BIST (PDF)

M. Negreiros , Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
L. Carro , Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
A.A. Susin , Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 570-573
SESSION 29: Nonlinear Model Order Reduction

Piecewise Polynomial Nonlinear Model Reduction (Abstract)

Ning Dong , University of Minnesota
Jaijeet Roychowdhury , University of Minnesota
pp. 484

A TBR-based Trajectory Piecewise-Linear Algorithm for Generating Accurate Low-order Models for Nonlinear Analog Circuits and MEMS (Abstract)

Dmitry Vasilyev , Massachusetts Institute of Technology, Cambridge
Michal Rewienski , Massachusetts Institute of Technology, Cambridge
Jacob White , Massachusetts Institute of Technology, Cambridge
pp. 490

Optimum positioning of interleaved repeaters in bidirectional buses (PDF)

M. Ghoneima , Northwestern Univ., Evanston, IL, USA
Y. Ismail , Northwestern Univ., Evanston, IL, USA
pp. 586-591

Synthesizing optimal filters for crosstalk-cancellation for high-speed buses (PDF)

J. Ren , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
M. Greenstreet , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 592-597

Fast timing-driven partitioning-based placement for island style FPGAs (PDF)

P. Maidee , Electr. & Comput. Eng. Dept., Minnesota Univ., Minneapolis, MN, USA
C. Ababei , Electr. & Comput. Eng. Dept., Minnesota Univ., Minneapolis, MN, USA
K. Bazargan , Electr. & Comput. Eng. Dept., Minnesota Univ., Minneapolis, MN, USA
pp. 598-603

Compiler-generated communication for pipelined FPGA applications (PDF)

H.E. Ziegler , Inf. Sci. Inst., Southern California Univ., Marina del Rey, CA, USA
M.W. Hall , Inf. Sci. Inst., Southern California Univ., Marina del Rey, CA, USA
P.C. Diniz , Inf. Sci. Inst., Southern California Univ., Marina del Rey, CA, USA
pp. 610-615

Data communication estimation and reduction for reconfigurable systems (PDF)

A. Kaplan , Comput. Sci. Dept., California Univ., Los Angeles, CA, USA
P. Brisk , Comput. Sci. Dept., California Univ., Los Angeles, CA, USA
pp. 616-621

Low-power design methodology for an on-chip with adaptive bandwidth capability (PDF)

R. Bashirullah , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 628-633

Power-aware issue queue design for speculative instructions (PDF)

T. Moreshet , Div. of Eng., Brown Univ., Providence, RI, USA
R.I. Bahar , Div. of Eng., Brown Univ., Providence, RI, USA
pp. 634-637

State-based power analysis for systems-on-chip (PDF)

R.A. Bergamaschi , TJ Watson Res. Center, IBM, Yorktown Heights, NY, USA
pp. 638-641

Libraries: LifeJacket or Straitjacket (PDF)

C. Sechen , University of Washington
pp. 642-643

Switch-level emulation (PDF)

A. Ejlali , Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran
Seyed Ghassem Miremadi , Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran
pp. 644-649

Designing fault tolerant systems into SRAM-based FPGAs (PDF)

F. Lima , Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
L. Carro , Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
R. Reis , Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 650-655

Determining appropriate precisions for signals in fixed-point IIR filters (PDF)

J. Carletta , Electr. & Comput. Eng., Akron Univ., OH, USA
R. Veillette , Electr. & Comput. Eng., Akron Univ., OH, USA
F. Krach , Electr. & Comput. Eng., Akron Univ., OH, USA
Z. Fang , Electr. & Comput. Eng., Akron Univ., OH, USA
pp. 656-661
SESSION 33: Novel Self-Test Methods

Ultimate Low Cost Analog BIST (Abstract)

Marcelo Negreiros , Universidade Federal do Rio Grande do Sul - PPGC, Porto Alegre, RS, Brazil
Luigi Carro , Universidade Federal do Rio Grande do Sul - PPGC, Porto Alegre, RS, Brazil
Altamiro Amadeu Susin , Universidade Federal do Rio Grande do Sul - PPGC, Porto Alegre, RS, Brazil
pp. 570

Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models (PDF)

A. Krstic , California Univ., Santa Barbara, CA, USA
L.-C. Wang , California Univ., Santa Barbara, CA, USA
K.-T. Cheng , California Univ., Santa Barbara, CA, USA
pp. 668-673

Using satisfiability in application-dependent testing of FPGA interconnects (PDF)

M.B. Tahoori , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 678-681

Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL (PDF)

J.G. Maneatis , True Circuits, Inc., Los Altos, CA, USA
J. Kim , True Circuits, Inc., Los Altos, CA, USA
I. McClatchie , True Circuits, Inc., Los Altos, CA, USA
pp. 688-690
SESSION 35: Compilation Techniques for Reconfigurable Devices

Compiler-Generated Communication for Pipelined FPGA Applications (Abstract)

Heidi E. Ziegler , University of Southern California / Information Sciences Institute, Marina del Rey, CA
Mary W. Hall , University of Southern California / Information Sciences Institute, Marina del Rey, CA
Pedro C. Diniz , University of Southern California / Information Sciences Institute, Marina del Rey, CA
pp. 610

A 1.3GHz fifth generation SPARC64 microprocessor (PDF)

T. Motokurumada , Fujitsu Ltd., Kawasaki, Japan
H. Ando , Fujitsu Ltd., Kawasaki, Japan
A. Inoue , Fujitsu Ltd., Kawasaki, Japan
I. Sugiyama , Fujitsu Ltd., Kawasaki, Japan
T. Asakawa , Fujitsu Ltd., Kawasaki, Japan
K. Morita , Fujitsu Ltd., Kawasaki, Japan
T. Muta , Fujitsu Ltd., Kawasaki, Japan
Y. Yoshida , Fujitsu Ltd., Kawasaki, Japan
S. Okada , Fujitsu Ltd., Kawasaki, Japan
H. Yamashita , Fujitsu Ltd., Kawasaki, Japan
Y. Satsukawa , Fujitsu Ltd., Kawasaki, Japan
A. Konmoto , Fujitsu Ltd., Kawasaki, Japan
R. Yamashita , Fujitsu Ltd., Kawasaki, Japan
H. Sugiyama , Fujitsu Ltd., Kawasaki, Japan
pp. 702-705

A 1.5GHz third generation Itanium 2 processor (PDF)

J. Stinson , Intel Corp., Santa Clara, CA, USA
S. Rusu , Intel Corp., Santa Clara, CA, USA
pp. 706-709

Formal verification - prove it or pitch it (PDF)

R. Gupta , University of California at San Diego
pp. 710-711
SESSION 36: Architectural Power Estimation and Optimization

Power-Aware Issue Queue Design for Speculative Instructions (Abstract)

Tali Moreshet , Brown University, Providence, RI
R. Iris Bahar , Brown University, Providence, RI
pp. 634

State-Based Power Analysis for Systems-on-Chip (Abstract)

Reinaldo A. Bergamaschi , IBM T. J. Watson Research Center Yorktown, Heights, NY
Yunjian W. Jiang , University of California, Berkeley
pp. 638

On-chip interconnect-aware design and modeling methodology based on high bandwidth transmission line devices (PDF)

D. Goren , IBM Haifa R&D Labs, Israel
R. Gordin , IBM Haifa R&D Labs, Israel
I.A. Wagner , IBM Haifa R&D Labs, Israel
A. Barger , IBM Haifa R&D Labs, Israel
A. Amir , IBM Haifa R&D Labs, Israel
B. Livshitz , IBM Haifa R&D Labs, Israel
A. Sherman , IBM Haifa R&D Labs, Israel
M. Zelikson , IBM Haifa R&D Labs, Israel
pp. 724-727
SESSION 38: Techniques for Reconfigurable Logic Applications

Switch-Level Emulation (Abstract)

Alireza Ejlali , Sharif University of technology, Tehran, Iran
Seyed Ghassem Miremadi , Sharif University of technology, Tehran, Iran
pp. 644
SESSION 39: Test and Diagnosis for Complex Designs

Test Generation for Designs with Multiple Clocks (Abstract)

Xijiang Lin , Mentor Graphics Corp., Wilsonville, OR
Rob Thompson , Mentor Graphics Corp., Wilsonville, OR
pp. 662

On test data compression and n-detection test sets (PDF)

I. Pomeranz , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 748-751
SESSION 39: Test and Diagnosis for Complex Designs

Using Embedded Infrastructure IP for SOC Post-Silicon Verification (Abstract)

Yu Huang , Mentor Graphics Co., Waltham, MA
Wu-Tung Cheng , Mentor Graphics Co., Wilsonville, OR
pp. 674

Instruction set compiled simulation: a technique for fast and flexible instruction set simulation (PDF)

M. Reshadi , Architectures & Compilers for Embedded Syst. Lab., California Univ., Irvine, CA, USA
P. Mishra , Architectures & Compilers for Embedded Syst. Lab., California Univ., Irvine, CA, USA
N. Dutt , Architectures & Compilers for Embedded Syst. Lab., California Univ., Irvine, CA, USA
pp. 758-763
SESSION 40: Special Session - Highlights of ISSCC: High-Speed Heterogenous Design Techniques

Design of a 10GHz Clock Distribution Network Using Coupled Standing-Wave Oscillators (Abstract)

Frank O'Mahony , Stanford University, CA
C. Patrick Yue , Aeluros, Inc., Mountain View, CA
Mark A. Horowitz , Stanford University, CA
S. Simon Wong , Stanford University, CA
pp. 682

Designing mega-ASICs in nanogate technologies (PDF)

D.E. Lackey , IBM Microelectron. Div., Essex Junction, VT, USA
P.S. Zuchowski , IBM Microelectron. Div., Essex Junction, VT, USA
J. Koehl , IBM Microelectron. Div., Essex Junction, VT, USA
pp. 770-775

Architecting ASIC libraries and flows in nanometer era (PDF)

C. Bittlestone , Texas Instruments Inc., Dallas, TX, USA
A. Hill , Texas Instruments Inc., Dallas, TX, USA
V. Singhal , Texas Instruments Inc., Dallas, TX, USA
N.V. Arvind , Texas Instruments Inc., Dallas, TX, USA
pp. 776-781

Exploring regular fabrics to optimize the performance-cost trade-off (PDF)

L. Pileggi , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
H. Schmit , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
A.J. Strojwas , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
P. Gopalakrishnan , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
V. Kheterpal , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
A. Koorapaty , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
C. Patel , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
V. Rovner , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
K.Y. Tong , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 782-787

Pushing ASIC performance in a power envelope (PDF)

R. Puri , IBM Res., Yorktown Hts, NY, USA
L. Stok , IBM Res., Yorktown Hts, NY, USA
pp. 788-793
SESSION 41: Special Session - Highlights of ISSCC and The Design of State-of-the-Art Microprocessors

A 1.5GHz Third Generation Itanium? 2 Processor (Abstract)

Jason Stinson , Intel Corporation, Santa Clara, CA
Stefan Rusu , Intel Corporation, Santa Clara, CA
pp. 706
SESSION 42: Panel - Formal Verification - Prove It or Pitch It
SESSION 43: High Frequency Interconnect Modeling

Algorithms in FastImp: A Fast and Wideband Impedance Extraction Program For Complicated 3-D Geometries (Abstract)

Zhenhai Zhu , Massachusetts Institute of Technology, Cambridge
Ben Song , Massachusetts Institute of Technology, Cambridge
Jacob White , Massachusetts Institute of Technology, Cambridge
pp. 712

Checking satisfiability of a conjunction of BDDs (PDF)

R. Damiano , Adv. Technol. Group, Synopsis Inc., Hillsboro, OR, USA
J. Kukula , Adv. Technol. Group, Synopsis Inc., Hillsboro, OR, USA
pp. 818-823

Learning from BDDs in SAT-based bounded model checking (PDF)

A. Gupta , NEC Labs America, Princeton, NJ, USA
M. Ganai , NEC Labs America, Princeton, NJ, USA
pp. 824-829

A fast pseudo-Boolean constraint solver (PDF)

D. Chai , California Univ., Berkeley, CA, USA
A. Kuehlmann , California Univ., Berkeley, CA, USA
pp. 830-835

Shatter: efficient symmetry-breaking for Boolean satisfiability (PDF)

F.A. Aloul , Dept. of EECS, Michigan Univ., USA
I.L. Markov , Dept. of EECS, Michigan Univ., USA
K.A. Sakallah , Dept. of EECS, Michigan Univ., USA
pp. 836-839
SESSION 44: Novel Approaches in Test Cost Reduction

A Cost-Effective Scan Architecture for Scan Testing with Non-Scan Test Power and Test Application Cost (Abstract)

Dong Xiang , Tsinghua University, Beijing, China
Shan Gu , Tsinghua University, Beijing, China
Jia-Guang Sun , Tsinghua University, Beijing, China
Yu-liang Wu , The Chinese Univ. of Hong Kong, Shatin N.T., Hong Kong
pp. 744

Design of a 17-million gate network processor using a design factory (PDF)

G.-E. Descamps , Silicon Access Networks Inc., San Jose, CA, USA
S. Bagalkotkar , Silicon Access Networks Inc., San Jose, CA, USA
S. Ganesan , Silicon Access Networks Inc., San Jose, CA, USA
S. Iyengar , Silicon Access Networks Inc., San Jose, CA, USA
A. Pirson , Silicon Access Networks Inc., San Jose, CA, USA
pp. 844-849

Hybrid hierarchical timing closure methodology for a high performance and low power DSP (PDF)

K. Shi , Professional Services, Synopsis Inc., Dallas, TX, USA
pp. 850-855

Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations (PDF)

I.A. Ferzli , Dept. of ECE, Toronto Univ., Ont., Canada
F.N. Najm , Dept. of ECE, Toronto Univ., Ont., Canada
pp. 856-859

Temporofunctional crosstalk noise analysis (PDF)

D. Chai , Dept. of EECS, California Univ., Berkeley, CA, USA
pp. 860-863

Static noise analysis with noise windows (PDF)

K. Tseng , Cadence Design Syst., San Jose, CA, USA
V. Kariat , Cadence Design Syst., San Jose, CA, USA
pp. 864-868

Embedded intelligent SRAM (PDF)

P. Jain , Lab. for Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
G.E. Suh , Lab. for Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
S. Devadas , Lab. for Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
pp. 869-874

Improved indexing for cache miss reduction in embedded systems (PDF)

T. Givargis , Dept. of Comput. Sci., California Univ., Irvine, CA, USA
pp. 875-880
SESSION 46: Special Session - ASIC Design in Nanometer Era - Dead or Alive?

Pushing ASIC Performance in a Power Envelope (Abstract)

Ruchir Puri , IBM Research, Yorktown Hts, NY
Leon Stok , IBM Research, Yorktown Hts, NY
John Cohn , IBM Microelectronics, Essex Jn, VT
David Kung , IBM Research, Yorktown Hts, NY
David Pan , IBM Research, Yorktown Hts, NY
Dennis Sylvester , University of Michigan, Ann Arbor, MI
Ashish Srivastava , University of Michigan, Ann Arbor, MI
Sarvesh Kulkarni , University of Michigan, Ann Arbor, MI
pp. 788
SESSION 47: Floorplanning and Placement

An Algebraic Multigrid Solver for Analytical Placement with Layout Based Clustering (Abstract)

Hongyu Chen , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
Nan-Chi Chou , Mentor Graphics Corporation, San Jose, CA
Andrew B. Kahng , University of California, San Diego
John F. MacDonald , Mentor Graphics Corporation, San Diego, CA
Peter Suaris , Mentor Graphics Corporation, Wilsonville, OR
Bo Yao , University of California, San Diego
Zhengyong Zhu , University of California, San Diego
pp. 794

Wire Length Prediction based Clustering and its Application in Placement (Abstract)

Bo Hu , Univ. of California, Santa Barbara
Malgorzata Marek-Sadowska , Univ. of California, Santa Barbara
pp. 800

A survey of techniques for energy efficient on-chip communication (PDF)

V. Raghunathan , Dept. of Electr. Eng., UC Los Angeles, CA, USA
M.B. Srivastava , Dept. of Electr. Eng., UC Los Angeles, CA, USA
pp. 900-905

Extending the lifetime of a network of battery-powered mobile devices by remote processing: a Markovian decision-based approach (PDF)

P. Rong , Dept. of Electr. Eng., Southern California Univ., Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng., Southern California Univ., Los Angeles, CA, USA
pp. 906-911
SESSION 48: Advances in SAT

Learning from BDDs in SAT-based Bounded Model Checking (Abstract)

Aarti Gupta , NEC Labs America, Princeton, NJ
Malay Ganai , NEC Labs America, Princeton, NJ
Chao Wang , University of Colorado, Boulder
Zijiang Yang , NEC Labs America, Princeton, NJ
Pranav Ashar , NEC Labs America, Princeton, NJ
pp. 824

A low-energy chip-set for wireless intercom (PDF)

M.J. Ammer , California Univ., Berkeley, CA, USA
M. Sheets , California Univ., Berkeley, CA, USA
T. Karalar , California Univ., Berkeley, CA, USA
M. Kuulasa , California Univ., Berkeley, CA, USA
J. Rabaey , California Univ., Berkeley, CA, USA
pp. 916-919

Optimal integer delay budgeting on directed acyclic graphs (PDF)

E. Bozorgzadeh , Comput. Sci. Dept., California Univ., Los Angeles, CA, USA
S. Ghiasi , Comput. Sci. Dept., California Univ., Los Angeles, CA, USA
pp. 920-925

Optimizations for a simulator construction system supporting reusable components (PDF)

D.A. Penry , Dept. of Comput. Sci., Princeton Univ., USA
D.I. August , Dept. of Comput. Sci., Princeton Univ., USA
pp. 926-931
SESSION 49: Novel Design Methodologies and Signal Integrity

Hybrid Hierarchical Timing Closure Methodology for a High Performance and Low Power DSP (Abstract)

Kaijian Shi , Professional Services, Synopsys Inc., Dallas, TX
Graig Godwin , Texas Instruments, Inc., Dallas, TX
pp. 850

Crosstalk noise in FPGAs (PDF)

Y. Ran , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
M. Marek-Sadowska , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 944-949

Simple metrics for slew rate of RC circuits based on two circuit moments (PDF)

K. Agarwal , Michigan Univ., USA
D. Sylvester , Michigan Univ., USA
D. Blaauw , Michigan Univ., USA
pp. 950-953

Performance trade-off analysis of analog circuits by normal-boundary intersection (PDF)

G. Stehr , Inst. for Electron. Design Autom., Tech. Univ. of Munich, Germany
H. Graeb , Inst. for Electron. Design Autom., Tech. Univ. of Munich, Germany
K. Antreich , Inst. for Electron. Design Autom., Tech. Univ. of Munich, Germany
pp. 958-963

Support vector machines for analog circuit performance representation (PDF)

F. De Bernardinis , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
M.I. Jordan , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. SangiovanniVincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 964-969

Efficient description of the design space of analog circuits (PDF)

Md.M. Hershenson , Barcelona Design, Inc., Newark, CA, USA
pp. 970-973

Architectural selection of A/D converters (PDF)

M. Vogels , Katholieke Universiteit Leuven, Belgium
G. Gielen , Katholieke Universiteit Leuven, Belgium
pp. 974-977

Author/Panelist Index (PDF)

pp. 978-981
SESSION 51: Special Session - Design Automation for Quantum Circuits
SESSION 52: Energy-Aware System Design

A Survey of Techniques for Energy Efficient On-Chip Communication (Abstract)

Vijay Raghunathan , UC Los Angeles, CA
Mani B. Srivastava , UC Los Angeles, CA
Rajesh K. Gupta , UC San Diego, CA
pp. 900

Energy-Aware MPEG-4 FGS Streaming (Abstract)

Kihwan Choi , Univ. of Southern California, Los Angeles
Kwanho Kim , Seoul National University, Korea
Massoud Pedram , Univ. of Southern California, Los Angeles
pp. 912

A Low-Energy Chip-Set for Wireless Intercom (Abstract)

M. Josie Ammer , University of California, Berkeley
Michael Sheets , University of California, Berkeley
Tufan Karalar , University of California, Berkeley
Mika Kuulusa , University of California, Berkeley
Jan Rabaey , University of California, Berkeley
pp. 916
SESSION 53: Budgeting, Simulation and Statistical Timing

Optimal Integer Delay Budgeting on Directed Acyclic Graphs (Abstract)

E. Bozorgzadeh , University of California, Los Angeles (UCLA)
S. Ghiasi , University of California, Los Angeles (UCLA)
A. Takahashi , Tokyo Institute of Technology, Japan
M. Sarrafzadeh , University of California, Los Angeles (UCLA)
pp. 920

Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits (Abstract)

J. A. G. Jess , Eindhoven University of Technology, The Netherlands
K. Kalafala , IBM Microelectronics Division, East Fishkill, NY
S. R. Naidu , Eindhoven University of Technology, The Netherlands
R. H. J. M. Otten , Eindhoven University of Technology, The Netherlands
C. Visweswariah , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 932
SESSION 54: Interconnect Noise Avoidance Methodologies & Slew Rate Prediction

Crosstalk Noise in FPGAs (Abstract)

Yajun Ran , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 944

Simple Metrics for Slew Rate of RC Circuits Based on Two Circuit Moments (Abstract)

Kanak Agarwal , University of Michigan
Dennis Sylvester , University of Michigan
David Blaauw , University of Michigan
pp. 950

Post-Route Gate Sizing for Crosstalk Noise Reduction (Abstract)

Murat R. Becer , Motorola Inc.
David Blaauw , Univ. of Michigan Ann Arbor
Ilan Algor , Motorola Inc.
Rajendran Panda , Motorola Inc.
Chanhee Oh , Motorola Inc.
Vladimir Zolotov , Motorola Inc.
Ibrahim N. Hajj , Univ. of Illinois Urbana-Champaign
pp. 954
SESSION 55: Analog Design Space Exploration

Performance Trade-off Analysis of Analog Circuits By Normal-Boundary Intersection (Abstract)

Guido Stehr , Technical University of Munich, Germany
Helmut Graeb , Technical University of Munich, Germany
Kurt Antreich , Technical University of Munich, Germany
pp. 958

Support Vector Machines for Analog Circuit Performance Representation (Abstract)

F. De Bernardinis , University of California, Berkeley; Universit? di Pisa, Italy
M. I. Jordan , University of California, Berkeley
A. Sangiovanni-Vincentelli , University of California, Berkeley
pp. 964

Architectural Selection of A/D Converters (Abstract)

Martin Vogels , Katholieke Universiteit Leuven, Belgium
Georges Gielen , Katholieke Universiteit Leuven, Belgium
pp. 974

Author Index (PDF)

pp. 978
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