The Community for Technology Leaders
Design Automation Conference (2003)
Anaheim, CA
June 2, 2003 to June 6, 2003
ISBN: 1-58113-688-9
TABLE OF CONTENTS
SESSION 1: Special Session - Real Challenges and Solutions for Validating System-on-Chip

Verification Strategy for Integration 3G Baseband SoC (Abstract)

Yves Mathys , Motorola Inc., Switzerland
Andr? Ch?telain , Motorola Inc., Switzerland
pp. 7
SESSION 2: Panel - Reshaping EDA for Power
SESSION 3: Design for Manufacturability and Global Routing

A Cost-Driven Lithographic Correction Methodology Based on Off-the-Shelf Sizing Tools (Abstract)

A. B. Kahng , University of California at San Diego
J. Yang , University of Michigan at Ann Arbor
D. Sylvester , University of Michigan at Ann Arbor
P. Gupta , University of California at San Diego
pp. 16

Performance-Impact Limited Area Fill Synthesis (Abstract)

Andrew B. Kahng , UCSD, La Jolla, CA
Yu Chen , UCLA Computer Science Dept., Los Angeles, CA
Puneet Gupta , UCSD, La Jolla, CA
pp. 22

Improved Global Routing through Congestion Estimation (Abstract)

Patrick H. Madden , SUNY Binghamton CSD, Binghamton NY
Raia T. Hadsell , SUNY Binghamton CSD, Binghamton NY
pp. 28

Microarchitecture Evaluation With Physical Planning (Abstract)

Ashok Jagannathan , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
Glenn Reinman , University of California, Los Angeles
Michail Romesis , University of California, Los Angeles
pp. 32
SESSION 4: Design Analysis Techniques

Energy-Aware Design Techniques for Differential Power Analysis Protection (Abstract)

Fabrizio Pro , BullDAST s.r.l., Torino, Italy
Massimo Poncino , Univ. di Verona, Italy
Enrico Macii , Politecnico di Torino, Italy
Luca Benini , Univ. di Bologna, Italy
Elvira Omerbegovic , BullDAST s.r.l., Torino, Italy
Alberto Macii , Politecnico di Torino, Italy
pp. 36

A Timing-Accurate Modeling and Simulation Environment for Networked Embedded Systems (Abstract)

Franco Fummi , Universit? di Verona, Italy
Paolo Gallo , Telecom Italia Lab, Torino, Italy
Massimo Poncino , Universit? di Verona, Italy
Giovanni Perbellini , Universit? di Verona, Italy
Stefano Martini , Universit? di Verona, Italy
Fabio Ricciato , Telecom Italia Lab, Torino, Italy
pp. 42

Application of Design Patterns for Hardware Design (Abstract)

Vytautas Stuikys , Kaunas University of Technology
Robertas Damasevicius , Kaunas University of Technology
Giedrius Majauskas , Kaunas University of Technology
pp. 48
SESSION 5: Embedded Hardware Design Case Studies

A Fully-Programmable Memory Management System Optimizing Queue Handling at Multi Gigabit Rates (Abstract)

I. Papaefstathiou , Ellemedia Technologies, Athens, Greece
N. Zervos , Ellemedia Technologies, Athens, Greece
A. Nikologiannis , Ellemedia Technologies, Athens, Greece
G. Kornaros , Ellemedia Technologies, Athens, Greece
pp. 54

Design Flow for HW / SW Acceleration Transparency in the ThumbPod Secure Embedded System (Abstract)

Yi Fan , UCLA Electrical Engineering Department
David Hwang , UCLA Electrical Engineering Department
Bo-Cheng Lai , UCLA Electrical Engineering Department
Alireza Hodjat , UCLA Electrical Engineering Department
Patrick Schaumont , UCLA Electrical Engineering Department
Ingrid Verbauwhede , UCLA Electrical Engineering Department
Shenglin Yang , UCLA Electrical Engineering Department
Kazuo Sakiyama , UCLA Electrical Engineering Department
pp. 60

Design Techniques for Sensor Appliances: Foundations and Light Compass Case Study (Abstract)

Jennifer L. Wong , University of California, Los Angeles
Seapahn Megerian , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 66
SESSION 6: Special Session - Emerging Design and Tool Challenges in RF and Wireless Applications

RF Front End Application and Technology Trends (Abstract)

Pieter W. Hooijmans , Philips Research Laboratories, The Netherlands
pp. 73

4G Terminals: How are We Going to Design Them? (Abstract)

St?phane Donnay , IMEC, Leuven, Belgium
Jan Craninckx , IMEC, Leuven, Belgium
pp. 79

New Techniques for Non-Linear Behavioral Modeling of Microwave/RF ICs from Simulation and Nonlinear Microwave Measurements (Abstract)

Nick Tufillaro , Agilent Laboratories, Palo Alt, CA
David E. Root , Agilent Technologies, Santa Rosa, CA
John Wood , Agilent Technologies, Santa Rosa, CA
pp. 85
SESSION 7: Panel - COT-Customer Owned Trouble
SESSION 8: Power Grid Analysis and Optimization

Random Walks in a Supply Network (Abstract)

Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Sani R. Nassif , IBM Austin Research Labs, Austin, TX
Haifeng Qian , University of Minnesota, Minneapolis
pp. 93

A Static Pattern-Independent Technique for Power Grid Voltage Integrity Verification (Abstract)

Farid N. Najm , University of Toronto, Ontario, Canada
Dionysios Kouroussis , University of Toronto, Ontario, Canada
pp. 99

Power Network Analysis Using an Adaptive Algebraic Multigrid Approach (Abstract)

Zhengyong Zhu , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
Bo Yao , University of California, San Diego
pp. 105

Power Grid Reduction Based on Algebraic Multigrid Principles (Abstract)

Haihua Su , IBM Austin Research Lab, Austin, TX
Emrah Acar , IBM Austin Research Lab, Austin, TX
Sani R. Nassif , IBM Austin Research Lab, Austin, TX
pp. 109

On-chip Power Supply Network Optimization using Multigrid-based Technique (Abstract)

Kai Wang , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 113
SESSION 9: Low-Power Embedded System Design

Scalable Modeling and Optimization of Mode Transitions Based on Decoupled Power Management Architecture (Abstract)

Pai H. Chou , University of California, Irvine
Dexin Li , University of California, Irvine
Qiang Xie , University of California, Irvine
pp. 119

Optimal Voltage Allocation Techniques for Dynamically Variable Voltage Processors (Abstract)

Woo-Cheol Kwon , Samsung Electronics Co., Ltd., Kyounggi-Do, Korea
Taewhan Kim , Korea Advanced Institute of Science & Technology, Korea
pp. 125

Energy Reduction Techniques for Multimedia Applications with Tolerance to Deadline Misses (Abstract)

Shaoxiong Hua , University of Maryland, College Park
Shuvra S. Bhattacharyya , University of Maryland, College Park
Gang Qu , University of Maryland, College Park
pp. 131

Xtream-Fit: An Energy-Delay Efficient Data Memory Subsystem for Embedded Media Processing (Abstract)

Anand Ramachandran , The University of Texas at Austin
Margarida F. Jacome , The University of Texas at Austin
pp. 137
SESSION 10: Cyclic and Non-Cyclic Combinational Circuit Synthesis

A New Enhanced Constructive Decomposition and Mapping Algorithm (Abstract)

Timothy Kam , Intel Corporation, Hillsboro, OR
Alan Mishchenko , University of California, Berkeley
Xinning Wang , Intel Corporation, Hillsboro, OR
pp. 143

Large-Scale SOP Minimization Using Decomposition and Functional Properties (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology, Japan
Alan Mishchenko , University of California, Berkeley
pp. 149

Generalized Cofactoring for Logic Function Evaluation (Abstract)

Yunjian Jiang , University of California, Berkeley
Robert K. Brayton , University of California, Berkeley
Slobodan Matic , University of California, Berkeley
pp. 155

Making Cyclic Circuits Acyclic (Abstract)

Stephen A. Edwards , Columbia University, New York, NY
pp. 159

The Synthesis of Cyclic Combinational Circuits (Abstract)

Jehoshua Bruck , California Institute of Technology
Marc D. Riedel , California Institute of Technology
pp. 163
SESSION 11: Managing Leakage Power

Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling (Abstract)

Saibal Mukhopadhyay , Purdue University, West Lafayette, IN
Arijit Raychowdhury , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 169

Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage (Abstract)

Dennis Sylvester , University of Michigan, Ann Arbor, MI
Dongwoo Lee , University of Michigan, Ann Arbor, MI
David Blaauw , University of Michigan, Ann Arbor, MI
Wesley Kwong , University of Michigan, Ann Arbor, MI
pp. 175

Distributed Sleep Transistor Network for Power Reduction (Abstract)

Lei He , UCLA
Changbo Long , University of Wisconsin, Madison
pp. 181

Implications of Technology Scaling on Leakage Reduction Techniques (Abstract)

Y-F. Tsai , Penn State University
N. Vijaykrishnan , Penn State University
M. J. Irwin , Penn State University
D. Duarte , LTD, Intel Corporation
pp. 187

Static Leakage Reduction through Simultaneous Threshold Voltage and State Assignment (Abstract)

David Blaauw , University of Michigan, Ann Arbor, MI
Dongwoo Lee , University of Michigan, Ann Arbor, MI
pp. 191
SESSION 12: Panel - Emerging Markets: Design Goes Global
SESSION 13: Timing-Oriented Placement

Timing Optimization of FPGA Placements by Logic Replication (Abstract)

John Lillis , University of Illinois at Chicago
Giancarlo Beraudo , University of Illinois at Chicago
pp. 196

Delay Budgeting in Sequential Circuit with Application on FPGA Placement (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara
Chao-Yang Yeh , University of California, Santa Barbara
pp. 202

Multilevel Global Placement with Retiming (Abstract)

Jason Cong , University of California, Los Angeles
Xin Yuan , University of California, Los Angeles
pp. 208

Force Directed Mongrel with Physical Net Constraints (Abstract)

Vladimir Tiourin , Intel Corporation
Karthik Rajagopal , Intel Corporation
Bill Halpin , Syracuse Univ. and Intel Corporation
Amit Chowdhary , Intel Corporation
Sung-Woo Hur , Donga University
Yegna Parasuram , Intel Corporation
Tung Cao , Intel Corporation
pp. 214
SESSION 14: Model Order Reduction

Realizable Parasitic Reduction Using Generalized Y-Δ Transformation (Abstract)

Zhanhai Qin , Synopsys, Incorporation
Chung-Kuan Cheng , Univ. of California, San Diego
pp. 220

Realizable RLCK Circuit Crunching (Abstract)

Yehea I. Ismail , Northwestern Univ., Evanston, IL
Chirayu S. Amin , Northwestern Univ., Evanston, IL
Masud H. Chowdhury , Northwestern Univ., Evanston, IL
pp. 226

Efficient Model Order Reduction Including Skin Effect (Abstract)

Shizhong Mei , Northwestern University, Evanston, IL
Yehea I. Ismail , Northwestern University, Evanston, IL
Chirayu Amin , Northwestern University, Evanston, IL
pp. 232

Model Order Reduction of Nonuniform Transmission Lines Using Integrated Congruence Transform (Abstract)

Michel Nakhla , Carleton University, Ontario, Canada
Emad Gad , Carleton University, Ontario, Canada
pp. 238
SESSION 15: Issues in Partitioning & Design Space Exploration for Codesign

Dynamic Hardware/Software Partitioning: A First Approach (Abstract)

Roman Lysecky , University of California, Riverside
Frank Vahid , UC Irvine; University of California, Riverside
Greg Stitt , University of California, Riverside
pp. 250

Automatic Application-Specific Instruction-Set Extensions under Microarchitectural Constraints (Abstract)

Laura Pozzi , Swiss Federal Institute of Technology Lausanne (EPFL), Lausanne, Switzerland
Kubilay Atasu , Swiss Federal Institute of Technology Lausanne (EPFL), Lausanne, Switzerland
Paolo Ienne , Swiss Federal Institute of Technology Lausanne (EPFL), Lausanne, Switzerland
pp. 256

Instruction Encoding Synthesis for Architecture Exploration using Hierarchical Processor Models (Abstract)

Achim Nohl , CoWare, Inc., San Jose, CA
Heinrich Meyr , Aachen University of Technology (RWTH), Aachen, Germany
Oliver Schliebusch , Aachen University of Technology (RWTH), Aachen, Germany
Rainer Leupers , Aachen University of Technology (RWTH), Aachen, Germany
Andreas Hoffmann , CoWare, Inc., San Jose, CA
Gunnar Braun , CoWare, Inc., San Jose, CA
Volker Greive , CoWare, Inc., San Jose, CA
pp. 262
SESSION 16: Special Session - Nano Technology: Design Implications and CAD Challenges

Manipulation and Characterization of Molecular Scale Components (PDF)

Islamshah Amlani , Motorola Labs, Tempe, AZ
John Tresek , Motorola Labs, Tempe, AZ
Raymond K. Tsui , Motorola Labs, Tempe, AZ
Ruth Zhang , Motorola Labs, Tempe, AZ
Larry Nagahara , Motorola Labs, Tempe, AZ
pp. 276
SESSION 17: Panel - Mixed Signals on Mixed-Signal: the Right Next Technology
SESSION 18: Simulation Coverage and Generation for Verification

Coverage-Oriented Verification of Banias (Abstract)

Alon Gluska , Intel Israel, Haifa
pp. 280

Coverage Directed Test Generation for Functional Verification using Bayesian Networks (Abstract)

Avi Ziv , IBM Research Laboratory in Haifa, Israel
Shai Fine , IBM Research Laboratory in Haifa, Israel
pp. 286

Dos and Don'ts of CTL State Coverage Estimation (Abstract)

Mitra Purandare , University of Colorado at Boulder
Nikhil Jayakumar , University of Colorado at Boulder
Fabio Somenzi , University of Colorado at Boulder
pp. 292

Constraint Synthesis for Environment Modeling in Functional Verification (Abstract)

Adnan Aziz , University of Texas at Austin
Ken Albin , Motorola Inc., Austin, TX
Carl Pixley , Synopsys, Hillsboro, OR
Jun Yuan , Motorola Inc., Austin, TX
pp. 296
SESSION 19: Tool Support for Architectural Decisions in Embedded Systems

Automatic Communication Refinement for System Level Design (Abstract)

Daniel Gajski , University of California Irvine
Samar Abdi , University of California Irvine
Dongwan Shin , University of California Irvine
pp. 300

CoCo: A Hardware/Software Platform for Rapid Prototyping of Code Compression Technologies (Abstract)

J? Henkel , NEC Labs America, Princeton, New Jersey
Haris Lekatsas , NEC Labs America, Princeton, New Jersey; Vorras Corporation, Princeton, New Jersey
Venkata Jakkula , NEC Labs America, Princeton, New Jersey
Murugan Sankaradass , NEC Labs America, Princeton, New Jersey
Srimat Chakradhar , NEC Labs America, Princeton, New Jersey
pp. 306
SESSION 20: New Topics in Logic Synthesis

A Transformation Based Algorithm for Reversible Logic Synthesis (Abstract)

Gerhard W. Dueck , University of New Brunswick, Canada
Dmitri Maslov , University of New Brunswick, Canada
D. Michael Miller , University of Victoria, Canada
pp. 318

An Arbitrary Two-qubit Computation In 23 Elementary Gates Or Less (Abstract)

Igor L. Markov , The University of Michigan, Ann Arbor
Stephen S. Bullock , The University of Michigan, Ann Arbor
pp. 324

On-Chip Logic Minimization (Abstract)

Frank Vahid , University of California, Riverside
Roman Lysecky , University of California, Riverside
pp. 334
SESSION 21: Special Session - Coping with Variability: The End of Deterministic Design

Parameter Variations and Impact on Circuits and Microarchitecture (Abstract)

Vivek De , Circuit Research, Intel Labs, Hillsboro, OR
Ali Keshavarzi , Circuit Research, Intel Labs, Hillsboro, OR
Tanay Karnik , Circuit Research, Intel Labs, Hillsboro, OR
Jim Tschanz , Circuit Research, Intel Labs, Hillsboro, OR
Shekhar Borkar , Circuit Research, Intel Labs, Hillsboro, OR
Siva Narendra , Circuit Research, Intel Labs, Hillsboro, OR
pp. 338

Death, Taxes and Failing Chips (Abstract)

Chandu Visweswariah , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 343

Computation and Refinement of Statistical Bounds on Circuit Delay (Abstract)

Vladimir Zolotov , Motorola, Inc., Austin, TX
Sarma Vrudhula , University of Arizona, Tucson, AZ
Aseem Agarwal , University of Michigan, Ann Arbor, MI
David Blaauw , University of Michigan, Ann Arbor, MI
pp. 348
SESSION 22: Panel - Fast, Cheap and Under Control: The Next Implementation Fabric
SESSION 23: Testbench, Verification and Debugging: Practical Considerations

Using a Formal Specification and a Model Checker to Monitor and Direct Simulation (Abstract)

Serdar Tasiran , Ko? University, Istanbul, Turkey
Brannon Batson , Intel Corporation, Santa Clara, CA
Yuan Yu , Microsoft Research, Mountain View, CA
pp. 356

Advanced Techniques for RTL Debugging (Abstract)

Furshing Tsai , Novas Software Inc., San Jose, CA
Yirng-An Chen , Novas Software Inc., San Jose, CA
Bassam Tabbara , Novas Software Inc., San Jose, CA
Yu-Chin Hsu , Novas Software Inc., San Jose, CA
pp. 362

Behavioral Consistency of C and Verilog Programs Using Bounded Model Checking (Abstract)

Daniel Kroening , Carnegie Mellon University, Pittsburgh, PA
Karen Yorav , Carnegie Mellon University, Pittsburgh, PA
Edmund Clarke , Carnegie Mellon University, Pittsburgh, PA
pp. 368

Re-Use-Centric Architecture for a Fully Accelerated Testbench Environment (Abstract)

Martin Zambaldi , Infineon Technologies AG, Munich, Germany
Andreas Zinn , Infineon Technologies AG, Munich, Germany
Matthias Bauer , Infineon Technologies AG, Munich, Germany
Wolfgang Ecker , Infineon Technologies AG, Munich, Germany
Renate Henftling , Infineon Technologies AG, Munich, Germany
pp. 372
SESSION 24: Delay and Noise Modeling in the Nanometer Regime

An Effective Capacitance Based Driver Output Model for On-Chip RLC Interconnects (Abstract)

Dennis Sylvester , University of Michigan
David Blaauw , University of Michigan
Kanak Agarwal , University of Michigan
pp. 376

Delay and Slew Metrics Using the Lognormal Distribution (Abstract)

Chandramouli Kashyap , IBM Corp., Austin, Texas
Anirudh Devgan , IBM Corp., Austin, Texas
Charles J. Alpert , IBM Corp., Austin, Texas
Frank Liu , IBM Corp., Austin, Texas
pp. 382

Blade and Razor: Cell and Interconnect Delay Analysis Using Current-Based Models (Abstract)

D. F. Wong , University of Illinois at Urbana-Champaign
John F. Croix , Silicon Metrics Corporation, Austin, Texas
pp. 386

Non-Iterative Switching Window Computation for Delay-Noise (Abstract)

David Blaauw , University of Michigan, Ann Arbor, MI
Bhavana Thudi , University of Michigan, Ann Arbor, MI
pp. 390
SESSION 25: Modeling Issues in the Design of Embedded Systems

Architecture-Level Performance Evaluation of Component-Based Embedded Systems (Abstract)

Jeffry T Russell , University of Texas at Austin
Margarida F Jacome , University of Texas at Austin
pp. 396

An IDF-based Trace Transformation Method for Communication Refinement (Abstract)

Cagkan Erbas , University of Amsterdam, The Netherlands
Andy D. Pimentel , University of Amsterdam, The Netherlands
pp. 402

Schedulers as Model-Based Design Elements in Programmable Heterogeneous Multiprocessors (Abstract)

Jeffrey E. Nelson , Carnegie Mellon University, Pittsburgh, PA
Alex Bobrek , Carnegie Mellon University, Pittsburgh, PA
JoAnn M. Paul , Carnegie Mellon University, Pittsburgh, PA
Joshua J. Pieper , Carnegie Mellon University, Pittsburgh, PA
Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
pp. 408

A Complexity Effective Communication Model for Behavioral Modeling of Signal Processing Applications (Abstract)

M.N. Jayram , Philips Research, Eindhoven, Netherlands
Satya Kiran , Indian Institute of Technology Delhi
S. K. Nandy , Indian Institute of Science, Bangalore, India
Pradeep Rao , Indian Institute of Science, Bangalore, India
pp. 412
SESSION 26: Special Session - How Application/Technology Evolutions Will Shape Classical EDA?

System-on-Chip Beyond the Nanometer Wall (Abstract)

Philippe Magarshack , Central R&D, STMicroelectronics, France
Pierre G. Paulin , Central R&D, STMicroelectronics, France
pp. 419
SESSION 27: SAT and BDD Algorithms for Verification Tools

A Hybrid SAT-Based Decision Procedure for Separation Logic with Uninterpreted Functions (Abstract)

Shuvendu K. Lahiri , Carnegie Mellon University, Pittsburgh, PA
Sanjit A. Seshia , Carnegie Mellon University, Pittsburgh, PA
Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
pp. 425

Symbolic Representation with Ordered Function Templates (Abstract)

Gagan Hasteer , Innologic Systems, San Jose, CA
Amit Goel , Carnegie Mellon University, Pittsburgh, PA
Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
pp. 431

A Signal Correlation Guided ATPG Solver And Its Applications For Solving Difficult Industrial Cases (Abstract)

K.-T. (Tim) Cheng , University of California at Santa Barbara
Ziyad Hanna , INTEL Corporation
Feng Lu , University of California at Santa Barbara
John Moondanos , INTEL Corporation
Li-C. Wang , University of California at Santa Barbara
pp. 436

Solving the Latch Mapping Problem in an Industrial Setting (Abstract)

Rajarshi Mukherjee , Fujitsu Laboratories of America, Sunnyvale, CA
Mukul R Prasad , Fujitsu Laboratories of America, Sunnyvale, CA
Kelvin Ng , University of British Columbia, Vancouver, BC
Jawahar Jain , Fujitsu Laboratories of America, Sunnyvale, CA
pp. 442
SESSION 28: Elements of Functional and Performance Analysis

Static Analysis of Transaction-Level Models (Abstract)

Giovanni Agosta , Politecnico di Milano Italy
Francesco Bruschi , Politecnico di Milano Italy
Donatella Sciuto , Politecnico di Milano Italy
pp. 448

Enabling Scheduling Analysis of Heterogeneous Systems with Multi-Rate Data Dependencies and Rate Intervals (Abstract)

Rolf Ernst , Technical University of Braunschweig, Germany
Marek Jersak , Technical University of Braunschweig, Germany
pp. 454

Automatic Trace Analysis for Logic of Constraints (Abstract)

Felice Balarin , Cadence Berkeley Laboratories, Berkeley, CA
Harry Hsieh , University of California at Riverside
Yosinori Watanabe , Cadence Berkeley Laboratories, Berkeley, CA
Xi Chen , University of California at Riverside
pp. 460

Accurate Timing Analysis by Modeling Caches, Speculation and their Interaction (Abstract)

Xianfeng Li , National University of Singapore
Abhik Roychoudhury , National University of Singapore
Tulika Mitra , National University of Singapore
pp. 466
SESSION 29: Nonlinear Model Order Reduction

NORM: Compact Model Order Reduction of Weakly Nonlinear Systems (Abstract)

Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, Pennsylvania
Peng Li , Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 472

Analog and RF Circuit Macromodels for System-Level Analysis (Abstract)

Peng Li , Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Xin Li , Carnegie Mellon University, Pittsburgh, PA
Yang Xu , Carnegie Mellon University, Pittsburgh, PA
pp. 478

Piecewise Polynomial Nonlinear Model Reduction (Abstract)

Ning Dong , University of Minnesota
Jaijeet Roychowdhury , University of Minnesota
pp. 484

A TBR-based Trajectory Piecewise-Linear Algorithm for Generating Accurate Low-order Models for Nonlinear Analog Circuits and MEMS (Abstract)

Michal Rewienski , Massachusetts Institute of Technology, Cambridge
Dmitry Vasilyev , Massachusetts Institute of Technology, Cambridge
Jacob White , Massachusetts Institute of Technology, Cambridge
pp. 490
SESSION 30: Novel Techniques in High-Level Synthesis

Toward Efficient Static Analysis of Finite-Precision Effects in DSP Applications via Affine Arithmetic Modeling (Abstract)

Markus P?schel , Carnegie Mellon University
Tsuhan Chen , Carnegie Mellon University
Claire Fang Fang , Carnegie Mellon University
Rob A. Rutenbar , Carnegie Mellon University
pp. 496

Automating the Design of an Asynchronous DLX Microprocessor (Abstract)

Ivan Blunno , Politecnico di Torino, Torino, Italy
Christos P. Sotiriou , FORTH, Heraklion, Greece
Manish Amde , Indian Institute of Technology, Bombay, India
pp. 502

High-Level Synthesis of Asynchronous Systems by Data-Driven Decomposition (Abstract)

Catherine G. Wong , California Institute of Technology, Pasadena
Alain J. Martin , California Institute of Technology, Pasadena
pp. 508

Using Estimates from Behavioral Synthesis Tools in Compiler-Directed Design Space Exploration (Abstract)

Pedro C. Diniz , University of Southern California / Information Sciences Institute, Marina del Rey, California
Byoungro So , University of Southern California / Information Sciences Institute, Marina del Rey, California
Mary W. Hall , University of Southern California / Information Sciences Institute, Marina del Rey, California
pp. 514
SESSION 31: Mixed-Signal Design and Simulation

A 16-Bit Mixed-Signal Microsystem with Integrated CMOS-MEMS Clock Reference (Abstract)

Eric D. Marsman , University of Michigan, Ann Arbor, Michigan
Richard B. Brown , University of Michigan, Ann Arbor, Michigan
Matthew R. Guthaus , University of Michigan, Ann Arbor, Michigan
Keith L. Kraver , University of Michigan, Ann Arbor, Michigan
Robert M. Senger , University of Michigan, Ann Arbor, Michigan
Fadi H. Gebara , University of Michigan, Ann Arbor, Michigan
Michael S. McCorquodale , University of Michigan, Ann Arbor, Michigan
pp. 520

Computation of Noise Spectral Density in Switched Capacitor Circuits using the Mixed-Frequency-Time Technique (Abstract)

M. Ramakrishna , Indian Institute of Technology-Madras
V. Vasudevan , Indian Institute of Technology-Madras
pp. 538

Symbolic Analysis of Analog Circuits with Hard Nonlinearity (Abstract)

C.-J. Richard Shi , University of Washington, Seattle
Alicia Manthe , University of Washington, Seattle
Zhao Li , University of Washington, Seattle
pp. 542
SESSION 32: Panel - Nanometer Design: Place Your Bets
SESSION 33: Novel Self-Test Methods

A Scalable Software-Based Self-Test Methodology for Programmable Processors (Abstract)

Srivaths Ravi , NEC Laboratories America, Inc., Princeton, NJ
Anand Raghunathan , NEC Laboratories America, Inc., Princeton, NJ
Li Chen , University of California at San Diego
Sujit Dey , University of California at San Diego
pp. 548

A Scan BIST Generation Method Using A Markov Source And Partial Bit-Fixing (Abstract)

Sudhakar M. Reddy , Univ. of Iowa, Iowa City
Chaowen Yu , Univ. of Iowa, Iowa City
Wei Li , Univ. of Iowa, Iowa City
Irith Pomeranz , Purdue University, West Lafayette, IN
pp. 554

Seed Encoding with LFSRs and Cellular Automata (Abstract)

Ahmad A. Al-Yamani , Stanford University, CA
Edward J. McCluskey , Stanford University, CA
pp. 560

Efficient Compression and Application of Deterministic Patterns in a Logic BIST Architecture (Abstract)

Sanjay Patel , Synopsys Inc., Beaverton, OR
Peter Wohl , Synopsys Inc., Williston, VT
Minesh B. Amin , Synopsys Inc., Mountain View, CA
John A. Waicukauski , Synopsys Inc., Tualatin, OR
pp. 566

Ultimate Low Cost Analog BIST (Abstract)

Luigi Carro , Universidade Federal do Rio Grande do Sul - PPGC, Porto Alegre, RS, Brazil
Altamiro Amadeu Susin , Universidade Federal do Rio Grande do Sul - PPGC, Porto Alegre, RS, Brazil
Marcelo Negreiros , Universidade Federal do Rio Grande do Sul - PPGC, Porto Alegre, RS, Brazil
pp. 570
SESSION 34: Technology Mapping, Buffering, and Bus Design

Gain-Based Technology Mapping for Discrete-Size Cell Libraries (Abstract)

Yosinori Watanabe , Cadence Berkeley Labs, CA
Alex Kondratyev , Cadence Berkeley Labs, CA
Bo Hu , Univ. of CA, Santa Barbara
Malgorzata Marek-Sadowska , Univ. of CA, Santa Barbara
pp. 574

An O(nlogn) Time Algorithm for Optimal Buffer Insertion (Abstract)

Zhuo Li , Texas A&M University, College Station, TX
Weiping Shi , Texas A&M University, College Station, TX
pp. 580

Optimum Positioning of Interleaved Repeaters in Bidirectional Buses (Abstract)

Yehea Ismail , Northwestern University
Maged Ghoneima , Northwestern University
pp. 586

Synthesizing Optimal Filters for Crosstalk-cancellation for High-Speed Buses (Abstract)

Mark Greenstreet , University of British Columbia
Jihong Ren , University of British Columbia
pp. 592
SESSION 35: Compilation Techniques for Reconfigurable Devices

Fast Timing-driven Partitioning-based Placement for Island Style FPGAs (Abstract)

Kia Bazargan , University of Minnesota, Minneapolis
Pongstorn Maidee , University of Minnesota, Minneapolis
Cristinel Ababei , University of Minnesota, Minneapolis
pp. 598

Compiler-Generated Communication for Pipelined FPGA Applications (Abstract)

Heidi E. Ziegler , University of Southern California / Information Sciences Institute, Marina del Rey, CA
Pedro C. Diniz , University of Southern California / Information Sciences Institute, Marina del Rey, CA
Mary W. Hall , University of Southern California / Information Sciences Institute, Marina del Rey, CA
pp. 610

Data Communication Estimation and Reduction for Reconfigurable Systems (Abstract)

Adam Kaplan , University of California, Los Angeles
Ryan Kastner , University of California, Santa Barbara
Philip Brisk , University of California, Los Angeles
pp. 616
SESSION 36: Architectural Power Estimation and Optimization

Clock-Tree Power Optimization based on RTL Clock-Gating (Abstract)

Enrico Macii , Politecnico di Torino, Italy
Monica Donno , BullDAST s.r.l., Torino, Italy
Alessandro Ivaldi , Politecnico di Torino, Italy
Luca Benini , Universit? di Bologna, Italy
pp. 622

Low-Power Design Methodology for an On-chip Bus with Adaptive Bandwidth Capability (Abstract)

Ralph K. Cavin , Research Triangle Park, NC
Wentai Liu , University of California, Santa Cruz
Rizwan Bashirullah , North Carolina State University, Raleigh, NC
pp. 628

Power-Aware Issue Queue Design for Speculative Instructions (Abstract)

Tali Moreshet , Brown University, Providence, RI
R. Iris Bahar , Brown University, Providence, RI
pp. 634

State-Based Power Analysis for Systems-on-Chip (Abstract)

Reinaldo A. Bergamaschi , IBM T. J. Watson Research Center Yorktown, Heights, NY
Yunjian W. Jiang , University of California, Berkeley
pp. 638
SESSION 37: Panel - Libraries: Lifejacket or Straitjacket
SESSION 38: Techniques for Reconfigurable Logic Applications

Switch-Level Emulation (Abstract)

Seyed Ghassem Miremadi , Sharif University of technology, Tehran, Iran
Alireza Ejlali , Sharif University of technology, Tehran, Iran
pp. 644

Designing Fault Tolerant Systems into SRAM-based FPGAs (Abstract)

Ricardo Reis , Universidade Federal do Rio Grande do Sul
Fernanda Lima , Universidade Federal do Rio Grande do Sul
Luigi Carro , Universidade Federal do Rio Grande do Sul
pp. 650

Determining Appropriate Precisions for Signals in Fixed-Point IIR Filters (Abstract)

Joan Carletta , The University of Akron, OH
Robert Veillette , The University of Akron, OH
Zhengwei Fang , The University of Akron, OH
Frederick Krach , The University of Akron, OH
pp. 656
SESSION 39: Test and Diagnosis for Complex Designs

Test Generation for Designs with Multiple Clocks (Abstract)

Xijiang Lin , Mentor Graphics Corp., Wilsonville, OR
Rob Thompson , Mentor Graphics Corp., Wilsonville, OR
pp. 662

Enhancing Diagnosis Resolution For Delay Defects Based Upon Statistical Timing and Statistical Fault Models (Abstract)

L.-C. Wang , University of California, Santa Barbara
T. M. Mak , Intel Corporation, Santa Clara, CA
K.-T. Cheng , University of California, Santa Barbara
J.-J. Liou , Tsing-Hua University, Taiwan
A. Krstic , University of California, Santa Barbara
pp. 668

Using Embedded Infrastructure IP for SOC Post-Silicon Verification (Abstract)

Yu Huang , Mentor Graphics Co., Waltham, MA
Wu-Tung Cheng , Mentor Graphics Co., Wilsonville, OR
pp. 674
SESSION 40: Special Session - Highlights of ISSCC: High-Speed Heterogenous Design Techniques

Design of a 10GHz Clock Distribution Network Using Coupled Standing-Wave Oscillators (Abstract)

Mark A. Horowitz , Stanford University, CA
C. Patrick Yue , Aeluros, Inc., Mountain View, CA
Frank O'Mahony , Stanford University, CA
S. Simon Wong , Stanford University, CA
pp. 682

Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL (Abstract)

Manjusha Shankaradas , Texas Instruments Incorporated, Dallas, TX
John G. Maneatis , True Circuits, Inc., Los Altos, CA
Jaeha Kim , True Circuits, Inc., Los Altos, CA
Iain McClatchie , True Circuits, Inc., Los Altos, CA
Jay Maxey , Texas Instruments Incorporated, Dallas, TX
pp. 688

A Reconfigurable Signal Processing IC with embedded FPGA and Multi-Port Flash Memory (Abstract)

F. Lertora , STMicroelectronics, Central R&D, Agrate Brianza, Italy
L. Cal? , STMicroelectronics, Central R&D, Agrate Brianza, Italy
G. Muzzi , STMicroelectronics, Central R&D, Agrate Brianza, Italy
P. L. Rolandi , STMicroelectronics, Central R&D, Agrate Brianza, Italy
M. Poles , STMicroelectronics, Central R&D, Agrate Brianza, Italy
M. Pasotti , STMicroelectronics, Central R&D, Agrate Brianza, Italy
B. For? , STMicroelectronics, Central R&D, Agrate Brianza, Italy
D. Iezzi , STMicroelectronics, Central R&D, Agrate Brianza, Italy
G. De Sandre , STMicroelectronics, Central R&D, Agrate Brianza, Italy
M. Borgatti , STMicroelectronics, Central R&D, Agrate Brianza, Italy
pp. 691
SESSION 41: Special Session - Highlights of ISSCC and The Design of State-of-the-Art Microprocessors

Physical Synthesis Methodology for High Performance Microprocessors (Abstract)

Prabhakar Kudva , IBM TJ Watson Research Center, Yorktown Heights, NY
Greg Northrop , IBM TJ Watson Research Center, Yorktown Heights, NY
Yiu-Hing Chan , IBM Server Group, Poughkeepsie, NY
Thomas Rosser , IBM Server Group, Austin, TX
Lisa Lacey , IBM TJ Watson Research Center, Yorktown Heights, NY
pp. 696

A 1.3GHz Fifth Generation SPARC64 Microprocessor (Abstract)

Ryouichi Yamashita , Fujitsu Ltd. Kawasaki, Japan
Hiroyuki Sugiyama , Fujitsu Ltd. Kawasaki, Japan
Takeo Asakawa , Fujitsu Ltd. Kawasaki, Japan
Seishi Okada , Fujitsu Ltd. Kawasaki, Japan
Hisashige Ando , Fujitsu Ltd. Kawasaki, Japan
Hideo Yamashita , Fujitsu Ltd. Kawasaki, Japan
Aiichiro Inoue , Fujitsu Ltd. Kawasaki, Japan
Yuuji Yoshida , Fujitsu Ltd. Kawasaki, Japan
Itsumi Sugiyama , Fujitsu Ltd. Kawasaki, Japan
Tsuyoshi Motokurumada , Fujitsu Ltd. Kawasaki, Japan
Yoshihiko Satsukawa , Fujitsu Ltd. Kawasaki, Japan
Kuniki Morita , Fujitsu Ltd. Kawasaki, Japan
Akihiko Konmoto , Fujitsu Ltd. Kawasaki, Japan
Toshiyuki Muta , Fujitsu Ltd. Kawasaki, Japan
pp. 702

A 1.5GHz Third Generation Itanium? 2 Processor (Abstract)

Stefan Rusu , Intel Corporation, Santa Clara, CA
Jason Stinson , Intel Corporation, Santa Clara, CA
pp. 706
SESSION 42: Panel - Formal Verification - Prove It or Pitch It
SESSION 43: High Frequency Interconnect Modeling

Algorithms in FastImp: A Fast and Wideband Impedance Extraction Program For Complicated 3-D Geometries (Abstract)

Zhenhai Zhu , Massachusetts Institute of Technology, Cambridge
Jacob White , Massachusetts Institute of Technology, Cambridge
Ben Song , Massachusetts Institute of Technology, Cambridge
pp. 712

On-chip Interconnect-Aware Design and Modeling Methodology, Based on High Bandwidth Transmission Line Devices (Abstract)

D. Harame , IBM Design Automation Dept., Burlington
R. Groves , IBM SiGe Model Development, East Fishkill
A. Sherman , IBM Haifa Research and Development Labs, Israel
S. Strang , IBM Design Automation Dept., Burlington
Y. Tretiakov , IBM Design Automation Dept., Burlington
J. Park , IBM SiGe Model Development, East Fishkill
C. Dickey , IBM Design Automation Dept., Burlington
D. Jordan , IBM Design Automation Dept., Burlington
I. A. Wagner , IBM Haifa Research and Development Labs, Israel
R. Gordin , IBM Haifa Research and Development Labs, Israel
A. Barger , IBM Haifa Research and Development Labs, Israel
B. Livshitz , IBM Haifa Research and Development Labs, Israel
D. Goren , IBM Haifa Research and Development Labs, Israel
A. Amir , IBM Haifa Research and Development Labs, Israel
M. Zelikson , IBM Haifa Research and Development Labs, Israel
R. Singh , IBM Design Automation Dept., Burlington
pp. 724

An Adaptive Window-Based Susceptance Extraction and its Efficient Implementation (Abstract)

Guoan Zhong , Purdue University, West Lafayette, IN
Cheng-Kok Koh , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Venkataramanan Balakrishnan , Purdue University, West Lafayette, IN
pp. 728
SESSION 44: Novel Approaches in Test Cost Reduction

Test Cost Reduction for SOCs Using Virtual TAMs and Lagrange Multipliers (Abstract)

Anuja Sehgal , Duke University, Durham, NC
Vikram Iyengar , IBM Microelectronics, Essex Jct, VT
Krishnendu Chakrabarty , Duke University, Durham, NC
Mark D. Krasniewski , Duke University, Durham, NC
pp. 738

A Cost-Effective Scan Architecture for Scan Testing with Non-Scan Test Power and Test Application Cost (Abstract)

Yu-liang Wu , The Chinese Univ. of Hong Kong, Shatin N.T., Hong Kong
Dong Xiang , Tsinghua University, Beijing, China
Shan Gu , Tsinghua University, Beijing, China
Jia-Guang Sun , Tsinghua University, Beijing, China
pp. 744

On Test Data Compression and n-Detection Test Sets (Abstract)

Irith Pomeranz , Purdue University, W. Lafayette, IN
Sudhakar M. Reddy , University of Iowa, Iowa City
pp. 748
SESSION 45: Retargetable Tools for Embedded Software

A Retargetable Micro-architecture Simulator (Abstract)

Jianwen Zhu , University of Toronto, Ontario, Canada
Wai Sum Mong , University of Toronto, Ontario, Canada
pp. 752

Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation (Abstract)

Prabhat Mishra , University of California, Irvine
Mehrdad Reshadi , University of California, Irvine
Nikil Dutt , University of California, Irvine
pp. 758

Automated Synthesis of Efficient Binary Decoders for Retargetable Software Toolkits (Abstract)

Wei Qin , Princeton University, NJ
Sharad Malik , Princeton University, NJ
pp. 764
SESSION 46: Special Session - ASIC Design in Nanometer Era - Dead or Alive?

Designing Mega-ASICs in Nanogate Technologies (Abstract)

David E. Lackey , IBM Microelectronics Division, Essex Junction, VT
Paul S. Zuchowski , IBM Microelectronics Division, Essex Junction, VT
Juergen Koehl , IBM Microelectronics Division, Essex Junction, VT
pp. 770

Architecting ASIC Libraries and Flows in Nanometer Era (Abstract)

Vipul Singhal , Texas Instruments Inc. Dallas Texas
N.V. Arvind , Texas Instruments Inc. Dallas Texas
Anthony Hill , Texas Instruments Inc. Dallas Texas
Clive Bittlestone , Texas Instruments Inc. Dallas Texas
pp. 776

Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off (Abstract)

A. J. Strojwas , Carnegie Mellon University, Pittsburgh, Pennsylvania
H. Schmit , Carnegie Mellon University, Pittsburgh, Pennsylvania
V. Rovner , Carnegie Mellon University, Pittsburgh, Pennsylvania
C. Patel , Carnegie Mellon University, Pittsburgh, Pennsylvania
V. Kheterpal , Carnegie Mellon University, Pittsburgh, Pennsylvania
K. Y. Tong , Carnegie Mellon University, Pittsburgh, Pennsylvania
L. Pileggi , Carnegie Mellon University, Pittsburgh, Pennsylvania
A. Koorapaty , Carnegie Mellon University, Pittsburgh, Pennsylvania
P. Gopalakrishnan , Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 782

Pushing ASIC Performance in a Power Envelope (Abstract)

Sarvesh Kulkarni , University of Michigan, Ann Arbor, MI
Dennis Sylvester , University of Michigan, Ann Arbor, MI
John Cohn , IBM Microelectronics, Essex Jn, VT
Ruchir Puri , IBM Research, Yorktown Hts, NY
Leon Stok , IBM Research, Yorktown Hts, NY
David Pan , IBM Research, Yorktown Hts, NY
Ashish Srivastava , University of Michigan, Ann Arbor, MI
David Kung , IBM Research, Yorktown Hts, NY
pp. 788
SESSION 47: Floorplanning and Placement

An Algebraic Multigrid Solver for Analytical Placement with Layout Based Clustering (Abstract)

Zhengyong Zhu , University of California, San Diego
Peter Suaris , Mentor Graphics Corporation, Wilsonville, OR
Nan-Chi Chou , Mentor Graphics Corporation, San Jose, CA
Andrew B. Kahng , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
Hongyu Chen , University of California, San Diego
Bo Yao , University of California, San Diego
John F. MacDonald , Mentor Graphics Corporation, San Diego, CA
pp. 794

Wire Length Prediction based Clustering and its Application in Placement (Abstract)

Malgorzata Marek-Sadowska , Univ. of California, Santa Barbara
Bo Hu , Univ. of California, Santa Barbara
pp. 800

Dynamic Global Buffer Planning Optimization Based on Detail Block Locating and Congestion Analysis (Abstract)

Xianlong Hong , Tsinghua University, Beijing, China
Yuchun Ma , Tsinghua University, Beijing, China
Song Chen , Tsinghua University, Beijing, China
Yici Cai , Tsinghua University, Beijing, China
Jun Gu , Science & Technology University of Hong Kong
C. K. Cheng , University of California, San Diego
Sheqin Dong , Tsinghua University, Beijing, China
pp. 806

Multilevel Floorplanning/Placement for Large-Scale Modules Using B*-trees (Abstract)

Yao-Wen Chang , National Taiwan University, Taipei, Taiwan
Jer-Ming Hsu , National Center for High-Performance Computing, Hsinchu, Taiwan
Hsun-Cheng Lee , Synopsys Inc., Taipei, Taiwan
Hannah H. Yang , Intel Corporation, Hillsboro, OR
pp. 812
SESSION 48: Advances in SAT

Checking Satisfiability of a Conjunction of BDDs (Abstract)

James Kukula , Synopsys, Inc., Hillsboro, OR
Robert Damiano , Synopsys, Inc., Hillsboro, OR
pp. 818

Learning from BDDs in SAT-based Bounded Model Checking (Abstract)

Malay Ganai , NEC Labs America, Princeton, NJ
Zijiang Yang , NEC Labs America, Princeton, NJ
Pranav Ashar , NEC Labs America, Princeton, NJ
Chao Wang , University of Colorado, Boulder
Aarti Gupta , NEC Labs America, Princeton, NJ
pp. 824

A Fast Pseudo-Boolean Constraint Solver (Abstract)

Donald Chai , University of California at Berkeley
Andreas Kuehlmann , Cadence Berkeley Labs, Berkeley, CA
pp. 830

Shatter: Efficient Symmetry-Breaking for Boolean Satisfiability (Abstract)

Karem A. Sakallah , University of Michigan
Igor L. Markov , University of Michigan
Fadi A. Aloul , University of Michigan
pp. 836

SAT-Based Unbounded Symbolic Model Checking (Abstract)

Hyeong-Ju Kang , KAIST, Korea
In-Cheol Park , KAIST, Korea
pp. 840
SESSION 49: Novel Design Methodologies and Signal Integrity

Design of a 17-million Gate Network Processor using a Design Factory (Abstract)

Gilles-Eric Descamps , Silicon Access Networks Inc., San Jose, CA
Alain Pirson , Silicon Access Networks Inc., San Jose, CA
Satish Iyengar , Silicon Access Networks Inc., San Jose, CA
Subramanian Ganesan , Silicon Access Networks Inc., San Jose, CA
Satish Bagalkotkar , Silicon Access Networks Inc., San Jose, CA
pp. 844

Hybrid Hierarchical Timing Closure Methodology for a High Performance and Low Power DSP (Abstract)

Kaijian Shi , Professional Services, Synopsys Inc., Dallas, TX
Graig Godwin , Texas Instruments, Inc., Dallas, TX
pp. 850

Statistical Estimation of Leakage-Induced Power Grid Voltage Drop Considering Within-Die Process Variations (Abstract)

Farid N. Najm , University of Toronto, Ontario, Canada
Imad A. Ferzli , University of Toronto, Ontario, Canada
pp. 856

Temporofunctional Crosstalk Noise Analysis (Abstract)

Alex Kondratyev , Cadence Berkeley Labs, Berkeley, CA
Kenneth H. Tseng , Cadence Design Systems, San Jose, CA
Yosinori Watanabe , Berkeley, CA 94704
Yajun Ran , University of California, Santa Barbara
Donald Chai , University of California, Berkeley
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 860

Static Noise Analysis with Noise Windows (Abstract)

Ken Tseng , Cadence Design Systems
Vinod Kariat , Cadence Design Systems
pp. 864
SESSION 50: Memory Optimization for Embedded Systems

Embedded Intelligent SRAM (Abstract)

Prabhat Jain , Massachusetts Institute of Technology, Cambridge
Srinivas Devadas , Massachusetts Institute of Technology, Cambridge
G. Edward Suh , Massachusetts Institute of Technology, Cambridge
pp. 869

Improved Indexing for Cache Miss Reduction in Embedded Systems (Abstract)

Tony Givargis , University of California, Irvine
pp. 875

Memory Layout Techniques for Variables Utilizing Efficient DRAM Access Modes in Embedded System Design (Abstract)

Yoonseo Choi , Korea Advanced Institute of Science and Technology, KOREA
Taewhan Kim , Korea Advanced Institute of Science and Technology, KOREA
pp. 881

Interprocedural Optimizations for Improving Data Cache Performance of Array-Intensive Embedded Applications (Abstract)

M. Karakoy , Imperial College, London, UK
M. Kandemir , The Pennsylvania State University, University Park
W. Zhang , The Pennsylvania State University, University Park
G. Chen , The Pennsylvania State University, University Park
pp. 887
SESSION 51: Special Session - Design Automation for Quantum Circuits

Tutorial: Basic Concepts in Quantum Circuits (PDF)

John P. Hayes , University of Michigan, Ann Arbor
pp. 893
SESSION 52: Energy-Aware System Design

A Survey of Techniques for Energy Efficient On-Chip Communication (Abstract)

Vijay Raghunathan , UC Los Angeles, CA
Rajesh K. Gupta , UC San Diego, CA
Mani B. Srivastava , UC Los Angeles, CA
pp. 900

Energy-Aware MPEG-4 FGS Streaming (Abstract)

Massoud Pedram , Univ. of Southern California, Los Angeles
Kwanho Kim , Seoul National University, Korea
Kihwan Choi , Univ. of Southern California, Los Angeles
pp. 912

A Low-Energy Chip-Set for Wireless Intercom (Abstract)

M. Josie Ammer , University of California, Berkeley
Tufan Karalar , University of California, Berkeley
Michael Sheets , University of California, Berkeley
Jan Rabaey , University of California, Berkeley
Mika Kuulusa , University of California, Berkeley
pp. 916
SESSION 53: Budgeting, Simulation and Statistical Timing

Optimal Integer Delay Budgeting on Directed Acyclic Graphs (Abstract)

M. Sarrafzadeh , University of California, Los Angeles (UCLA)
A. Takahashi , Tokyo Institute of Technology, Japan
S. Ghiasi , University of California, Los Angeles (UCLA)
E. Bozorgzadeh , University of California, Los Angeles (UCLA)
pp. 920

Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits (Abstract)

J. A. G. Jess , Eindhoven University of Technology, The Netherlands
K. Kalafala , IBM Microelectronics Division, East Fishkill, NY
R. H. J. M. Otten , Eindhoven University of Technology, The Netherlands
S. R. Naidu , Eindhoven University of Technology, The Netherlands
C. Visweswariah , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 932
SESSION 54: Interconnect Noise Avoidance Methodologies & Slew Rate Prediction

Crosstalk Noise in FPGAs (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara
Yajun Ran , University of California, Santa Barbara
pp. 944

Simple Metrics for Slew Rate of RC Circuits Based on Two Circuit Moments (Abstract)

David Blaauw , University of Michigan
Kanak Agarwal , University of Michigan
Dennis Sylvester , University of Michigan
pp. 950

Post-Route Gate Sizing for Crosstalk Noise Reduction (Abstract)

Chanhee Oh , Motorola Inc.
Vladimir Zolotov , Motorola Inc.
Ilan Algor , Motorola Inc.
David Blaauw , Univ. of Michigan Ann Arbor
Ibrahim N. Hajj , Univ. of Illinois Urbana-Champaign
Rajendran Panda , Motorola Inc.
Murat R. Becer , Motorola Inc.
pp. 954
SESSION 55: Analog Design Space Exploration

Performance Trade-off Analysis of Analog Circuits By Normal-Boundary Intersection (Abstract)

Helmut Graeb , Technical University of Munich, Germany
Guido Stehr , Technical University of Munich, Germany
Kurt Antreich , Technical University of Munich, Germany
pp. 958

Support Vector Machines for Analog Circuit Performance Representation (Abstract)

M. I. Jordan , University of California, Berkeley
A. Sangiovanni-Vincentelli , University of California, Berkeley
F. De Bernardinis , University of California, Berkeley; Universit? di Pisa, Italy
pp. 964

Architectural Selection of A/D Converters (Abstract)

Martin Vogels , Katholieke Universiteit Leuven, Belgium
Georges Gielen , Katholieke Universiteit Leuven, Belgium
pp. 974

Author Index (PDF)

pp. 978
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