The Community for Technology Leaders
Design Automation Conference (2002)
New Orleans, LA
June 10, 2002 to June 14, 2002
ISBN: 1-58113-461-4
TABLE OF CONTENTS

Reviewers (PDF)

pp. xvi
Session 1 - PANEL: Wall Street Evaluates EDA
Session 2 - Web and IP Based Design

IP Delivery for FPGAs Using Applets and JHDL (Abstract)

Michael J. Wirthlin , Brigham Young University, Provo, UT
Brian McMurtrey , Brigham Young University, Provo, UT
pp. 2

Watermarking Integer Linear Programming Solutions (Abstract)

Milenko Drinic , University of California Los Angeles
Miodrag Potkonjak , University of California Los Angeles
Seapahn Megerian , University of California Los Angeles
pp. 8

Model Design Using Hierarchical Web-Based Libraries (Abstract)

Jean-Fran?ois Santucci , University of Corsica
Fabrice Bernardi , University of Corsica
pp. 14

Behavioral Synthesis via Engineering Change (Abstract)

Milenko Drinic , University of California, Los Angeles
Darko Kirovski , Microsoft Research, Redmond, WA
pp. 18
Session 3 - Design Innovations for Embedded Processors

A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation (Abstract)

Gunnar Braun , Integrated Signal Processing Systems, Aachen, Germany
Heinrich Meyr , Integrated Signal Processing Systems, Aachen, Germany
Andreas Hoffmann , LISATek Inc., Menlo Park, CA
Achim Nohl , Integrated Signal Processing Systems, Aachen, Germany
Rainer Leupers , Integrated Signal Processing Systems, Aachen, Germany
Oliver Schliebusch , Integrated Signal Processing Systems, Aachen, Germany
pp. 22

A Fast On-Chip Profiler Memory (Abstract)

Susan Cotterell , University of California, Riverside
Frank Vahid , University of California, Riverside
Roman Lysecky , University of California, Riverside
pp. 28

Design of an One-cycle Decompression Hardware for Performance Increase in Embedded Systems (Abstract)

Haris Lekatsas , NEC USA, Princeton, New Jersey
J? Henkel , NEC USA, Princeton, New Jersey
Venkata Jakkula , NEC USA, Princeton, New Jersey
pp. 34
Session 4 - Passive Model Order Reduction

A Factorization-Based Framework for Passivity-Preserving Model Reduction of RLC Systems (Abstract)

C.-K. Koh , Purdue University, West Lafayette, IN
V. Balakrishnan , Purdue University, West Lafayette, IN
Q. Su , Purdue University, West Lafayette, IN
pp. 40

Model Order Reduction for Strictly Passive and Causal Distributed Systems (Abstract)

Luca Daniel , University of California, Berkeley
Joel Phillips , Cadence Berkeley Labs
pp. 46

Guaranteed Passive Balancing Transformations for Model Order Reduction (Abstract)

Luca Daniel , University of California Berkeley
L. Miguel Silveira , INESC ID - Cadence Euro Labs
Joel Phillips , Cadence Design Systems, San Jose, CA
pp. 52
Session 5 - New Perspectives in Physical Design

Uncertainty-Aware Circuit Optimization (Abstract)

Xiaoliang Bai , UC San Diego, La Jolla
Chandu Visweswariah , IBM T. J. Watson Research Center, Yorktown Heights, NY
Philip N. Strenski , IBM T. J. Watson Research Center, Yorktown Heights, NY
David J. Hathaway , IBM Microelectronics, Essex Junction, VT
pp. 58

Congestion-driven Codesign of Power and Signal Networks (Abstract)

Jiang Hu , IBM Corp., Austin, TX
Sachin S. Sapantnekar , Univ. of Minnesota, Minneapolis
Sani R. Nassif , IBM Corp., Austin, TX
Haihu Su , IBM Corp., Austin, TX
pp. 64

On Metrics for Comparing Routability Estimation Methods for FPGAs (Abstract)

Parivallal Kannan , University of Texas at Dallas
Dinesh Bhatia , University of Texas at Dallas
Shankar Balachandran , University of Texas at Dallas
pp. 70
Session 6 - PANEL: Tools or Users: Which is the Bigger Bottleneck?
Session 7 - Special Session: Life after CMOS: Imminent or Irrelevant?

Life Is CMOS: Why Chase the Life After? (Abstract)

Shekhar Borkar , Intel Corporation, Santa Clara, CA
George Sery , Intel Corporation, Santa Clara, CA
Vivek De , Intel Corporation, Santa Clara, CA
pp. 78

The Next Chip Challenge:Effective Methods for Viable Mixed Technology SoCs (Abstract)

H. Bernhard Pogge , IBM Microelectronics, Hopewell Junction, NY
pp. 84

Few Electron Devices: Towards Hybrid CMOS-SET Integrated Circuits (Abstract)

Jacques Gautier , CEA-DRT - LETI/DTS - CEA/GRE
Santanu Mahapatra , Swiss Federal Institute of Technology Lausanne, Switzerland
Kaustav Banerjee , Stanford University, CA
Michel J. Declercq , Swiss Federal Institute of Technology Lausanne, Switzerland
Adrian M. Ionescu , Swiss Federal Institute of Technology Lausanne, Switzerland
pp. 88

Carbon Nanotube Field-Effect Transistors and Logic Circuits (Abstract)

Ph. Avouris , IBM T. J. Watson Research Center, Yorktown Heights, NY
V. Derycke , IBM T. J. Watson Research Center, Yorktown Heights, NY
J. Appenzeller , IBM T. J. Watson Research Center, Yorktown Heights, NY
R. Martel , IBM T. J. Watson Research Center, Yorktown Heights, NY
S. Wind , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 94
Session 8 - Formal Verification

Efficient State Representation for Symbolic Simulation (Abstract)

Kunle Olukotun , Stanford University, CA
Valeria Bertacco , Stanford University, CA
pp. 99

Handling Special Constructs in Symbolic Simulation (Abstract)

Robert Damiano , Synopsys Inc., Beaverton, OR
James Kukula , Synopsys Inc., Beaverton, OR
Kurt Antreich , Technical University of Munich, Germany
Alfred K?lbl , Technical University of Munich, Germany
pp. 105

A Hybrid Verification Approach : Getting Deep into the Design (Abstract)

Osnat Weissberg , Intel Corporation, Haifa, Israel
Gila Kamhi , Intel Corporation, Haifa, Israel
Scott Hazelhurst , University of the Witwatersrand, Johannesburg, South Africa
Limor Fix , Intel Corporation, Haifa, Israel
pp. 111

Can BDDs compete with SAT solvers on Bounded Model Checking? (Abstract)

Gianpiero Cabodi , Politecnico di Torino, Turin, Italy
Stefano Quer , Politecnico di Torino, Turin, Italy
Paolo Camurati , Politecnico di Torino, Turin, Italy
pp. 117
Session 9 - High Level Specification and Design

RTL C-Based Methodology for Designing and Verifying a Multi-Threaded Processor (Abstract)

Barry Pangrle , Synopsys, Inc.
Luc S?m?ria , Synopsys, Inc.
Daniel Ng , Broadcom, Inc.
Andrew Seawright , O-In Design Automation, Inc.
Renu Mehra , Synopsys, Inc.
pp. 123

High-Level Speci .cation and Automatic Generation of IP Interface Monitors (Abstract)

Alan J. Hu , University of British Columbia
Marcio T. Oliveira , University of British Columbia
pp. 129

Formal Verification of Module Interfaces against Real TIme Specifications (Abstract)

P. P. Chakrabarti , Indian Institute of Technology Kharagpur, India
Pallab Dasgupta , Indian Institute of Technology Kharagpur, India
Arindam Chakrabarti , UC Berkeley
Ansuman Banerjee , Indian Institute of Technology Kharagpur, India
pp. 141
Session 10 - Timing Abstraction

Automated Timing Model Generation (Abstract)

Chris Wolff , Synopsys, Inc., Hillsboro, OR
Qiuyang Wu , Synopsys, Inc., Hillsboro, OR
Loa Mize , Synopsys, Inc., Hillsboro, OR
Subramanyam Sripada , Synopsys, Inc., Hillsboro, OR
Ajay J. Daga , Synopsys, Inc., Hillsboro, OR
pp. 146

Timing Model Extraction of Hierarchical Blocks by Graph Reduction (Abstract)

Krishna P. Belkhale , Cadence Design Systems, San Diego, CA
Cho W. Moon , Cadence Design Systems, San Diego, CA
Harish Kriplani , Cadence Design Systems, San Diego, CA
pp. 152

Efficient Stimulus Independent Timing Abstraction Model Based on a New Concept of Circuit Block Transparency (Abstract)

Sean Tyler , Hewlett Packard Corporation, Fort Collins, CO
Brian Foutz , IBM Test Design Automation, Endicott, NY
Martin Foltin , Hewlett Packard Corporation, Fort Collins, CO
pp. 158
Session 11 - Special Session: E-Textiles

The Wearable Motherboard:A Framework for Personalized Mobile Information Processing (PMIP) (Abstract)

Sungmee Park , Georgia Institute of Technology, Atlanta
Sundaresan Jayaraman , Georgia Institute of Technology, Atlanta
Kenneth Mackenzie , Georgia Institute of Technology, Atlanta
pp. 170

Challenges and Opportunities in Electronic Textiles Modeling and Optimization (Abstract)

Diana Marculescu , Carnegie Mellon University
Radu Marculescu , Carnegie Mellon University
Pradeep K. Khosla , Carnegie Mellon University
pp. 175
Session 12 - PANEL: Analog Intellectual Property: Now? Or Never?
Session 13 - Low-Power System Design

Task Scheduling and Voltage Selection for Energy Minimization (Abstract)

Xiaobo (Sharon) Hu , University of Notre Dame, IN
Danny Z. Chen , University of Notre Dame, IN
Yumin Zhang , Synopsys, Inc., Mountain View, CA
pp. 183

Battery-Conscious Task Sequencing for Portable Devices Including Voltage/Clock Scaling (Abstract)

Chaitali Chakrabarti , Arizona State University, Tempe
Sarma Vrudhula , University of Arizona, Tucson
Daler Rakhmatov , University of Arizona, Tucson
pp. 189

An Energy Saving Strategy Based on Adaptive Loop Parallelization (Abstract)

M. Karakoy , Imperial College, London, UK
M. Kandemir , Pennsylvania State University, University Park
I. Kadayif , Pennsylvania State University, University Park
pp. 195
Session 14 - Fabric-Driven Logic Synthesis

River PLAs: A Regular Circuit Structure (Abstract)

Robert K. Brayton , University of California, Berkeley
Fan Mo , University of California, Berkeley
pp. 201

Layout-Aware Synthesis of Arithmetic Circuits (Abstract)

Taewhan Kim , Korea Advanced Institute of Science and Technology
Junhyung Um , Korea Advanced Institute of Science and Technology
pp. 207
Session 15 - Memory Management and Address Optimization in Embedded Systems

Automatic Data Migration for Reducing Energy Consumption in Multi-Bank Memory Systems (Abstract)

M. Kandemir , Pennsylvania State University, University Park
I. Kolcu , UMIST, Manchester, UK
V. De La Luz , Pennsylvania State University, University Park
pp. 213

Exploiting Shared Scratch Pad Memory Space in Embedded Multiprocessor Systems (Abstract)

A. Choudhary , Northwestern University, Evanston, IL
J. Ramanujam , Louisiana State University, Baton Rouge
Mahmut Kandemir , Pennsylvania State University, University Park
pp. 219

Address Assignment Combined with Scheduling in DSP Code Generation (Abstract)

Yoonseo Choi , Korea Advanced Institute of Science and Technology, KOREA
Taewhan Kim , Korea Advanced Institute of Science and Technology, KOREA
pp. 225
Session 16 - Special Session: Optics: Lighting the Way to EDA Riches?

Computer Aided Design of Long-Haul Optical Transmission Systems (PDF)

Brian E. Brewington , PhotonEx, Maynard, MA
Curtis R. Menyuk , PhotonEx, Maynard, MA
James G. Maloney , PhotonEx, Maynard, MA
pp. 235

A Fast Optical Propagation Technique for Modeling Micro-Optical Systems (Abstract)

Donald M. Chiarulli , University of Pittsburgh, PA
Timothy P. Kurzweg , University of Pittsburgh, PA
Mark Kahrs , University of Pittsburgh, PA
Jose A. Martinez , University of Pittsburgh, PA
Steven P. Levitan , University of Pittsburgh, PA
pp. 236
Session 17 - PANEL: Nanometer Design: What Hurts Next...?
Session 18 - Novel DFT, BIST and Diagnosis Techniques

Low-Cost Sequential ATPG with Clock-Control DFT (Abstract)

Miron Abramovici , Agere Systems - Murray Hill, NJ
Xiaoming Yu , University of Illinois - Urbana, IL
Elizabeth M. Rudnick , University of Illinois - Urbana, IL
pp. 243

Effective Diagnostics through Interval Unloads in a BIST Environment (Abstract)

Sanjay Patel , Synopsys Inc., Beaverton, OR
Peter Wohl , Synopsys Inc., Williston, VT
John A. Waicukauski , Synopsys Inc., Tualatin, OR
Greg Maston , Synopsys Inc., Denver, CO
pp. 249

On Output Response Compression in the Presence of Unknown Output Values (Abstract)

Sandip Kundu , Intel Corp., Austin, TX
Sudhakar M. Reddy , University of Iowa, Iowa City
Irith Pomeranz , Purdue University, W. Lafayette, IN
pp. 255

Software-Based Diagnosis for Processors (Abstract)

Li Chen , University of California at San Diego, La Jolla
Sujit Dey , University of California at San Diego, La Jolla
pp. 259
Session 19 - Case Studies in Embedded System Design

Design of a High-Throughput Low-Power IS95 Viterbi Decoder (Abstract)

Xun Liu , University of Michigan, Ann Arbor
Marios C. Papaefthymiou , University of Michigan, Ann Arbor
pp. 263

A Detailed Cost Model for Concurrent Use With Hardware/Software Co-Design (Abstract)

Peter Sandborn , University of Maryland, College Park
Daniel Ragan , University of Maryland, College Park
Paul Stoaks , Foresight-Systems, Inc., Austin, Texas
pp. 269

Efficient Code Synthesis from Extended Dataflow Graphs for Multimedia Applications (Abstract)

Hyunok Oh , Seoul National University
Soonhoi Ha , Seoul National University
pp. 275
Session 20 - Theoretical Foundations of Embedded System Design

Transformation Based Communication and Clock Domain Refinement for System Design (Abstract)

Axel Jantsch , Royal Institute of Technology, Stockholm, Sweden
Ingo Sander , Royal Institute of Technology, Stockholm, Sweden
pp. 281

Model Composition for Scheduling Analysis in Platform Design (Abstract)

Marek Jersak , Technical University of Braunschweig, Germany
Dirk Ziegenbein , Technical University of Braunschweig, Germany
Rolf Ernst , Technical University of Braunschweig, Germany
Kai Richter , Technical University of Braunschweig, Germany
pp. 287
Session 21 - Equivalence Verification

Automated Equivalence Checking of Switch Level Circuits (Abstract)

Atanas Parashkevov , Motorola Inc., South Australia
Tim McDougall , Motorola Inc., South Australia
Simon Jolly , FourSticks Pty. Ltd., Frewville, South Australia
pp. 299

A Practical and Efficient Method for Compare-Point Matching (Abstract)

Hi-Keung Tony Ma , Synopsys Inc.
Robert Damiano , Synopsys Inc.
Ted Stanion , Synopsys Inc.
Demos Anastasakis , Synopsys Inc.
pp. 305

Self-Referential Verification of Gate-Level Implementations of Arithmetic Circuits (Abstract)

Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
Ying-Tsai Chang , University of California, Santa Barbara
pp. 311
Session 22 - PANEL: Whither (or Wither?) ASIC Handoff
Session 23 - Embedded Software Automation: From Specification to Binary

Software Synthesis from Synchronous Specifications Using Logic Simulation Techniques (Abstract)

Robert K. Brayton , University of California, Berkeley
Yunjian Jiang , University of California, Berkeley
pp. 319

Complex Library Mapping for Embedded Software Using Symbolic Algebra (Abstract)

Armita Peymandoust , Stanford University, CA
Giovanni De Micheli , Stanford University, CA
Tajana Simunic , HP Labs & Stanford University, Palo Alto, CA
pp. 325

Retargetable Binary Utilities (Abstract)

Jianwen Zhu , University of Toronto, Canada
Maghsoud Abbaspour , University of Toronto, Canada
pp. 331
Session 24 - Applications of Reconfigurable Computing

Dynamic Hardware Plugins in an FPGA with Partial Run-time Reconfiguration (Abstract)

Edson L. Horta , Universidade de San P?ulo, Brazil
David Parlour , Xilinx, Inc, San Jose, CA
David E. Taylor , Washington University, Saint Louis, MO
John W. Lockwood , Washington University, Saint Louis, MO
pp. 343

A Reconfigurable FPGA-Based Readback Signal Generator For Hard-Drive Read Channel Simulator (Abstract)

Kia Bazargan , University of Minnesota, Minneapolis
Jaekyun Moon , University of Minnesota, Minneapolis
Jinghuan Chen , University of Minnesota, Minneapolis
pp. 349
Session 25 - New Test Methods Targeting Non-Classical Faults

Embedded Software-Based Self-Testing for SoC Design (Abstract)

S. Dey , University of California, San Diego
L. Chen , University of California, San Diego
A. Krstic , University of California, Santa Barbara
W.-C. Lai , University of California, Santa Barbara
K.-T. Cheng , University of California, Santa Barbara
pp. 355

A Novel Wavelet Transform Based Transient Current Analysis for Fault Detection and Localization (Abstract)

Swarup Bhunia , Purdue University, Indiana, USA
Kaushik Roy , Purdue University, Indiana, USA
Jaume Segura , Balearic Islands University, Spain
pp. 361

Signal Integrity Fault Analysis Using Reduced-Order Modeling (Abstract)

Amir Attarha , The University of Texas at Dallas
Mehrdad Nourani , The University of Texas at Dallas
pp. 367

Enhancing Test Efficiency for Delay Fault Testing Using Multiple-Clocked Schemes (Abstract)

Jennifer Dworak , Texas A&M University
Kwang-Ting Cheng , UC-Santa Barbara
Thomas W. Williams , Synopsys Inc.
M. Ray Mercer , Texas A&M University
Li-C. Wang , UC-Santa Barbara
Rohit Kapur , Synopsys Inc.
Jing-Jia Liou , UC-Santa Barbara
pp. 371
Session 26 - Special Session: How Do You Design a 10M Gate ASIC?
Session 27 - Power Distribution Issues

HiPRIME: Hierarchical and Passivity Reserved Interconnect Macromodeling Engine for RLKC Power Delivery (Abstract)

Charlie Chung-Ping Chen , University of Wisconsin at Madison
Tsung-Hao Chen , University of Wisconsin at Madison
Yahong Cao , University of Wisconsin at Madison
Yu-Min Lee , University of Wisconsin at Madison
pp. 379

High-Level Current Macro-Model For Power-Grid Analysis (Abstract)

Srinivas Bodapati , University of Illinois at Urbana-Champaign
Farid N. Najm , University of Toronto, Canada
pp. 385

Macro-Modeling Concepts For The Chip Electrical Interface (Abstract)

Claude R. Gauthier , Sun Microsystems Inc., Sunnyvale, CA
Dean Liu , Sun Microsystems Inc., Sunnyvale, CA
Brian W. Amick , Sun Microsystems Inc., Austin, TX
pp. 391

Modeling and Analysis of Regular Symmetrically Structured Power/Ground Distribution Networks (Abstract)

Hui Zheng , Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
pp. 395

Clock Tree Optimization in Synchronous CMOS Digital Circuits for Substrate Noise Reduction Using Folding of Supply Current Transients (Abstract)

St?phane Donnay , IMEC, Leuven, Belgium
Mustafa Badaroglu , IMEC, Leuven, Belgium; ESAT - KU Leuven, Belgium
Hugo De Man , IMEC, Leuven, Belgium; ESAT - KU Leuven, Belgium
Georges Gielen , ESAT - KU Leuven, Belgium
Piet Wambacq , IMEC, Leuven, Belgium
Kris Tiri , IMEC, Leuven, Belgium; UCLA
pp. 399
Session 28 - Advances in Synthesis

Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems (Abstract)

Tiberiu Chelcea , Columbia University, New York, NY
Steven M. Nowick , Columbia University, New York, NY
pp. 405

Design of Asynchronous Circuits by Synchronous CAD Tools (Abstract)

Alex Kondratyev , Cadence Berkeley Laboratory, Berkeley, CA
Kelvin Lwin , Reshape Inc., Mountain View, CA
pp. 411

Implementing Asynchronous Circuits using a Conventional EDA Tool-Flow (Abstract)

Christos P. Sotiriou , Institute of Computer Science (ICS), Foundation of Research and Technology - Hellas (FORTH), Greece
pp. 415

Transformation Rules for Designing CNOT-based Quantum Circuits (Abstract)

Yahiko Kambayashi , Kyoto Univ., Japan
Shigeru Yamashita , NTT Communication Science Labs., Japan
Kazuo Iwama , Kyoto Univ., Japan
pp. 419

Fast Three-Level Logic Minimization Based on Autosymmetry (Abstract)

Linda Pagli , University of Pisa, Italy
Valentina Ciriani , University of Pisa, Italy
Fabrizio Luccio , University of Pisa, Italy
Anna Bernasconi , University of Pisa, Italy
pp. 425
Session 29 - Analog Synthesis & Design Methodology

An Efficient Optimization-based Technique to Generate Posynomial Performance Models for Analog Integrated Circuits (Abstract)

Walter Daems , K. U. Leuven, ESAT-MICAS, Belgium
Willy Sansen , K. U. Leuven, ESAT-MICAS, Belgium
Georges Gielen , K. U. Leuven, ESAT-MICAS, Belgium
pp. 431

Remembrance of Circuits Past: Macromodeling by Data Mining in Large Analog Design Spaces (Abstract)

Hongzhou Liu , Carnegie Mellon University, Pittsburgh, Pennsylvania
Amit Singhee , Carnegie Mellon University, Pittsburgh, Pennsylvania
Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, Pennsylvania
L. Richard Carley , Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 437

Optimal Design of Delta-Sigma ADCs by Design Space Exploration (Abstract)

Georges Gielen , Katholieke Universiteit Leuven, Leuven, Belgium
Johan H. Huijsing , Delft University of Technology, The Netherlands
Ovidiu Bajdechi , Delft University of Technology, The Netherlands
pp. 443

Systematic Design of a 200 MS/s 8-bit Interpolating/Averaging A/D Converter (Abstract)

J. Vandenbussche , Katholieke Universiteit Leuven, Heverlee, Belgium
G. Gielen , Katholieke Universiteit Leuven, Heverlee, Belgium
K. Uyttenhove , Katholieke Universiteit Leuven, Heverlee, Belgium
M. Steyaert , Katholieke Universiteit Leuven, Heverlee, Belgium
E. Lauwers , Katholieke Universiteit Leuven, Heverlee, Belgium
pp. 449
Session 30 - Low-Power Physical Design

Petri Net Modeling of Gate and Interconnect Delays for Power Estimation (Abstract)

N. Ranganathan , University of South Florida, Tampa, Florida
Ashok K. Murugavel , University of South Florida, Tampa, Florida
pp. 455

Low-Swing Clock Domino Logic Incorporating Dual Supply and Dual Threshold Voltages (Abstract)

Sung-Mo Kang , University of California, Santa Cruz
Ki-Wook Kim , Pluris Incorporation, Cupertino, CA
Seong-Ook Jung , University of Illinois, Urbana
pp. 467

DRG-Cache: A Data Retention Gated-Ground Cache for Low Power (Abstract)

Hai Li , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Amit Agarwal , Purdue University, West Lafayette, IN
pp. 473
Session 31 - PANEL: Unified Tools for SoC Embedded Systems: Mission Critical, Mission Impossible or Mission Irrelevant?
Session 32 - Multi-Voltage, Multi-Threshold Design

Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique (Abstract)

Mohamed Elmasry , University of Waterloo, Canada
Mohab Anis , University of Waterloo, Canada
Shawki Areibi , University of Guelph, Canada
Mohamed Mahmoud , University of Waterloo, Canada
pp. 480

Total Power Optimization By Simultaneous Dual-Vt Allocation and Device Sizing in High Performance Microprocessors (Abstract)

Steven Burns , Strategic CAD, Intel Labs, Hillsboro, OR
Tanay Karnik , Circuit Research, Intel Labs, Hillsboro, OR
Venkatesh Govindarajulu , Circuit Research, Intel Labs, Hillsboro, OR
Vivek De , Circuit Research, Intel Labs, Hillsboro, OR
James Tschanz , Circuit Research, Intel Labs, Hillsboro, OR
Shekhar Borkar , Circuit Research, Intel Labs, Hillsboro, OR
Liqiong Wei , Circuit Research, Intel Labs, Hillsboro, OR
Yibin Ye , Circuit Research, Intel Labs, Hillsboro, OR
pp. 486

An Optimal Voltage Synthesis Technique for a Power-Efficient Satellite Application (Abstract)

Dong-In Kang , University of Southern California/Information Sciences Institute, Arlington, VA
Jinwoo Suh , University of Southern California/Information Sciences Institute, Arlington, VA
Stephen P. Crago , University of Southern California/Information Sciences Institute, Arlington, VA
pp. 492
Session 33 - Advanced Simulation Techniques

An Algorithm for Frequency-Domain Noise Analysis in Nonlinear Systems (Abstract)

Giorgio Casinovi , Georgia Institute of Technology, Atlanta
pp. 514
Session 34 - Design Methodologies Meet Network Applications

System-Level Performance Optimization of the Data Queueing Memory Management in High-Speed Network Processors (Abstract)

J. Lambrecht , IMEC, Leuven, Belgium
D. Verkest , IMEC, Leuven, Belgium
F. Catthoor , Katholieke Univ. Leuven; IMEC, Leuven, Belgium
A. Nikologiannis , ELLEMEDIA technologies, Athens, Greece
G. Konstantoulakis , Inaccess Networks SA, Athens, Greece
Ch. Ykman-Couvreur , IMEC, Leuven, Belgium
pp. 518

Analysis of Power Consumption on Switch Fabrics in Network Routers (Abstract)

Luca Benini , University of Bologna
Terry Tao Ye , Stanford University
Giovanni De Micheli , Stanford University
pp. 524

Memory Optimization in Single Chip Network Switch Fabrics (Abstract)

Herman Schmit , Carnegie Mellon University, Pittsburgh, PA
David Whelihan , Carnegie Mellon University, Pittsburgh, PA
pp. 530
Session 35 - Advances in Analog Modeling

Behavioral Modeling of (Coupled) Harmonic Oscillators (Abstract)

Georges Gielen , Katholieke Universiteit Leuven, Belgium
Piet Vanassche , Katholieke Universiteit Leuven, Belgium
Willy Sansen , Katholieke Universiteit Leuven, Belgium
pp. 536

Model Checking Algorithms for Analog Verification (Abstract)

Erich Barke , University of Hannover, Germany
Lars Hedrich , University of Hannover, Germany
Walter Hartong , University of Hannover, Germany
pp. 542

Regularization of Hierarchical VHDL-AMS Models using Bipartite Graphs (Abstract)

Manfred Glesner , Darmstadt University of Technology, Germany
Jochen Mades , Infineon Technologies AG, Munich, Germany
pp. 548
Session 36 - Advances in Timing and Simulation

A General Probabilistic Framework for Worst Case Timing Analysis (Abstract)

Kurt Keutzer , University of California, Berkeley
Michael Orshansky , University of California, Berkeley
pp. 556

False Timing Path Identification Using ATPG Techniques and Delay-Based Information (Abstract)

Magdy Abadir , Motorola Inc., Austin, TX
Jacob Abraham , University of Texas at Austin
Jing Zeng , Motorola Inc., Austin, TX
pp. 562

False-Path-Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation (Abstract)

Angela Krstic , University of California, Santa Barbara
Li-C. Wang , University of California, Santa Barbara
Kwang-Ting Cheng , University of California, Santa Barbara
Jing-Jia Liou , University of California, Santa Barbara
pp. 566
Session 37 - PANEL: Formal Verification Methods: Getting around the Brick Wall
Session 38 - Routing and Buffering

S-Tree: A Technique for Buffered Routing Tree Synthesis (Abstract)

John Lillis , University of Illinois at Chicago
Milos Hrkic , University of Illinois at Chicago
pp. 578

An Algorithm for Integrated Pin Assignment and Buffer Planning (Abstract)

D. F. Wong , University of Texas at Austin
Xiaoping Tang , University of Texas at Austin; Silicon Perspective, A Cadence Company, Santa Clara, CA
Hua Xiang , University of Texas at Austin
pp. 584

An Efficient Routing Database (Abstract)

William Nicholls , Synopsys Inc., Hillsboro, OR
Narendra V. Shenoy , Synopsys Inc., Mountain View, CA
pp. 590
Session 39 - System on Chip Design

Automatic Generation of Embedded Memory Wrapper for Multiprocessor SoC (Abstract)

Ahmed A. Jerraya , TIMA laboratory, France
Ferid Gharsalli , TIMA laboratory, France
Fr?d?ric Rousseau , TIMA laboratory, France
Samy Meftali , TIMA laboratory, France
pp. 596

A Novel Synthesis Technique for Communication Controller Hardware from declarative Data Communication Protocol Specifications (Abstract)

Dietmar M? , Chemnitz University of Technology, Germany
Robert Siegmund , Chemnitz University of Technology, Germany
pp. 602

High-Level Synthesis of Multiple-Precision Circuits Independent of Data-Objects Length (Abstract)

M. C. Molina , Universidad Complutense de Madrid, Spain
R. Hermida , Universidad Complutense de Madrid, Spain
J. M. Mend?as , Universidad Complutense de Madrid, Spain
pp. 612
Session 40 - Timing Analysis and Memory Optimization for Embedded Systems

Schedulability of Event-Driven Code Blocks in Real-Time Embedded Systems (Abstract)

Thomas Erlebach , Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Lothar Thiele , Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Samarjit Chakraborty , Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Simon K? , Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
pp. 616

Associative Caches in Formal Software Timing Analysis (Abstract)

Fabian Wolf , Volkswagen AG, Wolfsburg, Germany
Jan Staschulat , Technical University of Braunschweig, Germany
Rolf Ernst , Technical University of Braunschweig, Germany
pp. 622

Compiler-Directed Scratch Pad Memory Hierarchy Design and Management (Abstract)

A. Choudhary , Northwestern University, Evanston, IL
M. Kandemir , Pennsylvania State University, University Park
pp. 628
Session 41 - Processors and Acclerators for Embedded Applications

The iCore™ 520 MHz Synthesizable CPU Core (Abstract)

Julian Lewis , STMicroelectronics, Inc., UK
Lun Bin Huang , STMicroelectronics, Inc., San Diego, CA
Naresh Soni , STMicroelectronics, Inc., San Diego, CA
Tommy Zounes , STMicroelectronics, Inc., San Diego, CA
Nick Richardson , STMicroelectronics, Inc., San Diego, CA
Razak Hossain , STMicroelectronics, Inc., San Diego, CA
pp. 640

A Flexible Accelerator for Layer 7 Networking Applications (Abstract)

William H. Mangione-Smith , University of California, Los Angeles
Gokhan Memik , University of California, Los Angeles
pp. 646
Session 42 - PANEL: What's the Next EDA Driver?
Session 43 - Cross-Talk Noise Analysis and Management

Estimation of the Likelihood of Capacitive Coupling Noise (Abstract)

David Blaauw , Univ. of Michigan, Ann Arbor
Sarma B. K. Vrudhula , Univ. of Arizona, Tucson
Supamas Sirichotiyakul , Sun Microsystems, Boston, MA
pp. 653

Crosstalk Noise Estimation for Noise Management (Abstract)

Paul B. Morton , University of California at Santa Cruz
Wayne Dai , University of California at Santa Cruz
pp. 659

Towards Global Routing With RLC Crosstalk Constraints (Abstract)

James D. Z. Ma , University of Wisconsin, Madison
Lei He , University of Wisconsin, Madison
pp. 669
Session 44 - Test Cost Reduction for SOCS

Embedded Test Control Schemes for Compression in SOCs (Abstract)

Douglas Kay , Cisco Systems, San Jose, CA
Sung Chung , Cisco Systems, San Jose, CA
Samiha Mourad , Santa Clara University, CA
pp. 679

Wrapper/TAM Co-Optimization, Constraint-Driven Test Scheduling, and Tester Data Volume Reduction for SOCs (Abstract)

Krishnendu Chakrabarty , Duke University, Durham, NC
Vikram Iyengar , Duke University, Durham, NC
Erik Jan Marinissen , Philips Research Laboratories, The Netherlands
pp. 685
Session 45 - Scheduling Techniques for Embedded Systems

Scheduler-Based DRAM Energy Management (Abstract)

A. Sivasubramaniam , The Pennsylvania State University, University Park
N. Vijaykrishnan , The Pennsylvania State University, University Park
M. J. Irwin , The Pennsylvania State University, University Park
V. Delaluz , The Pennsylvania State University, University Park
M. Kandemir , The Pennsylvania State University, University Park
pp. 697

An Integer Linear Programming Based Approach for Parallelizing Applications in On-Chip Multiprocessors (Abstract)

U. Sezer , University of Wisconsin, Madison
I. Kadayif , Pennsylvania State University, University Park
M. Kandemir , Pennsylvania State University, University Park
pp. 703
Session 46 - Special Session: Designing SoCs for Yield Improvement

Embedding Infrastructure IP for SOC Yield Improvement (Abstract)

Yervant Zorian , Virage Logic, Fremont, CA
pp. 709

Using Embedded FPGAs for SoC Yield Improvement (Abstract)

Miron Abramovici , Agere Systems, Murray Hill, NJ
Marty Emmert , Wright State University, Dayton, OH
Charles Stroud , University of North Carolina, Charlotte
pp. 713
Session 47 - Advances in SAT

A Proof Engine Approach to Solving Combinational Design Automation Problems (Abstract)

Byron Cook , Prover Technology
Per Bjesse , Prover Technology
Gunnar Andersson , Prover Technology
Ziyad Hanna , Intel Corporation
pp. 725

Solving Difficult SAT Instances in the Presence of Symmetry (Abstract)

Karem A. Sakallah , University of Michigan, Ann Arbor
Fadi A. Aloul , University of Michigan, Ann Arbor
Arathi Ramani , University of Michigan, Ann Arbor
Igor L. Markov , University of Michigan, Ann Arbor
pp. 731

Satometer: How Much Have We Searched? (Abstract)

Brian D. Sierawski , University of Michigan
Karem A. Sakallah , University of Michigan
Fadi A. Aloul , University of Michigan
pp. 737

SAT with Partial Clauses and Back-Leaps (Abstract)

Gracia Hu , Synopsys, Inc., Hillsboro, OR
Slawomir Pilarski , Synopsys, Inc., Hillsboro, OR
pp. 743

Combining Strengths of Circuit-based and CNF-based Algorithms for a High-Performance SAT Solver (Abstract)

Malay K Ganai , NEC USA CCRL, Princeton NJ
Lintao Zhang , Princeton University
Sharad Malik , Princeton University
Aarti Gupta , NEC USA CCRL, Princeton NJ
Pranav Ashar , NEC USA CCRL, Princeton NJ
pp. 747
Session 48 - Inductance and Substrate Analysis

A Solenoidal Basis Method For Efficient Inductance Extraction (Abstract)

Weiping Shi , Texas A&M University, College Station
Hemant Mahawar , Texas A&M University, College Station
Vivek Sarin , Texas A&M University, College Station
pp. 751

On the Efficacy of Simplified 2D On-Chip Inductance Models (Abstract)

Tao Lin , Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Michael W. Beattie , Carnegie Mellon University, Pittsburgh, PA
pp. 757

A Physical Model for the Transient Response of Capacitively Loaded Distributed rlc Interconnects (Abstract)

James D. Meindl , Georgia Institute of Technology, Atlanta
Jeffrey A. Davis , Georgia Institute of Technology, Atlanta
Raguraman Venkatesan , Georgia Institute of Technology, Atlanta
pp. 763

HSpeedEx: A High-Speed Extractor for Substrate Noise Analysis in Complex Mixed-Signal SOC (Abstract)

Adil Koukab , Swiss Federal Institute of Technology (EPFL), Switzerland
Michel Declercq , Swiss Federal Institute of Technology (EPFL), Switzerland
Catherine Dehollain , Swiss Federal Institute of Technology (EPFL), Switzerland
pp. 767

Combined BEM/FEM Substrate Resistance Modeling (Abstract)

N.P. van der Meijs , Delft University of Technology, The Netherlands
E. Schrik , Delft University of Technology, The Netherlands
pp. 771
Session 49 - Development of Processors and Communication Networks for Embedded Systems

System Design Methodologies for a Wireless Security Processing Platform (Abstract)

Anand Raghunathan , NEC USA, Princeton, NJ
Murugan Sankaradass , NEC USA, Princeton, NJ
Srivaths Ravi , NEC USA, Princeton, NJ
Nachiketh Potlapally , NEC USA, Princeton, NJ
pp. 777

Constraint-Driven Communication Synthesis (Abstract)

Luca P. Carloni , UC Berkeley EECS Department
Alessandro Pinto , UC Berkeley EECS Department
Alberto L. Sangiovanni-Vincentelli , UC Berkeley EECS Department
pp. 783

Component-Based Design Approach for Multicore SoCs (Abstract)

W. Ces?rio , TIMA Laboratory, SLS Group, France
G. Nicolescu , TIMA Laboratory, SLS Group, France
A. Baghdadi , TIMA Laboratory, SLS Group, France
S. Yoo , TIMA Laboratory, SLS Group, France
A. A. Jerraya , TIMA Laboratory, SLS Group, France
M. Diaz-Nava , STMicroelectronics, France
Y. Paviot , TIMA Laboratory, SLS Group, France
L. Gauthier , TIMA Laboratory, SLS Group, France
D. Lyonnard , TIMA Laboratory, SLS Group, France
pp. 789

Traffic Analysis for On-chip Networks Design of Multimedia Applications (Abstract)

Girish Varatkar , Carnegie Mellon University, Pittsburgh, PA
Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
pp. 795
Session 50 - Moving Towards More Effective Validation

Hole Analysis for Functional Coverage Data (Abstract)

Shmuel Ur , IBM Research Laboratory in Haifa, Haifa University, Israel
Avi Ziv , IBM Research Laboratory in Haifa, Haifa University, Israel
Oded Lachish , IBM Research Laboratory in Haifa, Haifa University, Israel
Eitan Marcus , IBM Research Laboratory in Haifa, Haifa University, Israel
pp. 807

Effective Safety Property Checking Using Simulation-Based Sequential ATPG (PDF)

Koichiro Takayama , Fujitsu Labs. of America Inc., Sunnyvale, CA
Shuo Sheng , Rutgers University, Piscataway, NJ
Michael S. Hsiao , Virginia Tech, Blacksburg, VA
pp. 813

A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking (Abstract)

Darren Galpin , Infineon Technologies UK Ltd
Tim Blackmore , Infineon Technologies UK Ltd
Mike G. Bartley , Elixent Ltd, Castlemead
pp. 819
Session 51 - Special Session: Energy Efficient Mobile Computing

Energy-Efficient Communication Protocols (Abstract)

Carla F. Chiasserini , Dip. di Elettronica Politecnico di Torino, Italy
Vikram Srinivasan , Dept. of ECE, UCSD
Pavan Nuggehalli , Dept. of ECE, UCSD
pp. 824

Reliable and Energy-Efficient Digital Signal Processing (Abstract)

Naresh Shanbhag , University of Illinois at Urbana-Champaign
pp. 830

CMOS: A Paradigm for Low Power Wireless? (Abstract)

Michiel Steyaert , Katholieke Universiteit Leuven, Belgium
Peter Vancorenland , Katholieke Universiteit Leuven, Belgium
pp. 836
Session 52 - Floorplanning and Placement

TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans (Abstract)

Jai-Ming Lin , National Chiao Tung University, Taiwan
Yao-Wen Chang , National Taiwan University, Taiwan
pp. 842

Floorplanning with Alignment and Performance Constraints (Abstract)

D. F. Wong , University of Texas at Austin
Xiaoping Tang , University of Texas at Austin; Silicon Perspective, A Cadence Company, Santa Clara, CA
pp. 848
Session 53 - Circuit Effects in Static Timing

Coping with Buffer Delay Change Due to Power and Ground Noise (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara
Lauren Hui Chen , Avant! Corp., Fremont, CA
Forrest Brewer , University of California, Santa Barbara
pp. 860

Timed Pattern Generation for Noise-on-Delay Calculation (Abstract)

Seung Hoon Choi , Purdue University, West Lafayette, IN
Florentin Dartu , Intel Corporation, Hillsboro, OR
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 870

VeriCDF: A New Verification Methodology for Charged Device Failures (Abstract)

Jaesik Lee , Univ of Illinois, Urbana
Ki-Wook Kim , Pluris Incorporation, Cupertino, CA
Sung-Mo Kang , University of California, Santa Cruz
pp. 874
Session 54 - Design Space Exploration for Embedded Systems

A Framework for Evaluating Design Tradeoffs in Packet Processing Architectures (Abstract)

Simon K? , Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Samarjit Chakraborty , Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Lothar Thiele , Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Matthias Gries , Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
pp. 880

Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering (Abstract)

D. Sciuto , Politecnico di Milano, Italy
C. Silvano , Universit? degli Studi di Milano, Italy
A. Bona , ALaRI, Lugano, Switzerland
M. Sami , Politecnico di Milano, Italy
R. Zafalon , STMicroelectronics, Agrate B. (MI), Italy
V. Zaccaria , Politecnico di Milano, Italy
pp. 886

Energy Exploration and Reduction of SDRAM Memory Systems (Abstract)

Yongseok Choi , Seoul National University, Korea
Naehyuck Chang , Seoul National University, Korea
Yongsoo Joo , Seoul National University, Korea
Kwanho Kim , Seoul National University, Korea
Hojun Shim , Seoul National University, Korea
Hyung Gyu Lee , Seoul National University, Korea
pp. 892
Session 55 - Behavioral Synthesis

Coordinated Transformations for High-Level Synthesis of High Performance Microprocessor Blocks (Abstract)

Nikil Dutt , University of California, Irvine
Alex Nicolau , University of California, Irvine
Michael Kishinevsky , Intel Incorporated, Hillsboro, Oregon
Rajesh Gupta , University of California, Irvine
Nick Savoiu , University of California, Irvine
Timothy Kam , Intel Incorporated, Hillsboro, Oregon
Shai Rotem , Intel Incorporated, Hillsboro, Oregon
pp. 898

Forward-Looking Objective Functions: Concept & Applications in High Level Synthesis (Abstract)

Seapahn Megerian , Univ. of California, Los Angeles
Jennifer L. Wong , Univ. of California, Los Angeles
Miodrag Potkonjak , Univ. of California, Los Angeles
pp. 904

ILP-Based Engineering Change (Abstract)

Jessica Feng , University of California, Los Angeles
Farinaz Koushanfar , University of California, Berkeley
Jennifer L. Wong , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 910

Author Index (PDF)

pp. 916
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