The Community for Technology Leaders
Design Automation Conference (2001)
Las Vegas, Nevada, United States
June 18, 2001 to June 22, 2001
ISBN: 1-58113-297-2
TABLE OF CONTENTS

Reviewers (PDF)

pp. xv

Call for Papers (PDF)

pp. xix
Session 1 - Panel: Teh Electronics Industry Supply Chain: Who Will Do What?
Session 2 - Nanometer Futures

Future Performance Challenges in Nanometer Design (Abstract)

Himanshu Kaul , University of Michigan, Ann Arbor
Dennis Sylvester , University of Michigan, Ann Arbor
pp. 3-8

IC Design in High-Cost Nanometer-Technologies Era (Abstract)

Wojciech Maly , Carnegie Mellon University, Pittsburgh, PA
pp. 9-14
Session 3 - System-Level Configurability: Bus, Interface, and Processor Design

LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs (Abstract)

Anand Raghunathan , UC San Diego, La Jolla, CA
Kanishka Lahiri , NEC USA, Princeton, NJ
Ganesh Lakshminarayana , NEC USA, Princeton, NJ
pp. 15-20

Latency-Driven Design of Multi-Purpose Systems-on-Chip (Abstract)

Seapahn Maguerdichian , UCLA Computer Science Dep., Los Angeles, CA
Darko Kirovski , Microsoft Research, Redmond, WA
Milenko Drinic , UCLA Computer Science Dep., Los Angeles, CA
pp. 27-30
Session 4 - Making Verification More Efficient

Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines (Abstract)

Robert Damiano , Advanced Technology, Synopsys Inc.
James Kukula , Advanced Technology, Synopsys Inc.
Pei-Hsin Jiang , Advanced Technology, Synopsys Inc.
Tony Ma , Advanced Technology, Synopsys Inc.
Yunshan Zhu , Advanced Technology, Synopsys Inc.
Dong Wang , Carnegie Mellon University
pp. 35-40

Scalable Hybrid Verification of Complex Microprocessors (Abstract)

Fadi Aloul , University of Michigan
Saugata Chatterjee , University of Michigan
Todd Austin , University of Michigan
Chris Weaver , University of Michigan
Karem Sakallah , University of Michigan
Maher Mneimneh , University of Michigan
pp. 41-46

Symbolic RTL Simulation (Abstract)

Robert Damiano , Advanced Technology Group, Synopsys Inc.
Alferd K?lbl , Institute for EDA, technical University of Munich, Munich, Germany
James Kukula , Advanced Technology Group, Synopsys Inc.
pp. 47-52
Session 5 - SoC and High-Level DFT

Instruction-Level DFT for Testing Processor and IP Cores in System-on-A-Chip (Abstract)

Kwang-Ting Cheng , University of California, Santa Barbara, CA
Wei-Cheng Lai , University of California, Santa Barbara, CA
pp. 59-64

Test Strategies for BIST at the Algorithmic and Register-Transfer Levels (Abstract)

Chris Papachristou , Case Western Reserve University, Cleveland, OH
Kelly A. Ockunzzi , IBM Microelectronics, Burlington, VT
pp. 65-70
Session 6 - Panel: The Next HDL: If C++ is the Answer, What was the Question?
Session 7 - Design for Subwavelength Manufacturability: Impact on EDA

Reticle Enhancement Technology: Implications and Challenges for Physical Design (Abstract)

M. Thompson , Motorola DigitalDNA Laboratories, Austin, TX
W. Grobman , Motorola DigitalDNA Laboratories, Austin, TX
E. Demircan , Motorola DigitalDNA Laboratories, Austin, TX
C. Yuan , Motorola DigitalDNA Laboratories, Austin, TX
R. Wang , Motorola DigitalDNA Laboratories, Austin, TX
R. Tian , Motorola DigitalDNA Laboratories, Austin, TX
pp. 73-78

Enabling Alternating Phase Shifted Mask Designs for A Full Logic Gate Level: Design Rules and Design Rule Checking (Abstract)

Jennifer Lund , IBM Research, Yorktown Hts., NY
Fook-Luen Heng , IBM Research, Yorktown Hts., NY
Ioana Graur , IBM Microelectronics, East Fishkill, NY
Lars Liebmann , IBM Microelectronics, East Fishkill, NY
pp. 79-84

Layout Design Methodolgies for Sub-Wavelength Manufacturing (Abstract)

Sridhar Panchapakesan , Avant! Corporation, Beaverton, OR
Michael L. Rieger , Avant! Corporation, Beaverton, OR
Jeffrey P. Mayhew , Avant! Corporation, Beaverton, OR
pp. 85-88

Adoption of OPC and the Impact on Design and Layout (Abstract)

Luigi Capodieci , ASML MaskTools, Santa Clara, CA
Bob Socha , ASM Lithography, Santa Clara, CA
F. M. Schellenberg , Mentor Graphics, San Jose, CA
Olivier Toublan , Mentor Graphics, San Jose, CA
pp. 89-92

Practical Application of Full-Feature Alternating Phase-Shifting Technology for a Phase-Aware Standard-Cell Design Flow (Abstract)

Michel C? , Numerical Technologies, Inc., San Jose, CA
Philippe Hurat , Numerical Technologies, Inc., San Jose, CA
Vinod Malhotra , Numerical Technologies, Inc., San Jose, CA
Michael Sanie , Numerical Technologies, Inc., San Jose, CA
pp. 93-96
Session 8 - New Ideas in Logic Synthesis

Layout-Driven Hot-Carrier Degradation Minimization using Logic Restructuring Techniques (Abstract)

Kai Wang , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
Chih-Wei Chang , University of California, Santa Barbara
pp. 97-102

An Algorithm for Bi-Decomposition of Logic Functions (Abstract)

Alan Mishchenko , Portland State University, OR
Marek Perkowski , Portland State University, OR
Bernd Steinbach , Freiberg Univ. of Mining and Techn., Germany
pp. 103-108

Factoring and Recognition of Read-Once Functions using Cographs and Normality (Abstract)

Aviad Mintz , Bar-Ilan University, Israel
Udi Rotics , Netanya Academic College, Israel
Martin C. Golumbic , Bar-Ilan University, Israel
pp. 109-114

Logic Minimization Using Exclusive OR Gates (Abstract)

Valentina Ciriani , Dipartimento di Informatica, Pisa, Italy
pp. 115-120
Session 9 - Analog Design and Modeling

Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems (Abstract)

Jafar Savoj , University of California, Los Angeles, CA
Behzad Razavi , University of California, Los Angeles, CA
pp. 121-126

A Novel Method for Stochastic Nonlinearity Analysis of a CMOS Pipeline ADC (Abstract)

A. Wagner , IBM Haifa Research Lab, MATAM, Israel
Eliyahu Shamsaevc , IBM Haifa Research Lab, MATAM, Israel
David Goren , IBM Haifa Research Lab, MATAM, Israel
pp. 127-132

Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems (Abstract)

Sree Ganesan , University of Cincinnati, OH
Ranga Vemuri , University of Cincinnati, OH
pp. 133-138

Efficient DDD-Based Symbolic Analysis of Large Linear Analog Circuits (Abstract)

Georges Gielen , Katholieke Universiteit Leuven, Belgium
Wim Verhaegen , Katholieke Universiteit Leuven, Belgium
pp. 139-144
Session 10 - Scan-Based Testing

Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits (Abstract)

Irith Pomeranz , Purdue University, W. Lafayette, IN
pp. 145-150

Test Volume and Application Time Reduction Through Scan Chain Concealment (Abstract)

Alex Orailoglu , University of California, San Diego, La Jolla, CA
Ismet Bayraktaroglu , University of California, San Diego, La Jolla, CA
pp. 151-155

An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing (Abstract)

Sudhakar Reddy , University of Iowa, IA
Irith Pomeranz , Purdue University, W. Lafayette, IN
pp. 156-161

Generating Efficient Tests for Continuous Scan (Abstract)

Sheng-Nan Chiou , National Chung-Hsing University, Taiwan
Sying-Jyan Wang , National Chung-Hsing University, Taiwan
pp. 162-165

Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip (Abstract)

Krishnendu Chakrabarty , Duke University, Durham, NC
Anshuman Chandra , Duke University, Durham, NC
pp. 166-169
Session 11 - Panel: Your Core - My Problem? Integration and Verification of IP
Session 12 - Configurable Computing: Reconfiguring the Industry

A Quick Safari Through the Reconfiguration Jungle (Abstract)

Patrick Schaumont , IMEC, Leuven, Belgium
Kurt Keutzer , UCLA Dept of EECS, Los Angeles, CA
Majid Sarrafzadeh , UCLA Dept of CS, Los Angeles, CA
Ingrid Verbauwhede , UCLA Dept of EE, Los Angeles, CA
pp. 172-177

Re-Configurable Computing in Wireless (Abstract)

Levent Caglar , Chameleon Systems, Inc., San Jose, CA
Bill Salefski , Chameleon Systems, Inc., San Jose, CA
pp. 178-183

Hardware/Software Instruction set Configurability for System-on-Chip Processors (Abstract)

Earl Killian , Tensilica, Inc., Santa Clara, CA
Dror Maydan , Tensilica, Inc., Santa Clara, CA
Chris Rowen , Tensilica, Inc., Santa Clara, CA
Albert Wang , Tensilica, Inc., Santa Clara, CA
pp. 184-188
Session 13 - Interconnnect Design Optimization

A Practical Methodology for Early Buffer and Wire Resource Allocation (Abstract)

Charles J. Alpert , IBM Corporation, Austin, TX
Paul Villarrubia , IBM Corporation, Austin, TX
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Jiang Hu , IBM Corporation, Austin, TX
pp. 189-194

Creating and Exploiting Flexibility in Steiner Trees (Abstract)

Elaheh Bozorgzadeh , University of California, Los Angeles
Ryan Kastner , University of California, Los Angeles
Majid Sarrafzadeh , University of California, Los Angeles
pp. 195-198

Simultaneous Shield Insertion and Net Ordering Under Explicit RLC Noise Constraint (Abstract)

Lei He , University of Wisconsin, Madison
Irwan Luwandi , University of Wisconsin, Madison
Kevin M. Lepak , University of Wisconsin, Madison
pp. 199-202

On Optimum Switch Box Designs for 2-D FPGAs (Abstract)

Hongbing Fan , University of Victoria, BC. Canada
Chak-Chung Cheung , The Chinese University of HK, Shatin, Hong Kong
Jiping Liu , The University of Lethbridge, AB. Canada
Yu-Liang Wu , The Chinese University of HK, Shatin, Hong Kong
pp. 203-208
Session 14 - Power Estimation Techniques

Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks (Abstract)

N. Ranganathan , University of South Florida, Tampa, Florida
Sanjukta Bhanja , University of South Florida, Tampa, Florida
pp. 209-214

A Static Estimation Technique of Power Sensitivity in Logic Circuits (Abstract)

C. L. Liu , Tsing Hua Univ., Hsinchu, Taiwan
Ki-Seok Chung , Intel Corporation, Santa Clara, CA USA
Taewhan Kim , KAIST, Taejon, Korea
pp. 215-219

JouleTrack: A Web Based Tool for Software Energy Profiling (Abstract)

Anantha P. Chandrakasan , Massachusetts Institute of Technology, Cambridge
Amit Sinha , Massachusetts Institute of Technology, Cambridge
pp. 220-225
Session 15 - Functional Validation Based on Boolean Reasoning (BDD, SAT)

Effective use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW (Abstract)

Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
Miroslav N. Velev , Carnegie Mellon University, Pittsburgh, PA
pp. 226-231

Circuit-Based Boolean Reasoning (Abstract)

Malay K. Ganai , The University of Texas at Austin
Andreas Kuehlmann , Cadence Berkeley Labs, Berkeley, CA
Viresh Paruthi , IBM Enterprise Systems Group, Austin, TX
pp. 232-237

Checking Equivalence for Partial Implementations (Abstract)

Bernd Becker , Albert-Ludwigs-University, Germany
Christoph Scholl , Albert-Ludwigs-University, Germany
pp. 238-243
Session 16 - Verification: Life Beyond Algorithms

Validating the Intel Pentium 4 Microprocessor (Abstract)

Bob Bentley , Intel Corporation, Hillsboro, Oregon
pp. 244-248

Nuts and Bolts of Core and SoC Verification (Abstract)

Ken Albin , Motorola, Inc., Austin, TX
pp. 249-252

Teaching Future Verification Engineers: the Forgotten Side of Logic Design (Abstract)

Lyle Hanrahan , IBM Corporation
Duane Marhefka , The Ohio State University
Fusun Ozguner , The Ohio State University
Bruce Wile , IBM Corporation
Joanne DeGroat , The Ohio State University
Jennifer Stofer , IBM Corporation
pp. 253-255
Session 17 - Dissecting an Embedded System: Lessons from Bluetooth

SoC Integration of Reusable Baseband Bluetooth IP (Abstract)

Barry Clark , Ericsson Technol, Licensing AB, Lund
Torbj? Grahm , Ericsson Technol, Licensing AB, Lund
pp. 256-231

One-Chip Bluetooth Asic Challenges (PDF)

Paul T. M. van Zeijl , Ericsson Eurolab Netherlands, The Netherlands
pp. 262
Session 18 - Algorithmic and Compiler Transformations for High-Level Synthesis

Transformations for the Synthesis and Optimization of Asynchronous Distributed Control (Abstract)

Michael Theobald , Columbia University, New York, NY
Steven M. Nowick , Columbia University, New York, NY
pp. 263-268

Speculation Techniques for High Level Synthesis of Control Intensive Designs (Abstract)

Nikil Dutt , University of California at Irvine
Sunwoo Kim , University of California at Irvine
Rajesh Gupta , University of California at Irvine
Sumit Gupta , University of California at Irvine
Nick Savoiu , University of California at Irvine
Alex Nicolau , University of California at Irvine
pp. 269-272

Using Symbolic Algebra in Algorithmic Level DSP Synthesis (Abstract)

Giovanni De Micheli , Stanford University, CA
Armita Peymandoust , Stanford University, CA
pp. 277-282
Session 19 - Gate Delay Calculation

Computing Logic-Stage Delays using Circuit Simulation and Symbolic Elmore Analysis (Abstract)

Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
Clayton B. McDonald , Carnegie Mellon University, Pittsburgh, PA
pp. 283-288

A New Gate Delay Model for Simultaneous Switching and Its Applications (Abstract)

Sandeep K. Gupta , University of Southern California, Los Angeles, CA
Liang-Chi Chen , University of Southern California, Los Angeles, CA
Melvin A. Breuer , University of Southern California, Los Angeles, CA
pp. 289-294

Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits (Abstract)

Geng Bai , University of Illinois, Urbana
Sudhakar Bobba , Sun Microsystems Inc., Palo Alto CA
Ibrahim N. Hajj , University of Illinois, Urbana
pp. 295-300
Session 20 - Memory, Bus and Current Testing

Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories (Abstract)

Chih-Tsun Huang , National Tsing Hua University, Hsinchu, Taiwan
Chi-Feng Wu , National Tsing Hua University, Hsinchu, Taiwan
Kuo-Liang Cheng , National Tsing Hua University, Hsinchu, Taiwan
Chih-Wea Wang , National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Hsinchu, Taiwan
pp. 301-306

Improving Bus Test via IDDT and Boundary Scan (Abstract)

Shih-Yu Yang , Intel Corporation, Hillsboro, OR
Christos A. Papachristou , Case Western Reserve University, Cleveland, OH
Massood Tabib-Azar , Case Western Reserve University, Cleveland, OH
pp. 307-312

Fault Characterizations and Design-for-Testability Technique for Detecting I{DDQ} Faults in CMOS/BiCMOS Circuits (Abstract)

Kaamran Raahemifar , University of Windsor, Ontario, Canada
Majid Ahmadi , Ryerson Polytechnic University, Toronto, Canada
pp. 313-316

Testing for Interconnect Crosstalk Defects using On-Chip Embedded Processor Cores (Abstract)

Xiaoliang Bai , University of California at San Diego, La Jolla, CA
Li Chen , University of California at San Diego, La Jolla, CA
Sujit Dey , University of California at San Diego, La Jolla, CA
pp. 317-320
Session 21 - Panel: (When) Will FPGAs Kill ASIC's?
Session 22 - Inductance 101 and Beyond

Inductance 101: Modeling and Extraction (Abstract)

Michael W. Beattie , Carnegie Mellon University, Pittsburgh, Pennsylvania
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 323-328

Inductance 101: Analysis and Design Issues (Abstract)

David Blaauw , Motorola Inc., Austin TX
Junfeng Wang , Motorola Inc., Austin TX
Min Zhao , Motorola Inc., Austin TX
Kaushik Gala , Motorola Inc., Austin TX
Vladimir Zolotov , Motorola Inc., Austin TX
pp. 329-334

Modeling Magnetic Coupling for On-Chip Interconnect (Abstract)

Michael W. Beattie , Carnegie Mellon University, Pittsburgh, Pennsylvania
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 335-340

Min/Max On-Chip Inductance Models and Delay Metrics (Abstract)

Tak Young , Monterey Design Systems, Sunnyvale, CA
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Yi-Chang Lu , Stanford University, CA
Mustafa Celik , Monterey Design Systems, Sunnyvale, CA
pp. 341-346
Session 23 - Memory Optimization Techniques for DSP Processors

Utilizing Memory Bandwidth in DSP Embedded Processors (Abstract)

Catherine H. Gebotys , University of Waterloo, Ontario, Canada
pp. 347-352

Address Code Generation for Digital Signal Processors (Abstract)

Sathishkumar Udayanarayanan , Arizona State University, Tempe, AZ
Chaitali Chakrabarti , Arizona State University, Tempe, AZ
pp. 353-358

Reducing Memory Requirements of Nested Loops for Embedded Systems (Abstract)

A. Narayan , Louisiana State University, Baton Rouge, LA
J. Ramanujam , Louisiana State University, Baton Rouge, LA
Mahmut Kandemir , Pennsylvania State University, State College, PA
Jinpyo Hong , Louisiana State University, Baton Rouge, LA
pp. 359-364

Detecton of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications (Abstract)

Francky Catthoor , IMEC, Leuven, Belgium; EE.Dept. of Kath. Univ. Leuven
PerGunnar Kjeldsberg , Norwegian University of Science and Technology, Trondheim, Norway
Einar J. Aas , Norwegian University of Science and Technology, Trondheim, Norway
pp. 365-370
Session 24 - Technology Dependent Logic Synthesis

A New Structural Pattern Matching Algorithm for Technology Mapping (Abstract)

Min Zhao , Motorola Inc., Austin, TX
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
pp. 371-376

Latency and Latch Count Minimization in Wave Steered Circuits (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara
Amit Singh , University of California, Santa Barbara
Arindam Mukherjee , University of California, Santa Barbara
pp. 383-388

Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping (Abstract)

Jason Cong , UCLA Computer Science Department, Los Angeles, CA
Michail Romesis , UCLA Computer Science Department, Los Angeles, CA
pp. 389-394
Session 25 - Collaborative and Distributed Design Frameworks

Application of Constraint-Based Heuristics in Collaborative Design (Abstract)

Stephen W. Director , University of Michigan, Ann Arbor
Juan Antonio Carballo , IBM Austin Research Laboratory, TX
pp. 395-400

A Universal Client for Distributed Networked Design and Computing (Abstract)

Hemang Lavana , Cisco Systems, Inc., Research Triangle Park, NC
Franc Brglez , Department of Computer Science, NC State University, Raleigh, NC
pp. 401-406

Hypermedia-Aided Design (Abstract)

Darko Kirovski , University of California, Los Angeles
Milenko Drinic , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 407-412

A Framework for Object Oriented Hardware Specification, Verification, and Synthesis (Abstract)

Yaron Kashai , Verisity Design, Inc., Mountain View, CA
W. Rosenstiel , University of Tuebingen, Germany
T. Oppold , University of Tuebingen, Germany
M. Winterholer , University of Tuebingen, Germany
T. Kuhn , University of Tuebingen, Germany
Marc Edwards , Cisco Systems, Inc., NC
pp. 413-418
Session 26 - Panel: When Will the Analog Design Flow Catch Up with Digital Methodology?
Session 27 - Closing the Gap Between ASIC and Custom: Design Examples

Achieving 550 MHz in an ASIC Methodology (Abstract)

D. G. Chinnery , University of California at Berkeley
K. Keutzer , University of California at Berkeley
B. Nikolic , University of California at Berkeley
pp. 420-425

A Semi-Custom Design Flow in High-Performance Microprocessor Design (Abstract)

Gregory A. Northrop , IBM Research, Yorktown Heights, NY
Pong-Fei Lu , IBM Research, Yorktown Heights, NY
pp. 426-431

Reducing the Frequency Gap Between ASIC and Custom Designs: A Custom Perspective (Abstract)

Jim Schwartz , Intel Corporation, Hillsboro, OR
Matthew J. Parker , Intel Corporation, Hillsboro, OR
Stephen E. Rich , Intel Corporation, Hillsboro, OR
pp. 432-437
Session 28 - Energy and Flexibility Driven Scheduling

Low-Energy Intra-Task Voltage Scheduling using Static Timing Analysis (Abstract)

Seongsoo Lee , Ewha Woman's University
Dongkun Shin , Seoul National University
Jihong Kim , Seoul National University
pp. 438-443

Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems (Abstract)

Jiong Luo , Princeton University, NJ
Niraj K. Jha , Princeton University, NJ
pp. 444-449

An Approach to Incremental Design of Distributed Embedded Systems (Abstract)

Petru Eles , Link?ping University, Sweden
Zebo Peng , Link?ping University, Sweden
Paul Pop , Link?ping University, Sweden
Traian Pop , Link?ping University, Sweden
pp. 450-455
Session 29 - Representation and Optimization for Digital Arithmetic Circuits

Signal Representation Guided Synthesis Using Carry-Save Adders for Synchronous Data-Path Circuits (Abstract)

Alan N. Willson , University of California, Los Angeles
Zhan Yu , University of California, Los Angeles
Meng-Lin Yu , Agere Systems, Holmdel, NJ
pp. 456-461

Improved Merging of Datapath Operators Using Information Content and Required Precision Analysis (Abstract)

Sanjeev Saluja , Cadence Design Systems, San Jose, CA
Anmol Mathur , Cadence Design Systems, San Jose, CA
pp. 462-467

Digital Filter Synthesis Based on Minimal Signed Digit Representation (Abstract)

Hyeong-Ju Kang , KAIST, Taejeon, Korea
In-Cheol Park , KAIST, Taejeon, Korea
pp. 468-473
Session 30 - Techniques for IP Protection

Publicly Detectable Techniques for the Protection Virtual Components (Abstract)

Gang Qu , University of Maryland, College Park
pp. 474-479

Watermarking of SAT Using Combinatorial Isolation Lemmas (Abstract)

Jennifer L. Wong , University of California, Berkeley, California
Rupak Majumdar , University of California, Berkeley, California
pp. 480-485

Watermarking Graph Partitioning Solutions (Abstract)

Miodrag Potkonjak , University of California, Los Angeles
Greg Wolfe , University of California, Los Angeles
Jennifer L. Wong , University of California, Los Angeles
pp. 486-489

Hardware Metering (Abstract)

Gang Qu , University of Maryland, College Park
Farinaz Koushanfar , UC Berkeley, CA
pp. 490-493
Session 31 - Visualization and Animation for VLSI Design

Technical Visualizations in VLSI Design: Visualization (Abstract)

Phillip J. Restle , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 494-499

Using Texture Mapping with Mipmapping to Render a VLSI Layout (Abstract)

Jeff Solomon , Stanford University, CA
Mark Horowitz , Stanford University, CA
pp. 500-505

Web-Based Algorithm Animation (Abstract)

Marc Najork , Compaq Systems Research Center, Palo Alto, CA
pp. 506-511
Session 32 - Application-Specific Customization for Systems-on-a-Chip

Speeding Up Control-Dominated Applications Through Microarchitectural Customizations in Embedded Processors (Abstract)

Peter Petrov , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 512-517

Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip (Abstract)

Damien Lyonnard , SLS Group, TIMA Laboratory, France
Sungjoo Yoo , SLS Group, TIMA Laboratory, France
Amer Baghdadi , SLS Group, TIMA Laboratory, France
Ahmed A. Jerraya , SLS Group, TIMA Laboratory, France
pp. 518-523

Dynamic Voltage Scaling and Power Management for Portable Systems (Abstract)

Peter Glynn , Stanford University, CA
Giovanni De Micheli , Stanford University, CA
Luca Benini , DEIS, University of Bologna
Tajana Simunic , Stanford University, CA
Andrea Acquaviva , DEIS, University of Bologna
pp. 524-529
Session 33 - Satisfiability Solvers and Techniques

Chaff: Engineering an Efficient SAT Solver (Abstract)

Matthew W. Moskewicz , UC Berkeley
Lintao Zhang , Princeton University
Sharad Malik , Princeton University
Ying Zhao , Princeton University
pp. 530-535

Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation (Abstract)

Zijiang Yang , CCRL, NEC USA, Princeton, NJ
Anubhav Gupta , Carnegie Mellon University, Pittsburgh, PA
Pranav Ashar , CCRL, NEC USA, Princeton, NJ
Aarti Gupta , CCRL, NEC USA, Princeton, NJ
pp. 536-541

SATIRE: A New Incremental Satisfiability Engine (Abstract)

Jesse Whittemore , University of Michigan
Karem Sakallah , University of Michigan
Joonyoung Kim , Intel Corporation
pp. 542-545

A Framework for Low Complexity Static Learning (Abstract)

Emil Gizdarski , University of Rousse, Bulgaria
Hideo Fujiwara , Nara Institute of Science and Technology, Japan
pp. 546
Session 34 - Power and Interconnect Analysis

Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling (Abstract)

X.-D. Sheldon Tan , Altera Corporation, San Jose, CA
C.-J. Richard Shi , University of Washington, Seattle
pp. 550-554

An Interconnect Energy Model Considering Coupling Effects (Abstract)

Taku Uchino , Toshiba Corporation, Japan
Jason Cong , University of California, Los Angeles
pp. 555-558

Using Conduction Modes Basis Functions for Efficient Electromagnetic Anaysis of On-Chip and Off-Chip Interconnect (Abstract)

Alberto Sangiovanni-Vincentelli , Univ. of California, Berkeley
Jacob White , Massachusetts Institute of Technology
Luca Daniel , University of California, Berkeley
pp. 563-566

Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs (Abstract)

Massoud Pedram , Univ. of Southern California, Los Angeles
Kaustav Banerjee , Stanford University, CA
Lukas P. P. P. van Ginneken , Magma Design Automation Inc., Cupertino, CA
Amir H. Ajami , Univ. of Southern California, Los Angeles
pp. 567-572
Session 35 - Domain Specific Design Methodologies

Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-bit Symmetric Block Siphers (Abstract)

Piyush Mishra , Polytechnic University, Brooklyn, NY
Yongkook Kim , IBM Corporation, Poughkeepsie, NY
Ramesh Karri , Polytechnic University, Brooklyn, NY
Kaijie Wu , Polytechnic University, Brooklyn, NY
pp. 579-584

MetaCores: Design and Optimization Techniques (Abstract)

Dusan Petranovic , University of California, Berkeley
Seapahn Meguerdichian , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
Farinaz Koushanfar , LSI Logic Corporation, Milpitas, California
Advait Morge , University of California, Berkeley
pp. 585-590
Session 36 - Panel: Debate: Who has Nanometer Design Under Control?
Session 37 - Analysis and Implementation for Embedded Systems

A Hardware/Software Co-Design Flow and IP Library Based on Simulink (Abstract)

L. M. Reyneri , Politecnico di Torino, Italy
A. Serra , Politecnico di Torino, Italy
F. Cucinotta , Politecnico di Torino, Italy
L. Lavagno , Universit? di Udine, Italy
pp. 593-598

System-Level Power/Performance Analysis for Embedded Systems Design (Abstract)

Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
Amit Nandi , Carnegie Mellon University, Pittsburgh, PA
pp. 599-604

High-Level Software Energy Macro-Modeling (Abstract)

T. K. Tan , Princeton University, NJ
A. K. Raghunathan , NEC, C&C Research Labs, Princeton, NJ
G. Lakishminarayana , NEC, C&C Research Labs, Princeton, NJ
N. K. Jha , Princeton University, NJ
pp. 605-610
Session 38 - Industrial Case Studies in Verification

Model Checking of S3C2400X Industrial Embedded SOC Product (Abstract)

Hoon Choi , Samsung Electronics, Yongin-City, Kyunggi-Do, Korea
Hyunglae Roh , Samsung Electronics, Yongin-City, Kyunggi-Do, Korea
Byeongwhee Yun , Samsung Electronics, Yongin-City, Kyunggi-Do, Korea
Yuntae Lee , Samsung Electronics, Yongin-City, Kyunggi-Do, Korea
pp. 611-616

Semi-Formal Test Generation with Genevieve (Abstract)

Mike Benjamin , STMicroelectronics, UK
Daniel Geist , IBM Corp, MATAM, Haifa, Israel
Julia Dushina , STMicroelectronics, UK
pp. 617-622

A Transaction-Based Unified Simulation/Emulation Architecture for Functional Verification (Abstract)

Charles Selvidge , IKOS Systems Inc.
Soha Hassoun , Tufts University
Duaine Pryor , IKOS Systems Inc.
Murali Kudlugi , IKOS Systems Inc.
pp. 623-628
Session 39 - Integrated High-Level Synthesis Based Solutions

Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints (Abstract)

Ranga Vemuri , University of Cincinnati, OH
Alex Doboli , State University of New York at Stony Brook
pp. 629-634

Integrating Scheduling and Physical Design Into a Coherent Compilation Cycle for Reconfigurable Computing Architectures (Abstract)

Kia Bazargan , University of Minnesota, Minneapolis
Seda Ogrenci , UCLA, Los Angeles, CA
Majid Sarrafzadeh , UCLA, Los Angeles, CA
pp. 635-640

Statistical Design Space Exploration for Application-Specific Unit Synthesis (Abstract)

Alessandro Bogliolo , DEIS - University of Bologna, Italy
Davide Bruni , DEIS - University of Bologna, Italy
Luca Benini , DEIS - University of Bologna, Italy
pp. 641-646
Session 40 - Timing Verification and Simulation

Static Schedluing of Multiple Asynchronous Domains for Functional Verification (Abstract)

Murali Kudlugi , IKOS Systems Inc., Waltham, MA
Charles Selvidge , IKOS Systems Inc., Waltham, MA
Russell Tessier , University of Massachusetts, Amherst
pp. 647-652

Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara
Tong Xiao , Sun Microsystems, Inc., Palo Alto, CA
pp. 653-656

An Advanced Timing Characterization Method using Mode Dependecy (Abstract)

Mohammad Mortazavi , Cadence Design Systems, San Jose, CA
John Hayes , University of Michigan, Ann Arbor
Cyrus Bamji , Canesta Inc., Santa Clara, CA
Robert Palermo , Cadence Design Systems, San Jose, CA
Karem Sakallah , University of Michigan, Ann Arbor
Hakan Yalcin , Cadence Design Systems, San Jose, CA
pp. 657-660

Fast Statistical Timing Analysis by Probabilistic Event Propagation (Abstract)

Angela Krstic , University of California, Santa Barbara
Kwang-Ting Cheng , University of California, Santa Barbara
Jing-Jia Liou , University of California, Santa Barbara
Sandip Kundu , Intel Corporation, Austin
pp. 661-666
Session 41 - On-Chip Communication Architectures

Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Eesign (Abstract)

A. Mihal , University of California at Berkeley
S. Malik , Princeton University
K. Keutzer , University of California at Berkeley
M. Sheets , University of California at Berkeley
M. Sgroi , University of California at Berkeley
J. Rabaey , University of California at Berkeley
A. Sangiovanni-Vencentelli , University of California at Berkeley
pp. 667-672

Micronetwork-Based Integration for SOCs (Abstract)

Drew Wingard , Sonics, Inc., Mountain View, CA
pp. 673-677

On-Chip Communication Architecture for OC-768 Network Processors (Abstract)

Ramesh Rao , Univ. of CA, San Diego
Anh Nguyen , STMicroelectronics Inc., San Diego, CA
Faraydon Karim , STMicroelectronics Inc., San Diego, CA
Sujit Dey , Univ. of CA, San Diego
pp. 678-683

Route Packets, Net Wires: On-Chip Inteconnectoin Networks (Abstract)

Brian Towles , Stanford University, CA
William J. Dally , Stanford University, CA
pp. 684-689
Session 42 - Compiler and Architecture Interactions

Dynamic Management of Scratch-Pad Memory Space (Abstract)

A. Parikh , The Pennsylvania State University
J. Ramanujam , Louisiana State University, Baton Rouge, LA
N. Vijaykrishnan , The Pennsylvania State University
M. Kandemir , The Pennsylvania State University
I. Kadayif , The Pennsylvania State University
J. Irwin , The Pennsylvania State University
pp. 690-695

Clustered VLIW Architecture with Predicated Switching (Abstract)

Satish Pillai , The University of Texas at Austin, Austin
Margarida F. Jacome , The University of Texas at Austin, Austin
Gustavo de Veciana , The University of Texas at Austin, Austin
pp. 696-701

High-Quality Operation Binding for Clustered VLIW Datapaths (Abstract)

Margarida F. Jacome , The University of Texas at Austin
Viktor S. Lapinskii , The University of Texas at Austin
Gustavo A. de Veciana , The University of Texas at Austin
pp. 702-707

Fast Bit-Rrue Simulation (Abstract)

Holger Keding , Aachen University of Technology, Germany
Martin Coors , Aachen University of Technology, Germany
Olaf L? , Aachen University of Technology, Germany
Heinrich Meyr , Aachen University of Technology, Germany
pp. 708-713
Session 43 - Timing with Crosstalk

Timing Analysis with Crosstalk as Fixpoints on Complete Lattice (Abstract)

William Nicholls , Synopsys, Inc., Mountain View, CA
Narendra Shenoy , Synopsys, Inc., Mountain View, CA
Hai Zhou , Synopsys, Inc., Mountain View, CA
pp. 714-719

Driver Modeling and Alignment for Worst-Case Delay Noise (Abstract)

Vladimir Zolotov , Motorola Inc. Austin, TX
Chanhee Oh , Motorola Inc. Austin, TX
Supamas Sirichotiyakul , Motorola Inc. Austin, TX
David Blaauw , Motorola Inc. Austin, TX
Jingyan Zuo , Motorola Inc. Austin, TX
Rafi Levy , Motorola Semiconductor Israel Ltd. Tel Aviv, Israel
pp. 720-725

False Coupling Interactions in Static Timing Analysis (Abstract)

Ronald D. Blanton , Carnegie Mellon University, Pittsburgh, PA
Ravishankar Arunachalam , IBM Corporation, Austin, TX
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
pp. 726-731

Coupling Delay Optimization by Temporal Decorrelation Using Dual Threshold Voltage Technique (Abstract)

Prashant Saxena , Intel Corporation, Hillsboro, Oregon
C. L. Liu , National Tsing Hua University, Taiwan
Ki-Wook Kim , Pluris, Incorporation, Cupertino, California
Seong-Ook Jung , University of Illinois at Urbana-Champaign
Sung-Mo Kang , University of California at Santa Cruz
pp. 732-737
Session 44 - Low Power Design: Systems to Interconnect

Input Space Adaptive Design: a High-Level Methodology for Energy and Performance Optimization (Abstract)

Anand Raghunathan , NEC, C&C Research Labs, Princeton, NJ
Niraj K. Jha , Princeton University, NJ
Ganesh Lakshminarayana , NEC, C&C Research Labs, Princeton, NJ
Weidong Wang , Princeton University, NJ
pp. 738-743

A{2}BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs (Abstract)

Haris Lekatsas , C&C Research Laboratories, NEC USA, Princeton, NJ
J? Henkel , C&C Research Laboratories, NEC USA, Princeton, NJ
pp. 744-749

Coupling-Driven Bus Design for Low-Power Application-Specific Systems (Abstract)

Takayasu Sakurai , University of Tokyo, Japan
Youngsoo Shin , University of Tokyo, Japan
pp. 750-753

Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies (Abstract)

Clark N. Taylor , University of California, San Diego
Yi Zhao , University of California, San Diego
Sujit Dey , University of California, San Diego
pp. 754-757

A True Single-Phase 8-bit Adiabatic Multiplier (Abstract)

Marios C. Papaefthymiou , University of Michigan, Ann Arbor
Suhwan Kim , T. J. Watson Research Center, Yorktown Heights, NY
Conrad H. Ziesler , University of Michigan, Ann Arbor
pp. 758-763
Session 45 - Floorplanning Representations and Placement Algorithms

TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans (Abstract)

Yao-Wen Chang , National Chiao Tung University, Taiwan
Jai-Ming Lin , National Chiao Tung University, Taiwan
pp. 764-769

Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List (Abstract)

Sheqin Dong , Tsinghua University, Beijing, China
Xianlong Hong , Tsinghua University, Beijing, China
Jun Gu , Science & Technology University of Hong Kong
Yuchun Ma , Tsinghua University, Beijing, China
Chung-Kuan Cheng , University of California, San Diego
Yici Cai , Tsinghua University, Beijing, China
pp. 770-775

Improved Cut Sequences for Partitioning based Placement (Abstract)

Patrick H. Madden , State University of New York at Binghamton
Mehmet Can Yildiz , State University of New York at Binghamton
pp. 776-779

Timing Driven Placement using Physical Net Constraints (Abstract)

Bill Halpin , Design Technology, Intel, Santa Clara, CA
C. Y. Roger Chen , Syracuse University, NY
Naresh Sehgal , EPD, Intel, Santa Clara, CA
pp. 780-783

From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip (Abstract)

A. Macii , Politecnico di Torino, Italy
L. Benini , Universit? di Bologna, Italy
L. Macchiarulo , Politecnico di Torino, Italy
M. Poncino , Politecnico di Torino, Italy
E. Macii , Politecnico di Torino, Italy
pp. 784-789
Session 46 - Panel: What Drives EDA Innovation?
Session 47 - Signal Integrity: Avoidance and Test Techniques

Built-In Self-Test for Signal Integrity (Abstract)

Amir Attarha , The University of Texas at Dallas
Mehrdad Nourani , The University of Texas at Dallas
pp. 792-797

Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk (Abstract)

Yehia Massoud , Synopsys Inc., Mountain View, CA
Don MacMillen , Synopsys Inc., Mountain View, CA
Jamil Kawa , Synopsys Inc., Mountain View, CA
Jacob White , MIT, Cambridge, MA
pp. 804-809
Session 48 - Novel Approaches to Microprocessor Design and Verification

Automated Pipeline Design (Abstract)

Daniel Kroening , University of Saarland, Germany
Wolfgang J. Paul , University of Saarland, Germany
pp. 810-815

A New Verification Methodology for Complex Pipeline Behavior (Abstract)

Nobu Matsumoto , Toshiba Corporation Semiconductor Company, Japan
Kazuyoshi Kohno , Toshiba Corporation Semiconductor Company, Japan
pp. 816-821

Pre-Silicon Verification of the Alpha 21364 Microprocessor Error Handling System (Abstract)

Benjamin Tsien , Compaq Computer Corporation
Richard Lee , Compaq Computer Corporation
pp. 822-827
Session 49 - Scheduling Techniques for Power Management

Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors (Abstract)

Gang Quan , University of Notre Dame, IN
Xiaobo Hu , University of Notre Dame, IN
pp. 828-833

Dynamic Power Management in a Mobile Multimedia System with Guaranteed Quality-of-Service (Abstract)

Massoud Pedram , University of Southern California, Los Angeles
Qing Wu , University of Southern California, Los Angeles
Qinru Qiu , University of Southern California, Los Angeles
pp. 834-839

Power-Aware Scheduling Under Timing Constraints for Mission-Critical Embedded Systems (Abstract)

Fadi Kurdahi , University of California at Irvine
Nader Bagherzadeh , University of California at Irvine
Pai H. Chou , University of California at Irvine
Jinfeng Liu , University of California at Irvine
pp. 840-845
Session 50 - Novel Devices and Yield Optimization

Exploring SOI Device Structures and Interconnect Architecures for 3-Dimensional Integration (Abstract)

David B. Janes , Purdue University, West Lafayette, IN
Cheng-Kok Koh , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Rongtian Zhang , Purdue University, West Lafayette, IN
pp. 846-851

Two-Dimensional Position Deteciton System with MEMS Accelerometer for MOUSE Applications (Abstract)

Junseok Chae , University of Michigan, Ann Arbor
Seungbae Lee , University of Michigan, Ann Arbor
Alan J. Drake , University of Michigan, Ann Arbor
Gi-Joon Nam , University of Michigan, Ann Arbor
Hanseup Kim , University of Michigan, Ann Arbor
pp. 852-857

Mismatch Analysis and Direct Yield Optimization by Specwise Linearization and Feasibility-Guided Search (Abstract)

Michael Pronath , Technical University of Munich, Germany
Frank Schenkel , Technical University of Munich, Germany
Robert Schwencker , Technical University of Munich, Germany; Infineon Technologies AG, Munich, Germany
Helmut Graeb , Technical University of Munich, Germany
Stephen Zizala , Technical University of Munich, Germany; Infineon Technologies AG, Munich, Germany
Kurt Antreich , Technical University of Munich, Germany
pp. 858-863

Author Index (PDF)

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