The Community for Technology Leaders
Design Automation Conference (2000)
Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
TABLE OF CONTENTS

Fast power grid simulation (PDF)

S.R. Nassif , IBM Austin Research Laboratory
pp. 156-161

Call for Papers (PDF)

pp. xxi
Session 4: Interconnect Modeling

A Practical Approach to Parasitic Extraction for Design of Multimillion-Transistor Integrated Circuits (Abstract)

John MacDonald , Mentor Graphics, OR
Lakshminarasimh Varadadesikan , Sun Microsystems, Palo Alto, CA
Wieze Xie , Hewlett-Packard, CA
Eileen You , Sun Microsystems, Palo Alto, CA
pp. 69-74

A Rank-One Update Method for Efficient Processing of Interconnect Parasitics in Timing Analysis (Abstract)

Jacob White , Massachusetts Institute of Technology, Cambridge, MA
W. Scott , Synopsys, Mountain View, CA
D. MacMillen , Synopsys, Mountain View, CA
H. Levy , Synopsys, Mountain View, CA
pp. 75-78

On Switch Factor Based Analysis of Coupled RC Interconnects (Abstract)

Sudhakar Muddu , Silicon Graphics, Inc., Mountain View, CA
Egino Sarto , 3dfx Interactive, Inc., San Jose, CA
Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
pp. 79-84
Session 7: Formal Verification

Formal Verification of Superscale Microprocessors with Multicycle Functional Units, Exception, and Branch Prediction (Abstract)

Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
Miroslav N. Velev , Carnegie Mellon University, Pittsburgh, PA
pp. 112-117
Session 8: Test Issues for Deep-Submicron System-on-Chips

System Chip Test: How will it Impact Your Design? (Abstract)

Erik Jan Marinissen , Philips Research Laboratories, The Netherlands
Yervant Zorian , LogicVision, Inc., San Jose, CA
pp. 136-141

Test Challenges for Deep Sub-Micron Technologies (Abstract)

Kaushik Roy , Purdue University, W. Lafayette, IN
Mike Rodgers , Intel Corp., Santa Clara, CA
Sujit Dey , Univ. of California, San Diego
Kwang-Ting Cheng , Univ. of California, Santa Barbara
pp. 142-149

Wave-steering one-hot encoded FSMs (PDF)

L. Macchiarulo , University of California
pp. 357-360
Session 9: Clock and Power Grid Analysis for High Performance Designs

Impact of Interconnect Variations on the Clock Skew of a Gigahertz Microprocessor (Abstract)

Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Andrzej J. Strojwas , Carnegie Mellon University, Pittsburgh, PA
Sani R. Nassif , IBM Austin Research Lab, Austin, TX
Ying Liu , Carnegie Mellon University, Pittsburgh, PA
pp. 168-171
Session 13: Design Methods for Emerging Technologies

Multiple Si Layer ICs: Motivation, Performance Analysis, and Design Implications (Abstract)

Kaustav Banerjee , Stanford University, CA
Amit Mehrotra , University of Illinois, Urbana-Champaign
Krishna C. Saraswat , Stanford University, CA
Shukri J. Souri , Stanford University, CA
pp. 213-220
Session 14: Signal Integrity

Dynamic Noise Analysis in Precharge-Evaluate Circuits (Abstract)

Kaushik Roy , Purdue University, W. Lafayette, IN
Seung Hoon Choi , Purdue University, W. Lafayette, IN
Vivek De , Intel Corp. Hillsboro, OR
Yibin Ye , Intel Corp. Hillsboro, OR
Dinesh Somasekhar , Purdue University, W. Lafayette, IN
pp. 243-246

Extended Krylov Subspace Method for Reduced Order Analysis of Linear Circuits with Multiple Sources (Abstract)

Tuyen V. Nguyen , IBM Austin Research Laboratory, Austin, TX
Janet M. Wang , University of California at Berkeley
pp. 247-252
Session 15: Panel: EDA Mees .COM: How E-Services Will Change the EDA Business Model
Session 16: Timing Analysis and Verification

Symbolic Timing Simulation using Cluster Scheduling (Abstract)

Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
Clayton B. McDonald , Carnegie Mellon University, Pittsburgh, PA
pp. 254-259

Critical Path Analysis using a Dynamically Bounded Delay Model (Abstract)

Soha Hassoun , Tufts University, Medford, MA
pp. 260-265
Session 16: Timing Analysis and Verification

Removing User Specified False Paths from Timing Graphs (Abstract)

Abhijit Das , Motorola, Inc., Austin, TX
Rajendran Panda , Motorola, Inc., Austin, TX
David Blaauw , Motorola, Inc., Austin, TX
pp. 270-273
Session 17: Logic/Physical Co-Design

Domino Logic Synthesis Minimizing Crosstalk (Abstract)

Sung-Mo Kang , University of Illinois at Urbana-Champaign, IL
Unni Narayanan , Intel Corporation, Santa Clara, CA
Ki-Wook Kim , University of Illinois at Urbana-Champaign, IL
pp. 280-285
Session 17: Logic/Physical Co-Design

Depth Optimal Incremental Mapping for Field Programmable Gate Arrays (Abstract)

Hui Huang , Stanford University, CA
Jason Cong , University of California, Los Angeles
pp. 290-293
Session 18: Power Analysis and Optimization for Embedded Software

Synthesis of Application-Specific Memories for Power Optimization in Embedded Systems (Abstract)

Alberto Macii , Politecnico di Torino, Italy
Massimo Poncino , Politecnico di Torino, Italy
Enrico Macii , Politecnico di Torino, Italy
Luca Benini , Universit? di Bologna, Italy
pp. 300-303
Session 18: Power Analysis and Optimization for Embedded Software

Power Analysis of Embedded Operating Systems (Abstract)

Anand Raghunathan , CCRL-NEC USA, Princeton, NJ
Niraj K. Jha , Princeton University, Princeton, NJ
Ganesh Lakshminarayana , CCRL-NEC USA, Princeton, NJ
Robert P. Dick , Princeton University, Princeton, NJ
pp. 312-315
Session 19: Embedded Compilation Techniques

Interactive Co-Design of High Throughput Embedded Multimedia (Abstract)

Thierry Franzetti , IMEC-DESICS, Leuven, Belgium
Francky Catthoor , IMEC-DESICS, Leuven, Belgium
Thierry J.-F. Omn? , IMEC-DESICS, Leuven, Belgium
pp. 328-331
Plenary Panel: Embedded Systems Design in the New Millenium
Session 21: New Techniques in Power Estimation and Performance Improvement

Dynamic Power Management of Complex Systems using Generalized Stochastic Petri Nets (Abstract)

Massoud Pedram , University of Southern California, Los Angeles
Qing Wu , University of Southern California, Los Angeles
Qinru Qiu , University of Southern California, Los Angeles
pp. 352-356
Session 22: Combined Global Routing, Buffering and Wiresizing

A Current Driven Routing and Verification Methodology for Analog Applications (Abstract)

Hiltrud Brocke , University of Hanover, Germany
Lars Hedrich , University of Hanover, Germany
Erich Barke , University of Hanover, Germany
Thorsten Adler , Infineon Technologies AG, Munich, Germany
pp. 385-389
Session 23: Advances in System Modeling and Synthesis

A Codesign Virtual Machine for Hierarchical, Balanced Hardware/Software System Modeling (Abstract)

Simon N. Peffers , Carnegie Mellon University, Pittsburgh, PA
Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
JoAnn M. Paul , Carnegie Mellon University, Pittsburgh, PA
pp. 390-395

The role of custom design in ASIC chips (PDF)

W.J. Daily , Stanford University
pp. 643-647
Session 23: Advances in System Modeling and Synthesis

Application-Specific Memory Management for Embedded Systems Using Software-Controlled Caches (Abstract)

Larry Rudolph , Massachusetts Institute of Technology, Cambridge, MA
Prabhat Jain , Massachusetts Institute of Technology, Cambridge, MA
Srinivas Devadas , Massachusetts Institute of Technology, Cambridge, MA
Derek Chiou , Massachusetts Institute of Technology, Cambridge, MA
pp. 416-419
Session 24: Designing Systems on a Chip

Verification of Configurable Processor Cores (Abstract)

Pavlos Konas , Tensilica, Inc., Santa Clara, CA
G? Ezer , Tensilica, Inc., Santa Clara, CA
Marin? Puig-Medina , Tensilica, Inc., Santa Clara, CA
pp. 426-431
Session 26: Mixed Signal Design and Analysis

High-Level Simulation of Substrate Noise Generation Including Power Supply Noise Coupling (Abstract)

Ivo Bolsens , IMEC, Leuven, Belgium
Marc Engels , IMEC, Leuven, Belgium
Mustafa Badaroglu , IMEC, Leuven, Belgium
St?phane Donnay , IMEC, Leuven, Belgium
Marc van Heijningen , IMEC, Leuven, Belgium
pp. 446-451
Session 27: Floorplanning & Placement

Timing-Driven Placement based on Partitioning with Dynamic Cut-Net Control (Abstract)

Massoud Pedram , University of Southern California, Los Angeles
Shih-Lian Ou , University of Southern California, Los Angeles
pp. 472-476
Session 28: System Level Scheduling

Task Scheduling with RT Constraints (Abstract)

A. Sangiovanni-Vincentelli , Univ. of California at Berkeley
F. Balarin , Cadence Berkeley Labs, Berkeley, CA
M. Di Natale , Universit? degli Studi di Pisa, Italy
pp. 483-488

Large-scale capacitance calculation (PDF)

S. Kapur , Bell Laboratories
pp. 744-749
Session 29: Architectures for Embedded Systems

System Design of Active Basestations based on Dynamically Reconfigurable Hardware (Abstract)

Mani B. Srivastava , Dept. of Electrical Eng. at UCLA, Los Angeles, CA
Athanassios Boulis , Dept. of Electrical Eng. at UCLA, Los Angeles, CA
pp. 501-506
Session 30: Panel: Embedded Systems Education

Power minimization using control generated clocks (PDF)

M.S. Rao , Indian Institute of Science
pp. 794-799
Session 32: High Level Synthesis for DSPs: Data Intensive Applications

On Lower Bounds for Scheduling Problems in High-Level Synthesis (Abstract)

J. Ramanujam , Louisiana State University, Baton Rouge, LA
M. Narasimhan , Intel Corporation, Dupont, WA
pp. 546-551

Efficient Building Block Based RTL Code Generation from Synchronous Data Flow Graphs (Abstract)

Heinrich Meyr , Integrated Signal Processing Systems, RWTH Aachen, Germany
Jens Horstmannshoff , Integrated Signal Processing Systems, RWTH Aachen, Germany
pp. 552-555

System-Level Data Format Exploration for Dynamically Allocated Data Structures (Abstract)

Ahmed Hemani , ESD, KTH, Sweden
Miguel Miranda , IMEC, Belgium
Francky Catthoor , IMEC, Belgium; Katholieke Universiteit Leuven
Peeter Ellervee , ESD, KTH, Sweden
pp. 556-559
Session 33: Embedded Tutorial: MOSFET Modeling and Circuit Design: Re-Establishing a Lost Connection
Session 34: Reconfigurable Computing Systems

Using General-Purpose Programming Languages for FPGA Design (Abstract)

Brent E. Nelson , Brigham Young University, Provo, UT
Brad L. Hutchings , Brigham Young University, Provo, UT
pp. 561-566

An Architecture-Driven Detric for Simultaneous Placement and Global Routing for FPGAs (Abstract)

Yu-Tsang Chang , Chip Implementation Center, National Science Council of Taiwan, Taiwan
Yao-Wen Chang , National Chiao Tung University, Taiwan
pp. 567-572

MorphoSys: Case Study of a Reconfigurable Computing System Targeting Multimedia Applications (Abstract)

Guangming Lu , University of California, Irvine
Ming-Hau Lee , University of California, Irvine
Nader Bagherzadeh , University of California, Irvine
Rafael Maestre , Universidad Complutense, Madrid, Spain
Eliseu Filho , COPPE/Federal University of Rio De Janeiro, Brazil
Fadi Kurdahi , University of California, Irvine
Hartej Singh , University of California, Irvine
pp. 573-578
Session 35: Panel: Survival Strategies for Mixed-Signal Systems-On-Chip
Session 36: Intellectual Property Protection & Re-Use

Forensic Engineering Techniques for VLSI CAD Tools (Abstract)

Jennifer Wong , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
David Liu , University of California, Los Angeles
Darko Kirovski , University of California, Los Angeles
pp. 581-586

Fingerprinting Intellectual Property using Constraint-Addition (Abstract)

Miodrag Potkonjak , University of California, Los Angeles
Gang Qu , University of California, Los Angeles
pp. 587-592

Hardware/Software IP protection (Abstract)

Marcello Dalpasso , DEI - University of Padova, Italy
Alessandro Bogliolo , DI - University of Ferrara, Italy
Luca Benini , DEIS - University of Bologna, Italy
pp. 593-596

A Web-CAD Methodology for IP-Core Analysis and Simulation (Abstract)

Franco Fummi , Universit? di Verona, Italy
Alessandro Fin , Universit? di Verona, Italy
pp. 597-600
Session 37: Correctness Issues in High Level Synthesis

Optimizing Sequential Verification by Retiming Transformations (Abstract)

Stefano Quer , Politecnico di Torino, Italy
Fabio Somenzi , University of Colorado, Boulder
Gianpiero Cabodi , Politecnico di Torino, Italy
pp. 601-606

Efficient Methods for Embedded System Design Space Exploration (Abstract)

Alberto Sangiovanni-Vincentelli , University of California at Berkeley
Luciano Lavagno , Politecnico di Torino, Italy
Felice Balarin , Cadence Berkeley Laboratories, USA
Harry Hsieh , University of California at Berkeley
pp. 607-612

Synthesis-for-Testability of Controller-Datapath Pairs that use Gated Clocks (Abstract)

Joan Carletta , The Univ. of Akron, OH
Christos Papachristou , Case Western Reserve Univ., Cleveland, OH
Mehrdad Nourani , The Univ. of Texas at Dallas
pp. 613-618
Session 38: SOC Test Methodologies and Defect Modelling

Self-Test Methodology for At-Speed Test of Crosstalk in Chip Interconnects (Abstract)

Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
Sujit Dey , University of California, San Diego
Xiaoliang Bai , University of California, San Diego
pp. 619-624

Embedded Hardware and Software Self-Testing Methodologies for Processor Cores (Abstract)

Krishna Sekar , University of California at San Diego
Pablo Sanchez , University of Cantabria, Santander, Spain
Sujit Dey , University of California at San Diego
Ying Cheng , University of California at San Diego
Li Chen , University of California at San Diego
pp. 625-630

Modeling and Simulation of Real Defects using Fuzzy Logic (Abstract)

Mehradad Nourani , The Univ. of Texas at Dallas
Carco Lucas , The Univ. of Tehran, Iran
Amir Attarha , The Univ. of Texas at Dallas
pp. 631-636
Session 39: Embedded Tutorial: Bridging the Gap Between Full Custom and AISC Design

Closing the Gap Between ASIC and Custom: an ASIC Perspective (Abstract)

K. Keutzer , University of California at Berkeley
D. G. Chinnery , University of California at Berkeley
pp. 637-642

The Role of Custom Design in ASIC Chips (Abstract)

Andrew Chang , Stanford University, CA
Willaim J. Dally , Stanford University, CA
pp. 643-647
Session 40: Panel: Case Studies: Chip Design on the Bleeding Edge
Session 41: Layout Optimization

MINFLOTRANSIT: Min-Cost Flow based Transistor Sizing Tool (Abstract)

Keshab K. Parhi , University of Minnesota, Minneapolis
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Vijay Sundararajan , University of Minnesota, Minneapolis
pp. 649-664

Convex Delay Models for Transistor Sizing (Abstract)

Kishore Kasamsetty , University of Minnesota, Minneapolis
Sachin Sapatnekar , University of Minnesota, Minneapolis
Mahesh Ketkar , University of Minnesota, Minneapolis
pp. 655-660

Macro-Driven Circuit Design Methodology for High-Performance Datapaths (Abstract)

Vivek Tiwari , Intel Corporation, Santa Clara, CA
Mahadevamurty Nemani , Intel Corporation, Santa Clara, CA
pp. 661-666

Model-Based Dummy Feature Placement for Oxide Chemical-Mechanical Polishing Manufacturability (Abstract)

Robert Boone , Motorola Inc., Austin, TX; University of Texas at Austin
D. F. Wong , University of Texas at Austin, TX
Ruiqi Tian , University of Texas at Austin, TX; Motorola Inc., Austin, TX
pp. 667-670

Practical Iterated Fill Synthesis for CMP Uniformity (Abstract)

Alexander Zelikovsky , Georgia State University, Atlanta, GA
Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
Gabriel Robins , University of Virginia, Charlottesville, VA
Yu Chen , UCLA Computer Science Dept., Los Angeles, CA
pp. 671-674
Session 42: Decision Procedures for cAD Problems

Boolean Satisfiability in Electronic Design Automation (Abstract)

Karem A. Sakallah , University of Michigan, Ann Arbor, Michigan
Jo?o P. Marques-Silva , Technical University of Lisbon, IST/INESC, Lisbon, Portugal
pp. 675-680

Analysis of Composition Complexity and how to Obtain Smaller Canonical Graphs (Abstract)

I. Wegener , Universitaet Dortmund, Germany
K. Mohanram , University of Texas, Austin
Y. Lu , Carnegie Mellon University, Pittsburgh, PA
D. Moundanos , Fujitsu Labs of America, Sunnyvale, CA
J. Jain , Fujitsu Labs of America, Sunnyvale, CA
pp. 681-686

Efficient Variable Ordering using aBDD based Sampling (Abstract)

Jawahar Jain , Fujitsu Laboratories of America
Masahiro Fujita , Fujitsu Laboratories of America
Edmund Clarke , Carnegie Mellon University
Yuan Lu , Carnegie Mellon University
pp. 687-692
Session 43: New Frameworks for the EDA Field

GTX: the MARCO GSRC Technology Extrapolation System (Abstract)

Hua Lu , UC Berkeley EECS Dept., USA
Igor L. Markov , UCLA CS Dept., USA
Andrew B. Kahng , UCLA CS Dept., USA
Michael Oliver , UCLA CS Dept., USA
Yu Cao , UC Berkeley EECS Dept., USA
Dennis Sylvester , Synopsis, Inc., USA
Dirk Stroobandt , Ghent University ELIS Dept., Belgium
Farinaz Koushanfar , UCLA CS Dept., USA
Andrew E. Caldwell , UCLA CS Dept., USA
pp. 693-698

A System Simulation Framework (Abstract)

N. W. Schellingerhout , Philips Research Laboratories Eindhoven, The Netherlands
P. Bingley , Philips Research Laboratories Eindhoven, The Netherlands
W. P. M. van der Linden , Philips Research Laboratories Eindhoven, The Netherlands
P. van den Hamer , Philips Research Laboratories Eindhoven, The Netherlands
pp. 699-704

METRICS: a System Architecture for Design Process Optimization (Abstract)

Andrew B. Kahng , OxSigen LLC, San Jose, California
Stefanus Mantik , OxSigen LLC, San Jose, California
Bart Thielges , UCLA Computer Science Dept., Los Angeles, CA
David George , UCLA Computer Science Dept., Los Angeles, CA
Stephen Fenstermaker , UCLA Computer Science Dept., Los Angeles, CA
pp. 705-710
Session 44: High Performance Microprocessor Design

Timing Closure by Design, a High Frequency Microprocessor Design Methodology (Abstract)

J. Park , Samsung, Korea
J. Peter , IBM Austin Research Lab, Austin, TX
J. Silberman , IBM Watson Research Lab, Yorktown, NY
K. Lee , Sun Microsystems, CA
K. Nowka , IBM Austin Research Lab, Austin, TX
N. Aoki , IBM Austin Research Lab, Austin, TX
N. Kojima , IBM Austin Research Lab, Austin, TX
O. Kwon , IBM Austin Research Lab, Austin, TX
O. Takahashi , IBM Austin Research Lab, Austin, TX
P. Coulman , IBM Server Division, Austin, TX
P. Hofstee , IBM Austin Research Lab, Austin, TX
P. Villarrubia , IBM Server Division, Austin, TX
B. Flachs , Motorola, Austin, TX
S. Dhong , IBM Austin Research Lab, Austin, TX
D. Boerstler , IBM Austin Research Lab, Austin, TX
D. Meltzer , IBM Watson Research Lab, Yorktown, NY
S. Posluszny , IBM Austin Research Lab, Austin, TX
pp. 712-717

A Methodology for Formal Design of Hardware Control with Application to Cache Coherence Protocols (Abstract)

Irit Shitsevalov , IBM Haifa Research Laboratory, Israel
Ken Valk , IBM Rochester, MN
Kyle Nelson , IBM Rochester, MN
Russ Hoover , IBM Rochester, MN
Wayne Nation , IBM Rochester, MN
Cindy Eisner , IBM Haifa Research Laboratory, Israel
pp. 724-729

CGaAs PowerPC FXU (Abstract)

Keith L. Kraver , University of Michigan, Ann Arbor
P. Sean Stetson , University of Michigan, Ann Arbor
Phiroze N. Parakh , University of Michigan, Ann Arbor
Richard B. Brown , University of Michigan, Ann Arbor
Spencer M. Gold , University of Michigan, Ann Arbor
Todd D. Basso , University of Michigan, Ann Arbor
Claude R. Gauthier , University of Michigan, Ann Arbor
Alan J. Drake , University of Michigan, Ann Arbor
pp. 730-735
Session 45: Panel: When Bad Things Happen to Good Chips
Session 46: Large-Scale Parasitic Analysis

Fast Methods for Extraction and Sparsification of Substrate Coupling (Abstract)

Jacob White , Massachusetts Institute of Technology, Cambridge
Joel Phillips , Cadence Berkeley Laboratories, San Jose, CA
Joe Kanapka , Massachusetts Institute of Technology, Cambridge
pp. 738-743

Large-Scale Capacitance Calculation (Abstract)

David E. Long , Lucent Technologies, Murray Hill, NJ
Sharad Kapur , Lucent Technologies, Murray Hill, NJ
pp. 744-749

Fast Temperature Calculation for Transient Electrothermal Simulation by Mixed Frequency/Time Domain Thermal Model Reduction (Abstract)

Sung-Mo Kang , University of Illinois at Urbana-Champaign
Ching-Han Tsai , University of Illinois at Urbana-Champaign
pp. 750-755
Session 47: Advances in High Level Synthesis

Unifying Behavioral Synthesis and Physical Design (Abstract)

Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
William E. Dougherty , Carnegie Mellon University, Pittsburgh, PA
pp. 756-761

The use of Carry-Save Representation in Joint Module Selection and Retiming (Abstract)

Alan N. Willson , University of California, Los Angeles
Kei-Yong Khoo , University of California, Los Angeles
Zhan Yu , University of California, Los Angeles
pp. 768-773
Session 48: Fault Simulation and Extraction of Low-Level Effects

Closing the Gap Between Analog and Digital (Abstract)

Naim Ben Hamida , Fluence Technology Inc., Beaverton, OR
Bozena Kaminska , Fluence Technology Inc., Beaverton, OR
Khaled Saab , Fluence Technology Inc., Beaverton, OR
pp. 774-779

A Switch Level Fault Simulation Environment (Abstract)

J. Casas , Intel Corporation, Hillsboro, OR
T. Tetzlaff , Intel Corporation, Hillsboro, OR
V. Krishnaswamy , Intel Corporation, Hillsboro, OR
pp. 780-785

Universal Fault Simulation using Fault Tuples (Abstract)

R. D. Blanton , Carnegie Mellon University, Pittsburgh, PA
Kumar N. Dwarakanath , Carnegie Mellon University, Pittsburgh, PA
pp. 786-789

A Novel Algorithm to Extract Two-Node Bridges (Abstract)

Sreejit Chakravarty , Intel Corporation, Santa Clara, CA
Carl D. Roth , Intel Corporation, Santa Clara, CA
Sujit T. Zachariah , Intel Corporation, Santa Clara, CA
pp. 790-793
Session 49: Low Power Design Techniques and Estimation

Power Minimization using Control Generated Clocks (Abstract)

S. K. Nandy , Indian Institute of Science, Bangalore, India
M. Srikanth Rao , Indian Institute of Science, Bangalore, India
pp. 794-799

Bus Encoding for Low-Power High-Performance Memory Systems (Abstract)

Jinsung Cho , Seoul National University, Korea
Kwanho Kim , Seoul National University, Korea
Naehyuck Chang , Seoul National University, Korea
pp. 800-805

Run-Time Voltage Hopping for Low-Power Real-Time Systems (Abstract)

Takayasu Sakurai , University of Tokyo, Japan
Seongsoo Lee , University of Tokyo, Japan
pp. 806-809

Function-Level Power Estimation Methodology for Microprocessors (Abstract)

Kimiyoshi Usami , Toshiba Corporation, Kawasaki, Japan
Miodrag Potkonjak , University of California, Los Angeles
Naoyuki Kawabe , Toshiba Corporation, Kawasaki, Japan
Gang Qu , University of California, Los Angeles
pp. 810-813
Session 50: Panel: Emerging Companies-Acquiring Minds Want to Know

Author Index (PDF)

pp. 817
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