The Community for Technology Leaders
Design Automation Conference (2000)
Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
TABLE OF CONTENTS

Reviewers (PDF)

pp. xvi

Call for Papers (PDF)

pp. xxi
Session 1: Analog and RF

A Case Study of Synthesis for Industrial-Scale Analog IP: Redesign of the Equalizer/Filter Frontend for an ADSL CODEC (Abstract)

Michael J. Krasnicki , Carnegie Mellon University, Pittsburgh, Pennsylvania
James R. Hellums , Mixed Signal Products, Texas Instruments Incorporated
L. Richard Carley , Carnegie Mellon University, Pittsburgh, Pennsylvania
Rodney Phelps , Carnegie Mellon University, Pittsburgh, Pennsylvania
Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 1-6

Optimal RF Design using Smart Evolutionary Algorithms (Abstract)

G. Gielen , Katholieke Universiteit Leuven, Belgium
C. De Ranter , Katholieke Universiteit Leuven, Belgium
M. Steyaert , Katholieke Universiteit Leuven, Belgium
Peter Vancorenland , Katholieke Universiteit Leuven, Belgium
pp. 7-10

CYCLONE: Automated Design and Layout of RF LC-Oscillators (Abstract)

G. Van der Plas , Katholieke Universiteit Leuven, Belgium
P. Vancorenland , Katholieke Universiteit Leuven, Belgium
G. Gielen , Flemish Fund for Scientific Research (FWO)
M. Steyaert , Katholieke Universiteit Leuven, Belgium
B. De Muer , Katholieke Universiteit Leuven, Belgium
C. De Ranter , Katholieke Universiteit Leuven, Belgium
W. Sansen , Katholieke Universiteit Leuven, Belgium
pp. 11-14

An Asymptotically Constant, Linearly Bounded Methodology for the Statistical Simulation of Analog Circuits Including Component Mismatch Effects (Abstract)

Patrick McNamara , PDF Solutions Inc., San Jose, CA
Phillip Schumaker , PDF Solutions Inc., San Jose, CA
Carlo Gaurdiani , PDF Solutions Inc., San Jose, CA
Sharad Saxena , PDF Solutions Inc., San Jose, CA
Dale Coder , PDF Solutions Inc., San Jose, CA
pp. 15-18

Multi-Terminal Determinant Decision Diagrams: A New Approach to Semi-Symbolic Analysis of Analog Integrated Circuits (Abstract)

C.-J. Richard Shi , University of Washington, Seattle, WA
Tao Pi , University of Washington, Seattle, WA
pp. 19-22
Session 2: BDD-Based Model Checking

To Split or to Conjoin: The Question in Image Computation (Abstract)

In-Ho Moon , University of Colorado, Boulder
James H. Kukula , Synopsys, Beaverton, OR
Fabio Somenzi , University of Colorado, Boulder
Kavita Ravi , Cadence, New Providence, NJ
pp. 23-28

Symbolic Guided Search for CTL Model Checking (Abstract)

Kavita Ravi , Cadence Design Systems, New Providence, NJ
Roderick Bloem , University of Colorado, Boulder
Fabio Somenzi , University of Colorado, Boulder
pp. 29-34

Lazy Symbolic Model Checking (Abstract)

Jin Yang , Intel Corp.
Andreas Tiemeyer , Design Technology, Intel Corp.
pp. 35-38

Distance Driven Finite State Machine Traversal (Abstract)

Christoph Scholl , Albert-Ludwigs-University, Germany
Bernd Becker , Albert-Ludwigs-University, Germany
Andreas Hett , Albert-Ludwigs-University, Germany
pp. 39-42
Session 3: Test Generation and Diagnosis

Automatic Test Pattern Generation for Functional RTL Circuits using Assignment Decision Diagrams (Abstract)

Indradeep Ghosh , Fujitsu Laboratories of America, Sunnyvale, CA
Masahiro Fujita , Fujitsu Laboratories of America, Sunnyvale, CA
pp. 43-48

Interconnect Testing in Cluster-Based FPGA Architectures (Abstract)

Ian G. Harris , University of Massachusetts, Amherst, MA
Russell Tessier , University of Massachusetts, Amherst, MA
pp. 49-54

Improved Fault Diagnosis in Scan-Based BIST via Superposition (Abstract)

Alex Orailoglu , University of California, San Diego
Ismet Bayraktaroglu , University of California, San Diego
pp. 55-58

On Diagnosis of Pattern-Dependent Delay Faults (Abstract)

Sudhakar M. Reddy , University of Iowa, Iowa City
Irith Pomeranz , University of Iowa, Iowa City
pp. 59-62
Session 4: Interconnect Modeling

On-Chip Inductance Modeling and Analysis (Abstract)

Junfeng Wang , Motorola Inc., Austin TX
Vladimir Zolotov , Motorola Inc., Austin TX
Brian Young , Motorola Inc., Austin TX
David Blaauw , Motorola Inc., Austin TX
Kaushik Gala , Motorola Inc., Austin TX
Rajendran Panda , Motorola Inc., Austin TX
pp. 63-68

A Practical Approach to Parasitic Extraction for Design of Multimillion-Transistor Integrated Circuits (Abstract)

Lakshminarasimh Varadadesikan , Sun Microsystems, Palo Alto, CA
John MacDonald , Mentor Graphics, OR
Eileen You , Sun Microsystems, Palo Alto, CA
Wieze Xie , Hewlett-Packard, CA
pp. 69-74

A Rank-One Update Method for Efficient Processing of Interconnect Parasitics in Timing Analysis (Abstract)

W. Scott , Synopsys, Mountain View, CA
H. Levy , Synopsys, Mountain View, CA
D. MacMillen , Synopsys, Mountain View, CA
Jacob White , Massachusetts Institute of Technology, Cambridge, MA
pp. 75-78

On Switch Factor Based Analysis of Coupled RC Interconnects (Abstract)

Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
Egino Sarto , 3dfx Interactive, Inc., San Jose, CA
Sudhakar Muddu , Silicon Graphics, Inc., Mountain View, CA
pp. 79-84
Session 5: Special Session: Life at the End of CMOS Scaling (and Beyond)
Session 6: New Techniques for Synthesis and Mapping

Area and Search Space Control for Technology Mapping (Abstract)

Robert K. Brayton , University of California, Berkeley, USA
Dirk-Jan Jongeneel , Delft University of Technology, The Netherlands
Yosinori Watanbe , Cadence Berkeley Labs, USA
Ralph Otten , Delft University of Technology, The Netherlands
pp. 86-91

BDS: A BDD-Based Logic Optimization System (Abstract)

Congguang Yang , University of Massachusetts, Amherst
Maciej Ciesielski , University of Massachusetts, Amherst
Vigyan Singhal , Tempus Fugit, Inc., Albany, CA
pp. 92-97

A Fine-Grained Arithmetic Optimization Technique for High-Performance/Low-Power Data Path Synthesis (Abstract)

Taewhan Kim , Korea Adv. Institute of Science & Technology, Taejon, Korea
Junhyung Um , Korea Adv. Institute of Science & Technology, Taejon, Korea
C. L. Liu , National Tsing Hua Univ., Hsinchu, Taiwan
pp. 98-103

Optimal Low PowerX OR Gate Decomposition (Abstract)

D. F. Wong , University of Texas, Austin
Hai Zhou , Synopsys Inc., Mountain View, CA
pp. 104-107

Watermarking while Preserving the Critical Path (Abstract)

Seapahn Meguerdichian , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 108-111
Session 7: Formal Verification

Formal Verification of Superscale Microprocessors with Multicycle Functional Units, Exception, and Branch Prediction (Abstract)

Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
Miroslav N. Velev , Carnegie Mellon University, Pittsburgh, PA
pp. 112-117

Assertion Checking by Combined Word-Level ATPG and Modular Arithmetic Constraint-Solving Techniques (Abstract)

Chung-Yang Huang , University of California, Santa Barbara, CA
Kwang-Ting Cheng , University of California, Santa Barbara, CA
pp. 118-123

Reliable Verification using Symbolic Simulation with Scalar Values (Abstract)

David L. Dill , Stanford University, CA
Chris Wilson , Stanford University, CA
pp. 124-129

Automatic Formal Verification of DSP Software (Abstract)

David W. Currie , Mentor Graphics, Billerica, MA
Masahiro Fujita , Fujitsu Laboratories of America, Sunnyvale, CA
Alan J. Hu , University of British Columbia, Vancouver
Sreeranga Rajan , Fujitsu Laboratories of America, Sunnyvale, CA
pp. 130-135
Session 8: Test Issues for Deep-Submicron System-on-Chips

System Chip Test: How will it Impact Your Design? (Abstract)

Yervant Zorian , LogicVision, Inc., San Jose, CA
Erik Jan Marinissen , Philips Research Laboratories, The Netherlands
pp. 136-141

Test Challenges for Deep Sub-Micron Technologies (Abstract)

Sujit Dey , Univ. of California, San Diego
Kaushik Roy , Purdue University, W. Lafayette, IN
Mike Rodgers , Intel Corp., Santa Clara, CA
Kwang-Ting Cheng , Univ. of California, Santa Barbara
pp. 142-149
Session 9: Clock and Power Grid Analysis for High Performance Designs

Hierarchical Analysis of Power Distribution Networks (Abstract)

David Blaauw , Motorola Inc., Austin, TX
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Min Zhao , Motorola Inc., Austin, TX
Rajendran V. Panda , Motorola Inc., Austin, TX
Rajat Chaudhry , Motorola Inc., Austin, TX
Tim Edwards , Motorola Inc., Austin, TX
pp. 150-155

Fast Power Grid Simulation (Abstract)

Joseph N. Kozhaya , University of Illinois, Urbana
Sani R. Nassif , IBM Austin Research Laboratory, Austin, TX
pp. 156-161

Current Signature Compression for IR-Drop Analysis (Abstract)

Tim Edwards , Motorola Inc., Austin-TX
David Blaauw , Motorola Inc., Austin-TX
Rajat Chaudhry , Motorola Inc., Austin-TX
Rajendran Panda , Motorola Inc., Austin-TX
pp. 162-167

Impact of Interconnect Variations on the Clock Skew of a Gigahertz Microprocessor (Abstract)

Sani R. Nassif , IBM Austin Research Lab, Austin, TX
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Andrzej J. Strojwas , Carnegie Mellon University, Pittsburgh, PA
Ying Liu , Carnegie Mellon University, Pittsburgh, PA
pp. 168-171

A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance (Abstract)

Anantha Chandrakasan , Massachusetts Institute of Technology, Cambridge, MA
Rakesh Vallishayee , PDF Solutions, San Jose, CA
Duane Boning , Massachusetts Institute of Technology, Cambridge, MA
Vikas Mehrotra , Massachusetts Institute of Technology, Cambridge, MA
Sani Nassif , IBM, Austin, TX
Shiou Lin Sam , Massachusetts Institute of Technology, Cambridge, MA
pp. 172-175
Session 10: Panel: Design Closure: Hope or Hype?
Session 11: Algorithms for RF Simulation and Model Reduction

A Multi-Interval Chebyshev Collocation Method for Efficient High-Accuracy RF Circuit Simulation (Abstract)

Baolin Yang , Cadence Design Systems, Inc., San Jose, CA
Joel Phillips , Cadence Design Systems, Inc., San Jose, CA
pp. 178-183

Projection Frameworks for Model Reduction of Weakly Nonlinear Systems (Abstract)

Joel R. Phillips , Cadence Berkeley Laboratories, San Jose, CA
pp. 184-189

A Realizable Driving Point Model for on-Chip Interconnect with Inductance (Abstract)

Byron L. Krauter , IBM Corporation, Austin, TX
Chandramouli V. Kashyap , IBM Corporation, Austin, TX
pp. 190-195
Session 12: Verification and Debugging Methodologies

Formal Verification of an IBM CoreConnect Processor Local bus Arbiter Core (Abstract)

William R. Lee , System Level Design Methodology Leader, IBM, ASICs, NC
Amit Goel , Hamerschlag Hall, Pittsburgh, PA
pp. 196-200

Formal Verification of Iterative Algorithms in Microprocessors (Abstract)

Mark D. Aagaard , Intel Corporation, Hillsboro, Oregon
Katherine R. Kohatsu , Intel Corporation, Hillsboro, Oregon
Roope Kaivola , Intel Corporation, Hillsboro, Oregon
Robert B. Jones , Intel Corporation, Hillsboro, Oregon
Carl-Johan H. Seger , Intel Corporation, Hillsboro, Oregon
pp. 201-206

Efficient Error Detection, Localization, and Correction for FPGA-Based Debugging (Abstract)

William H. Mangione-Smith , UCLA EE Department, Los Angeles, CA
Miodrag Potkonjak , UCLA CS Department, Los Angeles, CA
John Lach , UCLA EE Department, Los Angeles, CA
pp. 207-212
Session 13: Design Methods for Emerging Technologies

Multiple Si Layer ICs: Motivation, Performance Analysis, and Design Implications (Abstract)

Krishna C. Saraswat , Stanford University, CA
Kaustav Banerjee , Stanford University, CA
Shukri J. Souri , Stanford University, CA
Amit Mehrotra , University of Illinois, Urbana-Champaign
pp. 213-220

High-Level Model of a WDMA Passive Optical Bus for a Reconfigurable Multiprocessor System (Abstract)

V. E. Boros , The University of Queensland, Australia
A. D. Rakic , The University of Queensland, Australia
S. Parameswaran , The University of Queensland, Australia
pp. 221-226

A Design of and Design Tools for a Novel Quantum Dot Based Microprocessor (Abstract)

Peter M. Kogge , University of Notre Dame, IN
Michael J. Kontz , University of Notre Dame, IN
Michael T. Niemier , University of Notre Dame, IN
pp. 227-232
Session 14: Signal Integrity

ClariNet: A Noise Analysis Tool for Deep Submicron Design (Abstract)

Vladimir Zolotov , Motorola Inc., Austin, TX
Aurobindo Dasgupta , Motorola Inc., Austin, TX
Supamas Sirichotiyakul , Motorola Inc., Austin, TX
Rafi Levy , Motorola Semiconductor Israel Ltd. Tel Aviv, Israel
Chanlee Oh , Motorola Inc., Austin, TX
Boaz Orshav , Motorola Inc., Austin, TX
Gabi Braca , Motorola Semiconductor Israel Ltd. Tel Aviv, Israel
Amir Grinshpon , Motorola Semiconductor Israel Ltd. Tel Aviv, Israel
David Blaauw , Motorola Inc., Austin, TX
pp. 233-238

Static Noise Analysis for Digital Integrated Circuits in Partially-Depleted Silicon-on-Insulator Technology (Abstract)

Dae-Jin Kim , Columbia University, New York, NY
Kenneth L. Shepard , Columbia University, New York, NY
pp. 239-242

Dynamic Noise Analysis in Precharge-Evaluate Circuits (Abstract)

Dinesh Somasekhar , Purdue University, W. Lafayette, IN
Seung Hoon Choi , Purdue University, W. Lafayette, IN
Yibin Ye , Intel Corp. Hillsboro, OR
Kaushik Roy , Purdue University, W. Lafayette, IN
Vivek De , Intel Corp. Hillsboro, OR
pp. 243-246

Extended Krylov Subspace Method for Reduced Order Analysis of Linear Circuits with Multiple Sources (Abstract)

Janet M. Wang , University of California at Berkeley
Tuyen V. Nguyen , IBM Austin Research Laboratory, Austin, TX
pp. 247-252
Session 15: Panel: EDA Mees .COM: How E-Services Will Change the EDA Business Model
Session 16: Timing Analysis and Verification

Symbolic Timing Simulation using Cluster Scheduling (Abstract)

Clayton B. McDonald , Carnegie Mellon University, Pittsburgh, PA
Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
pp. 254-259

Critical Path Analysis using a Dynamically Bounded Delay Model (Abstract)

Soha Hassoun , Tufts University, Medford, MA
pp. 260-265

TACO: Timing Analysis with Coupling (Abstract)

Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Karthik Rajagopal , Intel Corporation, Santa Clara, CA
Ravishankar Arunachalam , Carnegie Mellon University, Pittsburgh, PA
pp. 266-269

Removing User Specified False Paths from Timing Graphs (Abstract)

Rajendran Panda , Motorola, Inc., Austin, TX
David Blaauw , Motorola, Inc., Austin, TX
Abhijit Das , Motorola, Inc., Austin, TX
pp. 270-273
Session 17: Logic/Physical Co-Design

Performance Driven Multi-Level and Multiway Partitioning with Retiming (Abstract)

Jason Cong , UCLA Department of Computer Science, Los Angeles
Sung Kyu Lim , UCLA Department of Computer Science, Los Angeles
Chang Wu , Aplus Design Technologies, Inc., Los Angeles, CA
pp. 274-279

Domino Logic Synthesis Minimizing Crosstalk (Abstract)

Sung-Mo Kang , University of Illinois at Urbana-Champaign, IL
Unni Narayanan , Intel Corporation, Santa Clara, CA
Ki-Wook Kim , University of Illinois at Urbana-Champaign, IL
pp. 280-285

Fast Post-Placement Rewiring using Easily Detectable Functional Symmetries (Abstract)

Chih-Wei Chang , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
Peter Suaris , Mentor Graphics Corporation, Wilsonville, Oregon
Chung-Kuan Cheng , University of California, San Diego
pp. 286-289

Depth Optimal Incremental Mapping for Field Programmable Gate Arrays (Abstract)

Jason Cong , University of California, Los Angeles
Hui Huang , Stanford University, CA
pp. 290-293
Session 18: Power Analysis and Optimization for Embedded Software

Code Compression for Low Power Embedded System Design (Abstract)

Haris Lekatsas , Princeton University
J? Henkal , NEC USA
Wayne Wolf , Princeton University
pp. 294-299

Synthesis of Application-Specific Memories for Power Optimization in Embedded Systems (Abstract)

Alberto Macii , Politecnico di Torino, Italy
Enrico Macii , Politecnico di Torino, Italy
Luca Benini , Universit? di Bologna, Italy
Massimo Poncino , Politecnico di Torino, Italy
pp. 300-303

Influence of Compiler Optimizations on System Power (Abstract)

N. Vijaykrishnan , The Pennsylvania State University, University Park
W. Ye , The Pennsylvania State University, University Park
M. Kandemir , The Pennsylvania State University, University Park
M. J. Irwin , The Pennsylvania State University, University Park
pp. 304-307

Power Minimization Derived from Architectural-Usage of VLIW Processors (Abstract)

C. Gebotys , University of Waterloo, Canada
R. Gebotys , Wilfrid Laurier University
S. Wiratunga , University of Waterloo, Canada
pp. 308-311

Power Analysis of Embedded Operating Systems (Abstract)

Ganesh Lakshminarayana , CCRL-NEC USA, Princeton, NJ
Niraj K. Jha , Princeton University, Princeton, NJ
Anand Raghunathan , CCRL-NEC USA, Princeton, NJ
Robert P. Dick , Princeton University, Princeton, NJ
pp. 312-315
Session 19: Embedded Compilation Techniques

Memory Aware Compilation Through Accurate Timing Extraction (Abstract)

Peter Grun , University of California, Irvine, CA
Alex Nicolau , University of California, Irvine, CA
Nikil Dutt , University of California, Irvine, CA
pp. 316-321

Compiling Esterel into Sequential Code (Abstract)

Stephen A. Edwards , Advanced Technology Group, Synopsys
pp. 322-327

Interactive Co-Design of High Throughput Embedded Multimedia (Abstract)

Francky Catthoor , IMEC-DESICS, Leuven, Belgium
Thierry Franzetti , IMEC-DESICS, Leuven, Belgium
Thierry J.-F. Omn? , IMEC-DESICS, Leuven, Belgium
pp. 328-331

Predicting Performance Potential of Modern DSPs (Abstract)

Naji Ghazal , University of California, Berkeley
Jan Rabaey , University of California, Berkeley
Richard Newton , University of California, Berkeley
pp. 332-335
Session 20: Panel: Future Systems-on-Chip: Software or Hardware Design?
Plenary Panel: Embedded Systems Design in the New Millenium
Session 21: New Techniques in Power Estimation and Performance Improvement

The Design and use of Simplepower: A Cycle-Accurate Energy Estimation Tool (Abstract)

M. J. Irwin , The Pennsylvania State University, University Park
W. Ye , The Pennsylvania State University, University Park
N. Vijaykrishnan , The Pennsylvania State University, University Park
M. Kandemir , The Pennsylvania State University, University Park
pp. 340-345

An Instruction-Level Functionally-Based Energy Estimation Model for 32-Bits Microprocessors (Abstract)

F. Salice , Politecnico di Milano, Italy
C. Brandolese , Politecnico di Milano, Italy
W. Fornaciari , Politecnico di Milano, Italy
D. Sciuto , Politecnico di Milano, Italy
pp. 346-351

Dynamic Power Management of Complex Systems using Generalized Stochastic Petri Nets (Abstract)

Qing Wu , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
Qinru Qiu , University of Southern California, Los Angeles
pp. 352-356

Wave-Steering One-Hot Encoded FSMs (Abstract)

Luca Macchiarulo , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 357-360

Performance Analysis and Optimization of Latency Insensitive Systems (Abstract)

Alberto L. Sangiovanni-Vincentelli , University of California at Berkeley, CA
Luca P. Carloni , University of California at Berkeley, CA
pp. 361-367
Session 22: Combined Global Routing, Buffering and Wiresizing

A Fast Algorithm for Context-Aware Buffer Insertion (Abstract)

John Lillis , University of Illinois at Chicago
Ashok Jagannathan , University of Illinois at Chicago
Sung-Woo Hur , University of Illinois at Chicago
pp. 368-373

Maze Routing with Buffer Insertion and Wiresizing (Abstract)

D. F. Wong , The University of Texas at Austin
Minghorng Lai , The University of Texas at Austin
pp. 374-378

Routing Tree Construction under Fixed Buffer Locations (Abstract)

Xin Yuan , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 379-384

A Current Driven Routing and Verification Methodology for Analog Applications (Abstract)

Lars Hedrich , University of Hanover, Germany
Thorsten Adler , Infineon Technologies AG, Munich, Germany
Hiltrud Brocke , University of Hanover, Germany
Erich Barke , University of Hanover, Germany
pp. 385-389
Session 23: Advances in System Modeling and Synthesis

A Codesign Virtual Machine for Hierarchical, Balanced Hardware/Software System Modeling (Abstract)

Simon N. Peffers , Carnegie Mellon University, Pittsburgh, PA
JoAnn M. Paul , Carnegie Mellon University, Pittsburgh, PA
Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
pp. 390-395

Operating System based Software Generation for Systems-on-Chip (Abstract)

D. Verkest , IMEC, Leuven, Belgium
Hugo De Man , IMEC, Leuven, Belgium
Dirk Desmet , IMEC, Leuven, Belgium
pp. 396-401

YAPI: Application Modeling for Signal Processing Systems (Abstract)

E. A. de Kock , Philips Research, The Netherlands
P. van der Wolf , Philips Research, The Netherlands
G. Essink , Philips Research, The Netherlands
W. J. M. Smits , Philips Research, The Netherlands
W. M. Kruijtzer , Philips Research, The Netherlands
K. A. Vissers , Philips Research, The Netherlands
P. Lieverse , Delft University of Technology, The Netherlands
J.-Y. Brunel , Philips Research, The Netherlands
pp. 402-405

COSY Communication IP's (Abstract)

L. Pasquier , Philips Research Laboratories Eindhoven, Paris
J.-Y. Brunel , Philips Research
E. A. de Kock , Philips Research
H. J. H. N. Kenter , Philips Research
W. M. Kruijtzer , Philips Research
F. P?trot , Universit? Pierre et Marie Curie, Paris
W. J. M. Smits , Philips Research
pp. 406-409

Synthesis and Optimization of Coordination Controllers for Distributed Embedded Systems (Abstract)

Gaetano Borriello , University of Washington, Seattle
Pai H. Chou , University of California, Irvine
pp. 410-415

Application-Specific Memory Management for Embedded Systems Using Software-Controlled Caches (Abstract)

Larry Rudolph , Massachusetts Institute of Technology, Cambridge, MA
Srinivas Devadas , Massachusetts Institute of Technology, Cambridge, MA
Prabhat Jain , Massachusetts Institute of Technology, Cambridge, MA
Derek Chiou , Massachusetts Institute of Technology, Cambridge, MA
pp. 416-419
Session 24: Designing Systems on a Chip

Designing Systems-on-Chip using Cores (Abstract)

William R. Lee , IBM Microelectronics, Raleigh, NC
Reinaldo A. Bergamaschi , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 420-425

Verification of Configurable Processor Cores (Abstract)

Marin? Puig-Medina , Tensilica, Inc., Santa Clara, CA
G? Ezer , Tensilica, Inc., Santa Clara, CA
Pavlos Konas , Tensilica, Inc., Santa Clara, CA
pp. 426-431
Session 25: Panel: The Future of System Design Languages
Session 26: Mixed Signal Design and Analysis

A Methodology for Efficient High-Level Dataflow Simulation of Mixed-Signal Front-Ends of Digital Telecom Transceivers (Abstract)

Gerd Vandersteen , IMEC, Heverlee, Belgium
Petr Dobrovoln? , IMEC, Heverlee, Belgium
St?phane Donnay , IMEC, Heverlee, Belgium
Yves Rolain , Vrije Universiteit Brussel, Brussels, Belgium
Piet Wambacq , IMEC, Heverlee, Belgium
Marc Engels , IMEC, Heverlee, Belgium
Ivo Bolsens , IMEC, Heverlee, Belgium
pp. 440-445

High-Level Simulation of Substrate Noise Generation Including Power Supply Noise Coupling (Abstract)

Mustafa Badaroglu , IMEC, Leuven, Belgium
Marc Engels , IMEC, Leuven, Belgium
Marc van Heijningen , IMEC, Leuven, Belgium
Ivo Bolsens , IMEC, Leuven, Belgium
St?phane Donnay , IMEC, Leuven, Belgium
pp. 446-451

Systematic Design of a 14-bit 150-MS/s CMOS Current-Steering D/A Converter (Abstract)

W. Sansen , Katholieke Universiteit Leuven
J. Vandenbussche , Katholieke Universiteit Leuven
G. Gielen , ESAT-MICAS
G. Van der Plas , Katholieke Universiteit Leuven
W. Daems , Katholieke Universiteit Leuven
A. Van den Bosch , Katholieke Universiteit Leuven
pp. 452-457
Session 27: Floorplanning & Placement

B*-Trees: A New Representation for Non-Slicing Floorplans (Abstract)

Guang-Ming Wu , National Chiao Tung University, Hsinchu, Taiwan
Yun-Chih Chang , National Chiao Tung University, Hsinchu, Taiwan
Yao-Wen Chang , National Chiao Tung University, Hsinchu, Taiwan
Shu-Wei Wu , National Chiao Tung University, Hsinchu, Taiwan
pp. 458-463

Block Placement with Symmetry Constraints Based on the O-Tree Non-Slicing Representation (Abstract)

Florin Balasa , University of Illinois, Chicago
Yingxin Pang , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
Koen Lampaert , Conexant Systems Inc., Newport Beach, CA
pp. 464-467

Floorplan Sizing by Linear Programming Approximation (Abstract)

Pinhong Chen , Univ. of California at Berkeley
Ernest S. Kuh , Univ. of California at Berkeley
pp. 468-471

Timing-Driven Placement based on Partitioning with Dynamic Cut-Net Control (Abstract)

Shih-Lian Ou , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
pp. 472-476

Can Recursive Bisection Alone Produce Routable Placements? (Abstract)

Andrew E. Caldwell , UCLA Computer Science Dept., Los Angeles, CA
Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
Igor L. Markov , UCLA Computer Science Dept., Los Angeles, CA
pp. 477-482
Session 28: System Level Scheduling

Task Scheduling with RT Constraints (Abstract)

A. Sangiovanni-Vincentelli , Univ. of California at Berkeley
M. Di Natale , Universit? degli Studi di Pisa, Italy
F. Balarin , Cadence Berkeley Labs, Berkeley, CA
pp. 483-488

Task Generation and Compile-Time Scheduling for Mixed Data-Control Embedded Software (Abstract)

Yosinori Watanabe , Cadence Berkeley Labs
Jordi Cortadella , Universitat Polit?cnica de Catalunya
Sandra Moral , Universitat Polit?cnica de Catalunya
Luciano Lavagno , Universit? di Udine
Alberto Sangiovanni-Vincentelli , University of California Berkeley
Claudio Passerone , Politecnico di Torino
Alex Kondratyev , Theseus Logic
Marc Massot , Universitat de Girona
pp. 489-494

Schedulability-Driven Performance Analysis of Multiple Mode Embedded Real-Time Systems (Abstract)

Kiyoung Choi , Seoul National University, Korea
Daehong Kim , Seoul National University, Korea
Youngsoo Shin , University of Tokyo, Japan
pp. 495-500
Session 29: Architectures for Embedded Systems

System Design of Active Basestations based on Dynamically Reconfigurable Hardware (Abstract)

Athanassios Boulis , Dept. of Electrical Eng. at UCLA, Los Angeles, CA
Mani B. Srivastava , Dept. of Electrical Eng. at UCLA, Los Angeles, CA
pp. 501-506

Hardware-Software Co-Design of Embedded Reconfigurable Architectures (Abstract)

Tim Callahan , Univ. of California, Berkeley, CA
Jon Stockwood , Synopsys Inc., Mountain View, CA
Uday Kurkure , Synopsys Inc., Mountain View, CA
Yanbing Li , Synopsys Inc., Mountain View, CA
Ervan Darnell , Silicon Spice, Mountain View, CA
Randolph Harr , Synopsys Inc., Mountain View, CA
pp. 507-512

Communication Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for Systems-on-Chips (Abstract)

Sujit Dey , University of California, San Diego, CA
Anand Raghunathan , NEC USA, Princeton, NJ
Ganesh Lakshminarayana , NEC USA, Princeton, NJ
Kanishka Lahiri , University of California, San Diego, CA
pp. 513-518
Session 30: Panel: Embedded Systems Education
Session 31: Interconnect Analysis

Passive Model Order Reduction Algorithm Based on Chebyshev Expansion of Impulse Response of Interconnect Networks (Abstract)

Qingjian Yu , University of California at Berkeley
Janet M. Wang , University of California at Berkeley
Ernest S. Kuh , University of California at Berkeley
pp. 520-525

Passive Model Order Reduction of Multiport Distributed Interconnects (Abstract)

Michel Nakhla , Carleton University, Ottawa, Canada
Emad Gad , Carleton University, Ottawa, Canada
Anestis Dounavis , Carleton University, Ottawa, Canada
Ramachandra Achar , Carleton University, Ottawa, Canada
pp. 526-531
Session 32: High Level Synthesis for DSPs: Data Intensive Applications

Optimal Two Level Partitioning and Loop Scheduling for Hiding Memory Latency for DSP Applications (Abstract)

Michael Kirkpatrick , University of Notre Dame, IN
Zhong Wang , University of Notre Dame, IN
Edwin Hsing-Mean Sha , University of Notre Dame, IN
pp. 540-545

On Lower Bounds for Scheduling Problems in High-Level Synthesis (Abstract)

J. Ramanujam , Louisiana State University, Baton Rouge, LA
M. Narasimhan , Intel Corporation, Dupont, WA
pp. 546-551

Efficient Building Block Based RTL Code Generation from Synchronous Data Flow Graphs (Abstract)

Jens Horstmannshoff , Integrated Signal Processing Systems, RWTH Aachen, Germany
Heinrich Meyr , Integrated Signal Processing Systems, RWTH Aachen, Germany
pp. 552-555

System-Level Data Format Exploration for Dynamically Allocated Data Structures (Abstract)

Francky Catthoor , IMEC, Belgium; Katholieke Universiteit Leuven
Miguel Miranda , IMEC, Belgium
Peeter Ellervee , ESD, KTH, Sweden
Ahmed Hemani , ESD, KTH, Sweden
pp. 556-559
Session 33: Embedded Tutorial: MOSFET Modeling and Circuit Design: Re-Establishing a Lost Connection
Session 34: Reconfigurable Computing Systems

Using General-Purpose Programming Languages for FPGA Design (Abstract)

Brad L. Hutchings , Brigham Young University, Provo, UT
Brent E. Nelson , Brigham Young University, Provo, UT
pp. 561-566

An Architecture-Driven Detric for Simultaneous Placement and Global Routing for FPGAs (Abstract)

Yu-Tsang Chang , Chip Implementation Center, National Science Council of Taiwan, Taiwan
Yao-Wen Chang , National Chiao Tung University, Taiwan
pp. 567-572

MorphoSys: Case Study of a Reconfigurable Computing System Targeting Multimedia Applications (Abstract)

Guangming Lu , University of California, Irvine
Eliseu Filho , COPPE/Federal University of Rio De Janeiro, Brazil
Rafael Maestre , Universidad Complutense, Madrid, Spain
Ming-Hau Lee , University of California, Irvine
Hartej Singh , University of California, Irvine
Nader Bagherzadeh , University of California, Irvine
Fadi Kurdahi , University of California, Irvine
pp. 573-578
Session 35: Panel: Survival Strategies for Mixed-Signal Systems-On-Chip
Session 36: Intellectual Property Protection & Re-Use

Forensic Engineering Techniques for VLSI CAD Tools (Abstract)

David Liu , University of California, Los Angeles
Jennifer Wong , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
Darko Kirovski , University of California, Los Angeles
pp. 581-586

Fingerprinting Intellectual Property using Constraint-Addition (Abstract)

Gang Qu , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 587-592

Hardware/Software IP protection (Abstract)

Alessandro Bogliolo , DI - University of Ferrara, Italy
Luca Benini , DEIS - University of Bologna, Italy
Marcello Dalpasso , DEI - University of Padova, Italy
pp. 593-596

A Web-CAD Methodology for IP-Core Analysis and Simulation (Abstract)

Alessandro Fin , Universit? di Verona, Italy
Franco Fummi , Universit? di Verona, Italy
pp. 597-600
Session 37: Correctness Issues in High Level Synthesis

Optimizing Sequential Verification by Retiming Transformations (Abstract)

Stefano Quer , Politecnico di Torino, Italy
Fabio Somenzi , University of Colorado, Boulder
Gianpiero Cabodi , Politecnico di Torino, Italy
pp. 601-606

Efficient Methods for Embedded System Design Space Exploration (Abstract)

Felice Balarin , Cadence Berkeley Laboratories, USA
Harry Hsieh , University of California at Berkeley
Luciano Lavagno , Politecnico di Torino, Italy
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
pp. 607-612

Synthesis-for-Testability of Controller-Datapath Pairs that use Gated Clocks (Abstract)

Mehrdad Nourani , The Univ. of Texas at Dallas
Christos Papachristou , Case Western Reserve Univ., Cleveland, OH
Joan Carletta , The Univ. of Akron, OH
pp. 613-618
Session 38: SOC Test Methodologies and Defect Modelling

Self-Test Methodology for At-Speed Test of Crosstalk in Chip Interconnects (Abstract)

Sujit Dey , University of California, San Diego
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
Xiaoliang Bai , University of California, San Diego
pp. 619-624

Embedded Hardware and Software Self-Testing Methodologies for Processor Cores (Abstract)

Ying Cheng , University of California at San Diego
Li Chen , University of California at San Diego
Krishna Sekar , University of California at San Diego
Pablo Sanchez , University of Cantabria, Santander, Spain
Sujit Dey , University of California at San Diego
pp. 625-630

Modeling and Simulation of Real Defects using Fuzzy Logic (Abstract)

Amir Attarha , The Univ. of Texas at Dallas
Carco Lucas , The Univ. of Tehran, Iran
Mehradad Nourani , The Univ. of Texas at Dallas
pp. 631-636
Session 39: Embedded Tutorial: Bridging the Gap Between Full Custom and AISC Design

Closing the Gap Between ASIC and Custom: an ASIC Perspective (Abstract)

K. Keutzer , University of California at Berkeley
D. G. Chinnery , University of California at Berkeley
pp. 637-642

The Role of Custom Design in ASIC Chips (Abstract)

Willaim J. Dally , Stanford University, CA
Andrew Chang , Stanford University, CA
pp. 643-647
Session 40: Panel: Case Studies: Chip Design on the Bleeding Edge
Session 41: Layout Optimization

MINFLOTRANSIT: Min-Cost Flow based Transistor Sizing Tool (Abstract)

Keshab K. Parhi , University of Minnesota, Minneapolis
Vijay Sundararajan , University of Minnesota, Minneapolis
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
pp. 649-664

Convex Delay Models for Transistor Sizing (Abstract)

Kishore Kasamsetty , University of Minnesota, Minneapolis
Mahesh Ketkar , University of Minnesota, Minneapolis
Sachin Sapatnekar , University of Minnesota, Minneapolis
pp. 655-660

Macro-Driven Circuit Design Methodology for High-Performance Datapaths (Abstract)

Mahadevamurty Nemani , Intel Corporation, Santa Clara, CA
Vivek Tiwari , Intel Corporation, Santa Clara, CA
pp. 661-666

Model-Based Dummy Feature Placement for Oxide Chemical-Mechanical Polishing Manufacturability (Abstract)

D. F. Wong , University of Texas at Austin, TX
Robert Boone , Motorola Inc., Austin, TX; University of Texas at Austin
Ruiqi Tian , University of Texas at Austin, TX; Motorola Inc., Austin, TX
pp. 667-670

Practical Iterated Fill Synthesis for CMP Uniformity (Abstract)

Gabriel Robins , University of Virginia, Charlottesville, VA
Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
Yu Chen , UCLA Computer Science Dept., Los Angeles, CA
Alexander Zelikovsky , Georgia State University, Atlanta, GA
pp. 671-674
Session 42: Decision Procedures for cAD Problems

Boolean Satisfiability in Electronic Design Automation (Abstract)

Jo?o P. Marques-Silva , Technical University of Lisbon, IST/INESC, Lisbon, Portugal
Karem A. Sakallah , University of Michigan, Ann Arbor, Michigan
pp. 675-680

Analysis of Composition Complexity and how to Obtain Smaller Canonical Graphs (Abstract)

K. Mohanram , University of Texas, Austin
D. Moundanos , Fujitsu Labs of America, Sunnyvale, CA
I. Wegener , Universitaet Dortmund, Germany
Y. Lu , Carnegie Mellon University, Pittsburgh, PA
J. Jain , Fujitsu Labs of America, Sunnyvale, CA
pp. 681-686

Efficient Variable Ordering using aBDD based Sampling (Abstract)

Masahiro Fujita , Fujitsu Laboratories of America
Yuan Lu , Carnegie Mellon University
Edmund Clarke , Carnegie Mellon University
Jawahar Jain , Fujitsu Laboratories of America
pp. 687-692
Session 43: New Frameworks for the EDA Field

GTX: the MARCO GSRC Technology Extrapolation System (Abstract)

Yu Cao , UC Berkeley EECS Dept., USA
Hua Lu , UC Berkeley EECS Dept., USA
Dennis Sylvester , Synopsis, Inc., USA
Andrew B. Kahng , UCLA CS Dept., USA
Farinaz Koushanfar , UCLA CS Dept., USA
Andrew E. Caldwell , UCLA CS Dept., USA
Igor L. Markov , UCLA CS Dept., USA
Dirk Stroobandt , Ghent University ELIS Dept., Belgium
Michael Oliver , UCLA CS Dept., USA
pp. 693-698

A System Simulation Framework (Abstract)

W. P. M. van der Linden , Philips Research Laboratories Eindhoven, The Netherlands
N. W. Schellingerhout , Philips Research Laboratories Eindhoven, The Netherlands
P. Bingley , Philips Research Laboratories Eindhoven, The Netherlands
P. van den Hamer , Philips Research Laboratories Eindhoven, The Netherlands
pp. 699-704

METRICS: a System Architecture for Design Process Optimization (Abstract)

Stephen Fenstermaker , UCLA Computer Science Dept., Los Angeles, CA
Stefanus Mantik , OxSigen LLC, San Jose, California
Andrew B. Kahng , OxSigen LLC, San Jose, California
David George , UCLA Computer Science Dept., Los Angeles, CA
Bart Thielges , UCLA Computer Science Dept., Los Angeles, CA
pp. 705-710
Session 44: High Performance Microprocessor Design

Timing Closure by Design, a High Frequency Microprocessor Design Methodology (Abstract)

N. Kojima , IBM Austin Research Lab, Austin, TX
P. Villarrubia , IBM Server Division, Austin, TX
O. Takahashi , IBM Austin Research Lab, Austin, TX
P. Hofstee , IBM Austin Research Lab, Austin, TX
B. Flachs , Motorola, Austin, TX
K. Nowka , IBM Austin Research Lab, Austin, TX
N. Aoki , IBM Austin Research Lab, Austin, TX
J. Peter , IBM Austin Research Lab, Austin, TX
P. Coulman , IBM Server Division, Austin, TX
K. Lee , Sun Microsystems, CA
D. Meltzer , IBM Watson Research Lab, Yorktown, NY
O. Kwon , IBM Austin Research Lab, Austin, TX
J. Park , Samsung, Korea
J. Silberman , IBM Watson Research Lab, Yorktown, NY
S. Posluszny , IBM Austin Research Lab, Austin, TX
S. Dhong , IBM Austin Research Lab, Austin, TX
D. Boerstler , IBM Austin Research Lab, Austin, TX
pp. 712-717

A Methodology for Formal Design of Hardware Control with Application to Cache Coherence Protocols (Abstract)

Kyle Nelson , IBM Rochester, MN
Cindy Eisner , IBM Haifa Research Laboratory, Israel
Irit Shitsevalov , IBM Haifa Research Laboratory, Israel
Russ Hoover , IBM Rochester, MN
Wayne Nation , IBM Rochester, MN
Ken Valk , IBM Rochester, MN
pp. 724-729

CGaAs PowerPC FXU (Abstract)

Keith L. Kraver , University of Michigan, Ann Arbor
Richard B. Brown , University of Michigan, Ann Arbor
Phiroze N. Parakh , University of Michigan, Ann Arbor
Alan J. Drake , University of Michigan, Ann Arbor
P. Sean Stetson , University of Michigan, Ann Arbor
Todd D. Basso , University of Michigan, Ann Arbor
Spencer M. Gold , University of Michigan, Ann Arbor
Claude R. Gauthier , University of Michigan, Ann Arbor
pp. 730-735
Session 45: Panel: When Bad Things Happen to Good Chips
Session 46: Large-Scale Parasitic Analysis

Fast Methods for Extraction and Sparsification of Substrate Coupling (Abstract)

Jacob White , Massachusetts Institute of Technology, Cambridge
Joe Kanapka , Massachusetts Institute of Technology, Cambridge
Joel Phillips , Cadence Berkeley Laboratories, San Jose, CA
pp. 738-743

Large-Scale Capacitance Calculation (Abstract)

Sharad Kapur , Lucent Technologies, Murray Hill, NJ
David E. Long , Lucent Technologies, Murray Hill, NJ
pp. 744-749

Fast Temperature Calculation for Transient Electrothermal Simulation by Mixed Frequency/Time Domain Thermal Model Reduction (Abstract)

Sung-Mo Kang , University of Illinois at Urbana-Champaign
Ching-Han Tsai , University of Illinois at Urbana-Champaign
pp. 750-755
Session 47: Advances in High Level Synthesis

Unifying Behavioral Synthesis and Physical Design (Abstract)

Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
William E. Dougherty , Carnegie Mellon University, Pittsburgh, PA
pp. 756-761

The use of Carry-Save Representation in Joint Module Selection and Retiming (Abstract)

Zhan Yu , University of California, Los Angeles
Kei-Yong Khoo , University of California, Los Angeles
Alan N. Willson , University of California, Los Angeles
pp. 768-773
Session 48: Fault Simulation and Extraction of Low-Level Effects

Closing the Gap Between Analog and Digital (Abstract)

Bozena Kaminska , Fluence Technology Inc., Beaverton, OR
Khaled Saab , Fluence Technology Inc., Beaverton, OR
Naim Ben Hamida , Fluence Technology Inc., Beaverton, OR
pp. 774-779

A Switch Level Fault Simulation Environment (Abstract)

J. Casas , Intel Corporation, Hillsboro, OR
V. Krishnaswamy , Intel Corporation, Hillsboro, OR
T. Tetzlaff , Intel Corporation, Hillsboro, OR
pp. 780-785

Universal Fault Simulation using Fault Tuples (Abstract)

Kumar N. Dwarakanath , Carnegie Mellon University, Pittsburgh, PA
R. D. Blanton , Carnegie Mellon University, Pittsburgh, PA
pp. 786-789

A Novel Algorithm to Extract Two-Node Bridges (Abstract)

Sujit T. Zachariah , Intel Corporation, Santa Clara, CA
Carl D. Roth , Intel Corporation, Santa Clara, CA
Sreejit Chakravarty , Intel Corporation, Santa Clara, CA
pp. 790-793
Session 49: Low Power Design Techniques and Estimation

Power Minimization using Control Generated Clocks (Abstract)

M. Srikanth Rao , Indian Institute of Science, Bangalore, India
S. K. Nandy , Indian Institute of Science, Bangalore, India
pp. 794-799

Bus Encoding for Low-Power High-Performance Memory Systems (Abstract)

Kwanho Kim , Seoul National University, Korea
Jinsung Cho , Seoul National University, Korea
Naehyuck Chang , Seoul National University, Korea
pp. 800-805

Run-Time Voltage Hopping for Low-Power Real-Time Systems (Abstract)

Seongsoo Lee , University of Tokyo, Japan
Takayasu Sakurai , University of Tokyo, Japan
pp. 806-809

Function-Level Power Estimation Methodology for Microprocessors (Abstract)

Naoyuki Kawabe , Toshiba Corporation, Kawasaki, Japan
Kimiyoshi Usami , Toshiba Corporation, Kawasaki, Japan
Gang Qu , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 810-813
Session 50: Panel: Emerging Companies-Acquiring Minds Want to Know

Author Index (PDF)

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