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Design Automation Conference (2000)
Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 800-805
Kwanho Kim , Seoul National University, Korea
Jinsung Cho , Seoul National University, Korea
Naehyuck Chang , Seoul National University, Korea
ABSTRACT
High-performance memory buses consume large energy as they include termination networks, BiCMOS and/or open-drain output. This paper introduces power reduction techniques for memory systems deliberating on burst-mode transfers over the high-speed bus specifications such as Low Voltage BiCMOS (LVT), Gunning Transfer Logic (GTL+) and Stub Series Termination Logic (SSTL_2) which are widely used. The reduction techniques take both the static and the dynamic power consumption into account because most high-performance bus drivers and end-termination networks dissipate significant static power as well. Extensive performance analysis is conducted through mathematical analysis and trace data-driven simulations. We had reduction of 14% with random data and up to 67.5% with trace data.
INDEX TERMS
fault modeling, fault simulation, hard faults, test vector generation
CITATION
Kwanho Kim, Jinsung Cho, Naehyuck Chang, "Bus Encoding for Low-Power High-Performance Memory Systems", Design Automation Conference, vol. 00, no. , pp. 800-805, 2000, doi:10.1109/DAC.2000.855423
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