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Design Automation Conference (2000)
Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 786-789
Kumar N. Dwarakanath , Carnegie Mellon University, Pittsburgh, PA
R. D. Blanton , Carnegie Mellon University, Pittsburgh, PA
ABSTRACT
We introduce a new fault representation mechanism for digital circuits based on fault tuples. A fault tuple is a simple 3-element condition for a signal line, its value, and clock cycle constraint. AND-OR expressions of fault tuples are used to represent arbitrary misbehaviors. A fault simulator based on fault tuples was used to conduct experiments on benchmark circuits. Simulation results show that a 17% reduction of average CPU time is achieved when performing simulation on all fault types simultaneously, as opposed to individually. We expect further improvements in speedup when the shared characteristics of the various fault types are better exploited.
INDEX TERMS
fault modeling, fault simulation, hard faults, test vector generation
CITATION
Kumar N. Dwarakanath, R. D. Blanton, "Universal Fault Simulation using Fault Tuples", Design Automation Conference, vol. 00, no. , pp. 786-789, 2000, doi:10.1109/DAC.2000.855420
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