The Community for Technology Leaders
RSS Icon
Subscribe
Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 649-664
Keshab K. Parhi , University of Minnesota, Minneapolis
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Vijay Sundararajan , University of Minnesota, Minneapolis
ABSTRACT
This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool that has two alternating phases. For a circuit with
INDEX TERMS
ASIC, clock frequency, clock speed, comparison, custom
CITATION
Keshab K. Parhi, Sachin S. Sapatnekar, Vijay Sundararajan, "MINFLOTRANSIT: Min-Cost Flow based Transistor Sizing Tool", DAC, 2000, Design Automation Conference, Design Automation Conference 2000, pp. 649-664, doi:10.1109/DAC.2000.855394
127 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool