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Design Automation Conference (2000)
Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 649-664
Keshab K. Parhi , University of Minnesota, Minneapolis
Vijay Sundararajan , University of Minnesota, Minneapolis
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool that has two alternating phases. For a circuit with
ASIC, clock frequency, clock speed, comparison, custom
Keshab K. Parhi, Vijay Sundararajan, Sachin S. Sapatnekar, "MINFLOTRANSIT: Min-Cost Flow based Transistor Sizing Tool", Design Automation Conference, vol. 00, no. , pp. 649-664, 2000, doi:10.1109/DAC.2000.855394
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