The Community for Technology Leaders
Design Automation Conference (2000)
Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 340-345
M. J. Irwin , The Pennsylvania State University, University Park
W. Ye , The Pennsylvania State University, University Park
N. Vijaykrishnan , The Pennsylvania State University, University Park
M. Kandemir , The Pennsylvania State University, University Park
ABSTRACT
In this paper, we present the design and use of a comprehensive framework, SimplePower, for evaluating the effect of high-level algorithmic, architectural, and compilation trade-offs on energy. An execution-driven, cycle-accurate RT level energy estimation tool that uses transition sensitive energy models forms the cornerstone of this framework. SimplePower also provides the energy consumed in the memory system and on-chip buses using analytical energy models. We present the use of SimplePower to evaluate the impact of a new selective gated pipeline register optimization, a high-level data transformation and a power-conscious post compilation optimization (register relabeling) on the datapath, memory and on-chip bus energy, respectively. We find that these three optimizations reduce the energy by 18-36% in the datapath, 62% in the memory system and 12% in the instruction cache data bus, respectively.
INDEX TERMS
nanotechnology, quantum cellular automata
CITATION
M. J. Irwin, W. Ye, N. Vijaykrishnan, M. Kandemir, "The Design and use of Simplepower: A Cycle-Accurate Energy Estimation Tool", Design Automation Conference, vol. 00, no. , pp. 340-345, 2000, doi:10.1109/DAC.2000.855333
89 ms
(Ver 3.3 (11022016))