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Design Automation Conference (2000)
Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 239-242
Dae-Jin Kim , Columbia University, New York, NY
Kenneth L. Shepard , Columbia University, New York, NY
ABSTRACT
In this paper, we extend transistor-level static noise analysis tools to consider the unique features of partially-depleted silicon-on-insulator (PD-SOI) technology: floating-body-induced threshold voltage variations and parasitic bipolar leakage currents. This involves a unique state-diagram abstraction of the device physics determining the body-potential of PD-SOI FETs. Based on this picture, a simple model of the body voltage is derived which takes into account modest knowledge of which nets have dependable, regular switching activity. Results are presented using a commericial static noise analysis tool incorporating these extensions.
INDEX TERMS
nanotechnology, quantum cellular automata
CITATION
Dae-Jin Kim, Kenneth L. Shepard, "Static Noise Analysis for Digital Integrated Circuits in Partially-Depleted Silicon-on-Insulator Technology", Design Automation Conference, vol. 00, no. , pp. 239-242, 2000, doi:10.1109/DAC.2000.855310
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