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Design Automation Conference (2000)
Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 233-238
Vladimir Zolotov , Motorola Inc., Austin, TX
Aurobindo Dasgupta , Motorola Inc., Austin, TX
Supamas Sirichotiyakul , Motorola Inc., Austin, TX
Rafi Levy , Motorola Semiconductor Israel Ltd. Tel Aviv, Israel
Chanlee Oh , Motorola Inc., Austin, TX
Boaz Orshav , Motorola Inc., Austin, TX
Gabi Braca , Motorola Semiconductor Israel Ltd. Tel Aviv, Israel
Amir Grinshpon , Motorola Semiconductor Israel Ltd. Tel Aviv, Israel
David Blaauw , Motorola Inc., Austin, TX
ABSTRACT
Coupled noise analysis has become a critical issue for deep-submicron, high performance design. In this paper, we present, ClariNet, an industrial noise analysis tool, which was developed to efficiently analyze large, high performance processor designs. We present the overall approach and tool flow of ClariNet and discuss three critical large-processor design issues which have received limited discussion in the past. First, we present how the driver gates of a coupled interconnect network are represented with accurate linear models. Second, we show how to speed the analysis of large designs by using noise filters based on reduced interconnect representations and then pruning the nets coupled to a signal net. Third, we show how to incorporate logic and timing correlations into noise analysis to reduce its pessimism. We present the results from several industrial circuits, including a large high performance microprocessor design and a DSP design.
INDEX TERMS
nanotechnology, quantum cellular automata
CITATION
Vladimir Zolotov, Aurobindo Dasgupta, Supamas Sirichotiyakul, Rafi Levy, Chanlee Oh, Boaz Orshav, Gabi Braca, Amir Grinshpon, David Blaauw, "ClariNet: A Noise Analysis Tool for Deep Submicron Design", Design Automation Conference, vol. 00, no. , pp. 233-238, 2000, doi:10.1109/DAC.2000.855309
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