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Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 221-226
S. Parameswaran , The University of Queensland, Australia
A. D. Rakic , The University of Queensland, Australia
V. E. Boros , The University of Queensland, Australia
We describe the first iteration of a comprehensive model with which we can investigate the practical limits on optical bus bandwidth and number of bus processing modules for given signal power. The selection algorithm will ultimately allow programmable evaluation of system parameters bus bandwidth, optical power budget, electrical power budget, number of modules and space consumption for an optimal design that is suited to on-the-fly system reconfiguration.
fault modeling, fault simulation, hard faults, test vector generation
S. Parameswaran, A. D. Rakic, V. E. Boros, "High-Level Model of a WDMA Passive Optical Bus for a Reconfigurable Multiprocessor System", DAC, 2000, Design Automation Conference, Design Automation Conference 2000, pp. 221-226, doi:10.1109/DAC.2000.855307
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