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Design Automation Conference (2000)
Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 207-212
William H. Mangione-Smith , UCLA EE Department, Los Angeles, CA
Miodrag Potkonjak , UCLA CS Department, Los Angeles, CA
John Lach , UCLA EE Department, Los Angeles, CA
Simulations for modern designs are often performed on Field Programmable Gate Array technology in a functional test and debugging process known as emulation, allowing for more complex simulations than possible in software. One drawback to emulation is the lengthy time spent in the back-end CAD tools for each debugging iteration, including debugging changes and the introduction of control and observation logic. We have developed a technique that confines the re-place-and-route area to only the portions of the design affected by the introduction of the test logic and by the debugging changes. Therefore, the back-end CAD effort for error detection, localization, and correction is reduced. This benefit is achieved by partitioning the design at the physical level into independent blocks, and the test logic and design changes are localized to the affected blocks. The result is a shortened time between debugging iterations, and thus a shortened time-to-market for the design.
fault modeling, fault simulation, hard faults, test vector generation
William H. Mangione-Smith, Miodrag Potkonjak, John Lach, "Efficient Error Detection, Localization, and Correction for FPGA-Based Debugging", Design Automation Conference, vol. 00, no. , pp. 207-212, 2000, doi:10.1109/DAC.2000.855305
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