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Design Automation Conference (2000)
Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 150-155
David Blaauw , Motorola Inc., Austin, TX
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Min Zhao , Motorola Inc., Austin, TX
Rajendran V. Panda , Motorola Inc., Austin, TX
Rajat Chaudhry , Motorola Inc., Austin, TX
Tim Edwards , Motorola Inc., Austin, TX
Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated through the analysis of case studies of several multi-million node power grids, extracted from real microprocessor and DSP designs.
fault modeling, fault simulation, hard faults, test vector generation
David Blaauw, Sachin S. Sapatnekar, Min Zhao, Rajendran V. Panda, Rajat Chaudhry, Tim Edwards, "Hierarchical Analysis of Power Distribution Networks", Design Automation Conference, vol. 00, no. , pp. 150-155, 2000, doi:10.1109/DAC.2000.855294
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