Formal Verification of Superscale Microprocessors with Multicycle Functional Units, Exception, and Branch Prediction
Los Angeles, CA
June 5, 2000 to June 9, 2000
Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
Miroslav N. Velev , Carnegie Mellon University, Pittsburgh, PA
We extend the Burch and Dill flushing technique  for formal verification of microprocessors to be applicable to designs where the functional units and memories have multicycle and possibly arbitrary latency. We also show ways to incorporate exceptions and branch prediction by exploiting the properties of the logic of Positive Equality with Uninterpreted Functions . We study the modeling of the above features in different versions of dual-issue superscalar processors.
fault modeling, fault simulation, hard faults, test vector generation
Randal E. Bryant, Miroslav N. Velev, "Formal Verification of Superscale Microprocessors with Multicycle Functional Units, Exception, and Branch Prediction", DAC, 2000, Design Automation Conference, Design Automation Conference 2000, pp. 112-117, doi:10.1109/DAC.2000.855288