Design Automation Conference (2000)
Los Angeles, CA
June 5, 2000 to June 9, 2000
D. F. Wong , University of Texas, Austin
Hai Zhou , Synopsys Inc., Mountain View, CA
With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. For the problem of low power decomposition of an XOR gate, if the implementation technology is static CMOS logic, previous research gave an O(n) log (n) time algorithm which assumes that the inputs have both polarities available. But that approach can not be used in dynamic logic. In this paper, we analyze the properties of optimal XOR decompositions in dynamic logic. Based on these optimality properties, we design an optimal algorithm to solve the low power XOR decomposition problem in dynamic logic. We also point out that the previous solution for static logic is not optimal, and give an optimal algorithm which does not even change the input polarities.
fault modeling, fault simulation, hard faults, test vector generation
D. F. Wong, Hai Zhou, "Optimal Low PowerX OR Gate Decomposition", Design Automation Conference, vol. 00, no. , pp. 104-107, 2000, doi:10.1109/DAC.2000.855286