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Design Automation Conference (2000)
Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 98-103
Taewhan Kim , Korea Adv. Institute of Science & Technology, Taejon, Korea
Junhyung Um , Korea Adv. Institute of Science & Technology, Taejon, Korea
C. L. Liu , National Tsing Hua Univ., Hsinchu, Taiwan
ABSTRACT
Wallace-tree compressor style has been widely recognized as one of the most effective implementation schemes for arithmetic computation sin VLSI design. However, the scheme has been applied only in a rather restrictive way, that is, for implementing fast multipliers and for generating fixed structures without considering the characteristic of the input signals. The contributions of our work are (1) to extend the applicability of the Wallace scheme to any arithmetic circuit which consists of additions/substractions/multiplications globally (instead of applying it to each operation) to produce a globally efficient architecture of the circuit; (2) to optimize the timing of the circuit for uneven signal arrival profiles; (Specifically, we present an efficient algorithm for generating a delay-optimal (bit-level) carry-save addition structure of an arithmetic circuit.) (3) to provide a comprehensive analysis of the switching activity of a (bit-level) carry-save addition structure, and based on which we derive an effective algorithm for synthesizing low power circuits. Putting these arithmetic optimization solutions together, a circuit designer will be able to fully understand the synthesis of arithmetic circuit based on the bit-level carry-save addition.
INDEX TERMS
fault modeling, fault simulation, hard faults, test vector generation
CITATION
Taewhan Kim, Junhyung Um, C. L. Liu, "A Fine-Grained Arithmetic Optimization Technique for High-Performance/Low-Power Data Path Synthesis", Design Automation Conference, vol. 00, no. , pp. 98-103, 2000, doi:10.1109/DAC.2000.855285
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