The Community for Technology Leaders
Design Automation Conference (1999)
New Orleans, Louisiana, United States
June 21, 1999 to June 25, 1999
ISBN: 1-58113-109-7
TABLE OF CONTENTS
Papers

An Efficient Lyapunov Equation-Based Approach for Generating Reduced-Order Models of Interconnect (Abstract)

Jing-Rebecca Li , Massachusetts Institute of Technology, Cambridge, MA
Frank Wang , Massachusetts Institute of Technology, Cambridge, MA
Jacob White , Massachusetts Institute of Technology, Cambridge, MA
pp. 1-6

Error Bounded Pad? Approximation via Bilinear Conformal Transformation (Abstract)

R. F. Wong , University of Texas at Austin
Chung-Ping Chen , Strategic CAD Labs, Intel Corp., Hillsboro, Oregon
pp. 7-12

Model-Reduction of Nonlinear Circuits Using Krylov-Space Techniques (Abstract)

Pavan K. Gunupudi , Carleton University, Ottawa, Canada
Michel S. Nakhla , Carleton University, Ottawa, Canada
pp. 13-16

Why is ATPG Easy? (Abstract)

Mukul R. Prasad , University of California, Berkeley, CA
Kurt Keutzer , University of California, Berkeley, CA
Philip Chong , University of California, Berkeley, CA
pp. 22-28

Using Lower Bounds during Dynamic BDD Minimization (Abstract)

Wolfgang G?nther , Albert-Ludwigs-University, Germany
Rolf Drechsler , Albert-Ludwigs-University, Germany
pp. 29-32

Optimization-Intensive Watermarking Techniques for Decision Problems (Abstract)

Jennifer L. Wong , University of California, Los Angeles, CA
Miodrag Potkonjak , University of California, Los Angeles, CA
Gang Qu , University of California, Los Angeles, CA
pp. 33-36

Efficient Algorithms for Optimum Cycle Mean and Optimum Cost to Time Ratio Problems (Abstract)

Rajesh K. Gupta , University of California, Irvine, CA
Sandy S. Irani , University of California, Irvine, CA
Ali Dasdan , University of Illinois, Urbana, IL
pp. 37-42

IP-Based Design Methodology (PDF)

Daniel D. Gajski , University of California, Irvine
pp. 43

ipChinook: An Integrated IP-Based Design Framework for Distributed Embedded Systems (Abstract)

Ken Hines , University of Washington, Seattle, WA
Kurt Partridge , University of Washington, Seattle, WA
Pai Chou , Consystant Design Technologies, Inc., Seattle, WA
Gaetano Borriello , University of Washington, Seattle, WA
Ross Ortega , University of Washington, Seattle, WA
pp. 44-49

Virtual Simulation of Distributed IP-Based Designs (Abstract)

Luca Benini , DEIS - Universit? di Bologna, Italy
Alessandro Bogliolo , DEIS - Universit? di Bologna, Italy
Marcello Dalpasso , DEI - Universit? di Padova, Italy
pp. 50-55

Common-Case Computation: A High-Level Technique for Power and Performance Optimization (Abstract)

Sujit Dey , Univ. of California, San Diego
Niraj K. Jha , Princeton University
Ganesh Lakshminarayana , CCRL-NEC USA
Anand Raghunathan , CCRL-NEC USA
Kamal S. Khouri , Princeton University
pp. 56-61

Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-Based Designs (Abstract)

Jinn-Shyan Wang , Nat'l Chung-Cheng Univ., Taiwan
Yin-Shuin Kang , Nat'l Chung-Cheng Univ., Taiwan
Shan-Jih Shieh , Nat'l Chung-Cheng Univ., Taiwan
Chingwei Yeh , Nat'l Chung-Cheng Univ., Taiwan
pp. 62-67

Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications (Abstract)

Wen-Bone Jone , Nat'l Chung-Cheng Univ., Taiwan
Min-Cheng Chang , Nat'l Chung-Cheng Univ., Taiwan
Chingwei Yeh , Nat'l Chung-Cheng Univ., Taiwan
Shih-Chieh Chang , Nat'l Chung-Cheng Univ., Taiwan
pp. 68-71

Synthesis of Low Power CMOS VLSI Circuits using Dual Supply Voltages (Abstract)

Keshab K. Parhi , University of Minnesota, MN
Vijay Sundararajan , University of Minnesota, MN
pp. 72-75

Reliability-Constrained Area Optimization of VLSI Power/Ground Networks Via Sequence of Linear Programmings (Abstract)

Xiang-Dong Tan , University of Washington, Seattle, WA
C.-J. Richard Shi , University of Washington, Seattle, WA
Dragos Lungeanu , University of Washington, Seattle, WA
Li-Pen Yuan , Avant! Corporation, Fremont, CA
Jyh-Chwen Lee , Avant! Corporation, Fremont, CA
pp. 78-83

FAR-DS: Full-plane AWE Routing with Driver Sizing (Abstract)

Jiang Hu , University of Minnesota, MN
Sachin S. Sapatnekar , University of Minnesota, MN
pp. 84-89

Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation (Abstract)

Jing-Yang Jou , National Chiao Tung University, Taiwan
Hui-Ru Jiang , National Chiao Tung University, Taiwan
Yao-Wen Chang , National Chiao Tung University, Taiwan
pp. 90-95

Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations (Abstract)

Hai Zhou , University of Texas, Austin
I-Min Liu , University of Texas, Austin
D. F. Wong , University of Texas, Austin
Adnan Aziz , University of Texas, Austin
pp. 96-99

Crosstalk Minimization using Wire Perturbations (Abstract)

C. L. Liu , National Tsing Hua University, Taiwan
Prashant Saxena , Intel Corporation, Hillsboro, OR
pp. 100-103

Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces (Abstract)

Erik Brunvand , University of Utah, SLC
Kenneth Yun , University of California, San Diego
Steven Nowick , Columbia University, New York
pp. 104-109

Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems (Abstract)

Luciano Lavagno , Univ. of Udine, Italy
Michael Kishinevsky , Intel Corp., USA
Jordi Cortadella , Univ. Polit?cnica, Catalunya, Spain
Alexander Yakovlev , Univ. of Newcastle upon Tyne, UK
Alex Kondratyev , Univ. of Aizu, Japan
pp. 110-115

CAD Directions for High Performance Asynchronous Circuits (Abstract)

Jordi Cortadella , Universitat Polit?cnica de Catalunya, Barcelona, Spain
Steven M. Burns , Intel Corporation, Hillsboro, OR
Shai Rotem , Intel Corporation, Hillsboro, OR
Michael Kishinevsky , Intel Corporation, Hillsboro, OR
Ken Stevens , Intel Corporation, Hillsboro, OR
Ran Ginosar , Intel Corporation, Hillsboro, OR; VLSI Systems Research Center, Technion, Haifa, Israel
Marly Roncken , Intel Corporation, Hillsboro, OR
pp. 116-121

Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses (Abstract)

E. Macii , Politecnico di Torino, Italy
L. Benini , Universit? di Bologna, Italy
A. Macii , Politecnico di Torino, Italy
R. Scarsi , Politecnico di Torino, Italy
M. Poncino , Politecnico di Torino, Italy
pp. 128-133

Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems (Abstract)

Kiyoung Choi , Seoul National University, Korea
Youngsoo Shin , Seoul National University, Korea
pp. 134-139

Memory Exploration for Low Power, Embedded Systems (Abstract)

Wen-Tsong Shiue , Arizona State University, Tempe, AZ
Chaitali Chakrabarti , Arizona State University, Tempe, AZ
pp. 140-145

Distributed Application Development with Inferno (Abstract)

Ravi Sharma , Lucent Technologies, Freehold, NJ
pp. 146-150

Embedded Application Design Using a Real-Time OS (Abstract)

David Hui , Integrated Systems, Inc, Sunnyvale, CA
David Stepner , Integrated Systems, Inc, Sunnyvale, CA
Nagarajan Rajan , Integrated Systems, Inc, Sunnyvale, CA
pp. 151-156

The Jini™ Architecture: Dynamic Services in a Flexible Network (Abstract)

Ken Arnold , Sun Microsystems, Inc., Burlington, MA
pp. 157-162

Verifying Large-Scale Multiprocessor using an Abstract Verification Environment (Abstract)

Dennis Abts , Silicon Graphics Inc., Chippewa Falls, WI
Mike Roberts , Silicon Graphics Inc., Chippewa Falls, WI
pp. 163-168

Functional Verification of the Equator MAP1000 Microprocessor (Abstract)

Guanghui Hu , Equator Technologies Inc., Austin, Texas
Dave Baker , Equator Technologies Inc., Austin, Texas
Jian Shen , The University of Texas at Austin
Tony Hurson , Equator Technologies Inc., Austin, Texas
Chen-chau Chu , Equator Technologies Inc., Austin, Texas
Martin Kinkade , Equator Technologies Inc., Austin, Texas
Gregorio Gervasio , Equator Technologies Inc., Austin, Texas
Jacob Abraham , The University of Texas at Austin
pp. 169-174

Micro Architecture Coverage Directed Generation of Test Programs (Abstract)

Yoav Yadin , IBM Haifa Research Lab
Shmuel Ur , IBM Haifa Research Lab
pp. 175-180

Verification of a Microprocessor Using Real World Applications (Abstract)

Seungjong Lee , KAIST, Taejon, Korea
In-Cheol Park , KAIST, Taejon, Korea
Chong-Min Kyung , KAIST, Taejon, Korea
You-Sung Chang , KAIST, Taejon, Korea
pp. 181-184

High-Level Test Generation for Design Verification of Pipelined Microprocessors (Abstract)

David Van Campenhout , The University of Michigan, Ann Arbor, MI
Trevor Mudge , The University of Michigan, Ann Arbor, MI
John P. Hayes , The University of Michigan, Ann Arbor, MI
pp. 185-188

Developing an Architecture Validation Suite Application to the PowerPC Architecture (Abstract)

Anatoly Koyfman , IBM Research Lab in Haifa
Moshe Levinger , IBM Research Lab in Haifa
Laurent Fournier , IBM Research Lab in Haifa
pp. 189-194

Model Order-Reduction of RC(L) Interconnect including Variational Analysis (Abstract)

Ying Liu , Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Andrzej J. Strojwas , Carnegie Mellon University, Pittsburgh, PA
pp. 201-206

Robust Rational Function Approximation Algorithm for Model Generation (Abstract)

Joel R. Phillips , Cadence Design Systems, San Jose, CA
Carlos P. Coelho , INESC / Cadence European Laboratories, Portugal
L. Miguel Silveira , INESC / Cadence European Laboratories, Portugal
pp. 207-212

Soft Scheduling in High Level Synthesis (Abstract)

Jianwen Zhu , University of California, Irvine, CA
Daniel D. Gajski , University of California, Irvine, CA
pp. 219-224

Graph Coloring Algorithms for Fast Evaluation of Curtis Decompositions (Abstract)

Alan Mishchenko , Portland State University, Oregon
Marek Perkowski , Portland State University, Oregon
Rahul Malvi , Portland State University, Oregon
Mike Burns , Portland State University, Oregon
Stan Grygiel , Portland State University, Oregon
pp. 225-230

Maximizing Performance by Retiming and Clock Skew Scheduling (Abstract)

Eby G. Friedman , University of Rochester, New York
Marios C. Papaefthymiou , University of Michigan, Ann Arbor
Xun Liu , University of Michigan, Ann Arbor
pp. 231-236

A Practical Approach to Multiple-Class Retiming (Abstract)

Klaus Eckl , Technical Univ. of Munich, Germany
Jean Christophe Madre , Synopsys, Inc., France
Christian Legl , Technical Univ. of Munich, Germany
Peter Zepter , Synopsys Inc., Mountain View, CA
pp. 237-242

Performance-Driven Integration of Retiming and Resynthesis (Abstract)

Peichen Pan , Intel Corporation, Hillsboro, OR
pp. 243-246

Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms (Abstract)

M. Poncino , Politecnico di Torino, Italy
E. Macii , Politecnico di Torino, Italy
G. Odasso , Politecnico di Torino, Italy
G. De Micheli , Stanford University, CA
L. Benini , Universit? di Bologna, Italy
pp. 247-252

Customized Instruction-Sets For Embedded Processors (Abstract)

Joseph A. Fisher , Hewlett-Packard Laboratories Cambridge, Cambridge, MA
pp. 253-257

System-Level Hardware/Software Trade-Offs (PDF)

Samuel P. Harbison , Texas Instruments, Monroeville, PA
pp. 258-259

A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning (Abstract)

Youn-Long Lin , Tsing Hua University, Taiwan
Allen C.-H. Wu , Tsing Hua University, Taiwan
Hsiao-Pin Su , Tsing Hua University, Taiwan; Taiwan Semiconductor Manufacturing Company, Ltd., Taiwan
pp. 262-267

An O-Tree Representation of Non-Slicing Floorplan and Its Applications (Abstract)

Takeshi Yoshimura , NEC Corp., Japan
Pei-Ning Guo , Mentor Graphics Corp., San Jose, CA
Chung-Kuan Cheng , Mentor Graphics Corp., San Jose, CA
pp. 268-273

Module Placement for Analog Layout Using the Sequence-Pair Representation (Abstract)

Florin Balasa , Conexant Systems, Newport Beach, CA
Koen Lampaert , Conexant Systems, Newport Beach, CA
pp. 274-279

Performance-Driven Scheduling with Bit-Level Chaining (Abstract)

Kiyoung Choi , Seoul National University, Korea
Sanghun Park , Seoul National University, Korea
pp. 286-291

A Model for Scheduling Protocol-Constrained Components and Environments (Abstract)

Steve Haynal , University of California, Santa Barbara
Forrest Brewer , University of California, Santa Barbara
pp. 292-295

A Reordering Technique for Efficient Code Motion (Abstract)

Luiz C. V. dos Santos , Eindhoven University of Technology, The Netherlands
Jochen A. G. Jess , Eindhoven University of Technology, The Netherlands
pp. 296-299

Coverage Estimation for Symbolic Model Checking (Abstract)

Timothy Kam , Intel Corp.
Pei-Hsin Ho , Synopsys, Inc.
Xudong Zhao , Intel Corp.
Yatin Hoskote , Intel Corp.
pp. 300-305

Improving Symbolic Traversals by Means of Activity Profiles (Abstract)

Paolo Camurati , Politecnico di Torino, Italy
Gianpiero Cabodi , Politecnico di Torino, Italy
Stefano Quer , Politecnico di Torino, Italy
pp. 306-311

Improved Approximate Reachability using Auxiliary State Variables (Abstract)

Shankar G. Govindaraju , Stanford University, CA
Jules P. Bergmann , Stanford University, CA
David L. Dill , Stanford University, CA
pp. 312-316

Symbolic Model Checking using SAT Procedures Instead of BDDs (Abstract)

E. M. Clarke , Carnegie Mellon University, Pittsburgh, PA; Verysys Design Automation, Inc., Fremont, CA
M. Fujita , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
A. Biere , Carnegie Mellon University, Pittsburgh, PA; Verysys Design Automation, Inc., Fremont, CA
Y. Zhu , Carnegie Mellon University, Pittsburgh, PA; Verysys Design Automation, Inc., Fremont, CA
A. Cimatti , Istituto per la Ricerca Scientifica e Tecnolgica (IRST), Italy
pp. 317-320

Global Multimedia System Design Exploration using Accurate Memory Organization Feedback (Abstract)

Erik Brockmeyer , IMEC vzw, Belgium
Miguel Miranda , IMEC vzw, Belgium
Arnout Vandecappelle , IMEC vzw, Belgium
Diederik Verkest , IMEC vzw, Belgium
Francky Catthoor , IMEC vzw, Belgium
pp. 327-332

Implementation of a Scalable MPEG-4 Wavelet-Based Visual Texture Compression System (Abstract)

B. Vanhoof , IMEC, Leuven, Belgium
M. Pe? , IMEC, Leuven, Belgium
L. Nachtergaele , IMEC, Leuven, Belgium
I. Bolsens , IMEC, Leuven, Belgium
J. Bormans , IMEC, Leuven, Belgium
G. Lafruit , IMEC, Leuven, Belgium
pp. 333-336

A 10 Mbit/s Upstream Cable Modem with Automatic Equalization (Abstract)

Serge Vernalde , IMEC vzw, Belgium
Marc Engels , IMEC vzw, Belgium
Patrick Schaumont , IMEC vzw, Belgium
Radim Cmar , IMEC vzw, Belgium
pp. 337-340

Multilevel k-Way Hypergraph Partitioning (Abstract)

Vipin Kumar , University of Minnesota, Minneapolis
George Karypis , University of Minnesota, Minneapolis
pp. 343-348

Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting (Abstract)

Andrew B. Kahng , UCLA Computer Science Department, Los Angeles, CA
Andrew E. Caldwell , UCLA Computer Science Department, Los Angeles, CA
Igor L. Markov , UCLA Computer Science Department, Los Angeles, CA
Andrew A. Kennings , Cypress Semiconductor, Beaverton, OR
pp. 349-354

Hypergraph Partitioning With Fixed Vertices (Abstract)

Andrew E. Caldwell , UCLA Computer Science Department, Los Angeles, CA
Andrew B. Kahng , UCLA Computer Science Department, Los Angeles, CA
Igor L. Markov , UCLA Computer Science Department, Los Angeles, CA
pp. 355-359

Relaxation and Clustering in a Local Search Framework: Application to Linear Placement (Abstract)

Sung-Woo Hur , University of Illinois at Chicago
John Lillis , University of Illinois at Chicago
pp. 360-366

An α-Approximate Algorithm for Delay-Constraint Technology Mapping (Abstract)

Sumit Roy , Cadence Design Systems, Santa Clara, CA
Prithvirai Banerjee , Northwestern University, Evanston, IL
Krishna Belkhale , Cadence Design Systems, Santa Clara, CA
pp. 367-372

Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections (Abstract)

Yean-Yow Hwang , University of California, Los Angeles
Songjie Xu , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 373-378

Automated Phase Assignment for the Synthesis of Low Power Domino Circuits (Abstract)

Priyadarshan Patra , Intel Corporation, Hillsboro, OR
Unni Narayanan , Intel Corporation, Santa Clara, CA
pp. 379-384

Enhancing Simulation with BDDs and ATPG (Abstract)

Malay K. Ganai , The University of Texas at Austin
Adnan Aziz , The University of Texas at Austin
Andreas Kuehlmann , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 385-390

Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits (Abstract)

Valeria Bertacco , Synopsys, Inc., Palo Alto, CA
Stefano Quer , Synopsys, Inc., Mountain View, CA
Maurizio Damiani , Synopsys, Inc., Mountain View, CA
pp. 391-396

Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors (Abstract)

Miroslav N. Velev , Carnegie Mellon University, Pittsburgh, PA
Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
pp. 397-401

Formal Verification Using Parametric Representations of Boolean Constraints (Abstract)

Mark D. Aagaard , Intel Corporation, Hillsboro, OR
Carl-Johan H. Seger , Intel Corporation, Hillsboro, OR
Robert B. Jones , Intel Corporation, Hillsboro, OR
pp. 402-407

Vertical Benchmarks for CAD (Abstract)

Yingfai Tong , Carnegie Mellon University, Pittsburgh, PA
Herman Schmit , Carnegie Mellon University, Pittsburgh, PA
Christopher Inacio , Carnegie Mellon University, Pittsburgh, PA
Ben Klass , Carnegie Mellon University, Pittsburgh, PA
Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
David Nagle , Carnegie Mellon University, Pittsburgh, PA
Andrew Ryan , Carnegie Mellon University, Pittsburgh, PA
pp. 408-413

A Framework for User Assisted Design Space Exploration (Abstract)

G. Quan , University of Notre Dame, IN
X. Hu , University of Notre Dame, IN
S. Ravichandran , Western Michigan University, Kalamazoo, MI
G. W. Greenwood , Western Michigan University, Kalamazoo, MI
pp. 414-419

Fast Prototyping: A System Design Flow Applied to a Complex System-On-Chip Multiprocessor Design (Abstract)

Francois Pogodalla , STMicroelectronics, France
Pierre Coulomb , STMicroelectronics, France
Bernard Ramanadin , STMicroelectronics, San Jose, CA
Benoit Clement , STMicroelectronics, France
Richard Hersemeule , STMicroelectronics, France
Etienne Lantreibecq , STMicroelectronics, France
pp. 420-424

Verification and Management of a Multimillion-Gate Embedded Core Design (Abstract)

Georg Niedrist , Siemens, Austria
Johann Notbauer , Siemens, Austria
Stefan Rohringer , Siemens Semiconductors, Austria
Thomas Albrecht , Siemens, Austria
pp. 425-428

Mixed- Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications (Abstract)

Vivek De , Intel Corp., Hillsboro, OR
Zhanping Chen , Purdue University, W. Lafayette, IN
Kaushik Roy , Purdue University, W. Lafayette, IN
Liqiong Wei , Purdue University, W. Lafayette, IN
Yibin Ye , Intel Corp., Hillsboro, OR
pp. 430-435

Stand-By Power Minimization through Simultaneous Threshold Voltage Selection and Circuit Sizing (Abstract)

Rajendran Panda , Advanced Tools, Motorola Inc., Austin, TX
Chanhee Oh , Advanced Tools, Motorola Inc., Austin, TX
Jingyan Zuo , Advanced Tools, Motorola Inc., Austin, TX
David Blaauw , Advanced Tools, Motorola Inc., Austin, TX
Supamas Sirichotiyakul , Advanced Tools, Motorola Inc., Austin, TX
Abhijit Dharchoudhury , Advanced Tools, Motorola Inc., Austin, TX
Tim Edwards , Advanced Tools, Motorola Inc., Austin, TX
pp. 436-441

Leakage Control With Efficient Use of Transistor Stacks in Single Threshold CMOS (Abstract)

Mark C. Johnson , Rose-Hulman Institute of Technology, Terre Haute, IN
Dinesh Somasekhar , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 442-445

Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation (Abstract)

C. Visweswariah , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
C. B. Whan , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
A. R. Conn , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
P. N. Strenski , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
P. R. O'Brien , IBM Electronic Design Automation, Austin, TX
W. W. Molzen, Jr. , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
I. M. Elfadel , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 452-459

Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization (Abstract)

Chang Wu , University of California, Los Angeles
Honching Li , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 460-465

Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique (Abstract)

Stephen I. Long , University of California, Santa Barbara
Arindam Mukherjee , University of California, Santa Barbara
Ranganathan Sudhakar , Stanford University, CA
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 466-471

MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood Search (Abstract)

Jinan Lou , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
Amir H. Salek , University of Southern California, Los Angeles
pp. 472-478

Buffer Insertion With Accurate Gate and Interconnect Delay Computation (Abstract)

Anirudh Devgan , IBM Austin Research Laboratory, Austin, TX
Stephen T. Quay , IBM Server Group, Austin, TX
Charles J. Alpert , IBM Austin Research Laboratory, Austin, TX
pp. 479-484

Reducing Cross-Coupling among Interconnect Wires in Deep-Submicron Datapath Design (Abstract)

Chong-Min Kyung , KAIST, Korea
Joon-Seo Yim , LG Corporate Institute of Technology, Korea
pp. 485-490

Improved Delay Prediction for On-Chip Buses (Abstract)

Griff L. Bilbro , North Carolina State University, Raleigh, NC
Real G. Pomerleau , North Carolina State University, Raleigh, NC
Paul D. Frazon , North Carolina State University, Raleigh, NC
pp. 497-501

Noise-Aware Repeater Insertion and Wire Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching (Abstract)

Noel Menezes , Intel Corporation, Hillsboro, OR
Chung-Ping Chen , Intel Corporation, Hillsboro, OR
pp. 502-506

Interconnect Estimation and Planning for Deep Submicron Designs (Abstract)

David Zhigang Pan , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 507-510

ECL: A Specification Environment for System-Level Design (Abstract)

Luciano Lavagno , Cadence Berkeley Laboratories, Berkeley, CA
Ellen Sentovich , Cadence Berkeley Laboratories, Berkeley, CA
pp. 511-516

Representation of Function Variants for Embedded System Optimization and Synthesis (Abstract)

R. Ernst , IDA / TU Braunschweig, Germany
D. Ziegenbein , IDA / TU Braunschweig, Germany
J. Teich , DATE / UNI Paderborn, Germany
K. Richter , IDA / TU Braunschweig, Germany
L. Thiele , TIK / ETH Z?rich, Switzerland
pp. 517-522

Vex - A CAD Toolbox (Abstract)

Jules P. Bergmann , Stanford University, CA
Mark A. Horowitz , Stanford University, CA
pp. 523-528

Constraint Management for Collaborative Electronic Design (Abstract)

Stephen W. Director , University of Michigan, Ann Arbor, MI
Juan Antonio Carballo , University of Michigan, Ann Arbor, MI
pp. 529-534

A Multiscale Method for Fast Capacitance Extraction (Abstract)

Johannes Tausch , Southern Methodist University, Dallas, TX
Jacob White , MIT, Cambridge, MA
pp. 537-542

Efficient Capacitance Computation for Structures with Non-Unifrom Adaptive Surface Meshes (Abstract)

Zoltan Cendes , Ansoft Corporation, Pittsburgh PA
Eric Bracken , Ansoft Corporation, Pittsburgh PA
Scott Savage , Ansoft Corporation, Pittsburgh PA
Vikram Jandhyala , Ansoft Corporation, Pittsburgh PA
pp. 543-548

Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation (Abstract)

Ching-Han Tsai , University of Illinois at Urbana-Champaign
Elyse Rosenbaum , University of Illinois at Urbana-Champaign
Sung-Mo (Steve) Kang , University of Illinois at Urbana-Champaign
Tong Li , Silicon Perspective Corp., Santa clara, CA
pp. 549-554

Dynamic Power Management Based on Continuous-Time Markov Decision Processes (Abstract)

Massoud Pedram , University of Southern California, Los Angeles
Qinru Qiu , University of Southern California, Los Angeles
pp. 555-561

Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning (Abstract)

Mauro Chinosi , Central R&D DAIS, SGS-THOMSON Agrate B. (MI), Italy
Roberto Zafalon , Central R&D DAIS, SGS-THOMSON Agrate B. (MI), Italy
Carlo Guardiani , Central R&D DAIS, SGS-THOMSON Agrate B. (MI), Italy
pp. 562-567

Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic (Abstract)

Milos Ercegovac , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
Darko Kirovski , University of California, Los Angeles
pp. 568-573

A Methodology For the Verification of a "System on Chip" (Abstract)

Michael Slavkin , IBM Haifa Research Lab, Haifa, Israel
Daniel Geist , IBM Haifa Research Lab, Haifa, Israel
Karen Holtz , IBM Haifa Research Lab, Haifa, Israel
Andy Long , IBM Field Design Center, Essex Junction, VT
Yvgeny Nustov , IBM Haifa Research Lab, Haifa, Israel
Tamara Arons , IBM Haifa Research Lab, Haifa, Israel
Dave King , IBM Field Design Center, Essex Junction, VT
Monica Farkas , IBM Haifa Research Lab, Haifa, Israel
Steve Barret , IBM Field Design Center, Essex Junction, VT
Giora Biran , IBM Haifa Research Lab, Haifa, Israel
pp. 574-579

ICEBERG: An Embedded In-circuit Emulator Synthesizer for Microcontrollers (Abstract)

Tai-An Lu , National Sun Yat-sen University, Taiwan
Ing-Jer Huang , National Sun Yat-sen University, Taiwan
pp. 580-585

Microprocessor Based Testing for Core-Based System on Chip (Abstract)

C. A. Papachristou , Case Western Reserve University, Cleveland, OH
M. Nourani , Case Western Reserve University, Cleveland, OH
F. Martin , Case Western Reserve University, Cleveland, OH
pp. 586-591

Comparing RTL and Behavioral Design Methodologies in the Case of a 2M-Transistor ATM Shaper (Abstract)

Marco Pavesi , Italtel, Italy
Luca Gazi , Italtel, Italy
Zoltan Sugar , TIMA laboratory, France
Salvatore Crudo , Italtel, Italy
Mario Diaz-Nava , STMicroelectronics, France
Imed Moussa , TIMA laboratory, France
Rodolph Suescun , AREXSYS, France
Ahmed Amine Jerraya , TIMA laboratory, France
pp. 598-603

Engineering Change: Methodology and Applications to Behavioral and System Synthesis (Abstract)

Miodrag Potkonjak , University of California, Los Angeles
Darko Kirovski , University of California, Los Angeles
pp. 604-609

Reconfigurable Computing: What, Why, and Implications for Design Automation (Abstract)

John Wawrzynek , University of California at Berkeley
Andr? DeHon , University of California at Berkeley
pp. 610-615

An Automated Temporal Partitioning and Loop Fission Approach for FPGA based Reconfigurable Synthesis of DSP Applications (Abstract)

Ranga Vemuri , University of Cincinnati, OH
Meenakshi Kaul , University of Cincinnati, OH
Sriram Govindarqjan , University of Cincinnati, OH
Iyad Ouaiss , University of Cincinnati, OH
pp. 616-622

Dynamically Reconfigurable Architecture for Image Processor Applications (Abstract)

Alexandro M. S. Ad?rio , Federal University at Porto Alegre, Brazil
Eduardo L. Roehe , Federal University at Porto Alegre, Brazil
Sergio Bampi , Federal University at Porto Alegre, Brazil
pp. 623-628

Multi-Time Simulation of Voltage-Controlled Oscillators (Abstract)

Jaijeet Roychowdhury , Bell Laboratories, Murray Hill
Onuttom Narayan , University of California, Santa Cruz
pp. 629-634

Efficient Computation of Quasi-Periodic Circuit Operating Conditions via a Mixed Frequency/Time Approach (Abstract)

Keith Nabors , Cadence Design Systems, San Jose, CA
Joel Phillips , Cadence Design Systems, San Jose, CA
Ken Kundert , Cadence Design Systems, San Jose, CA
Dan Feng , Cadence Design Systems, San Jose, CA
Jacob White , Massachusetts Institute of Technology, Cambridge, MA
pp. 635-640

Time-Mapped Harmonic Balance (Abstract)

Ognen J. Nastov , Motorola, Inc., Austin, TX
Jacob K. White , Massachusetts Institute of Technology, Cambridge, MA
pp. 641-646

Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor (Abstract)

Jacob A. Abraham , The University of Texas at Austin
Raghuram S. Tupuri , Advanced Micro Devices, Austin Texas
Arun Krishnamachary , The University of Texas at Austin
pp. 647-652

PROPTEST: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction (Abstract)

Ruifeng Guo , University of Iowa, Iowa City
Irith Pomeranz , University of Iowa, Iowa City
Sudhakar M. Reddy , University of Iowa, Iowa City
pp. 653-658

Multiple Error Diagnosis Based on Xlists (Abstract)

Jawahar Jain , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
Rajarshi Mukherjee , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
Vamsi Boppana , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
Masahiro Fujita , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
Pradeep Bollineni , Iowa State University, Ames, IA
pp. 660-665

Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage (Abstract)

Srinivas Devadas , MIT, Cambridge
Pranav Ashar , NEC USA, Princeton
Farzan Fallah , Fujitsu Labs. of America, Inc., Sunnyvale, CA
pp. 666-671

A Two-State Methodology for RTL Logic Simulation (Abstract)

Lionel Bening , Hewlett-Packard Company, Richardson, TX
pp. 672-677

An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications (Abstract)

Francisco Nascimento , University of T?bingen
Wolfgang Rosenstiel , University of T?bingen and FZI
Cordula Hansen , Forschungszentrum Informatik (FZI) at the University of Karlsruhe
pp. 678-683

A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware (Abstract)

Miron Abramovici , Bell Labs - Lucent Technologies, Murray Hill, NJ
Daniel Saab , Case Western Reserve University, Cleveland, Ohio
Jose T. de Sousa , Bell Labs - Lucent Technologies, Murray Hill, NJ
pp. 684-690

Dynamic Fault Diagnosis on Reconfigurable Hardware (Abstract)

Fatih Kocan , Case Western Reserve University, Cleveland, Ohio
Daniel G. Saab , Case Western Reserve University, Cleveland, Ohio
pp. 691-696

Hardware Compilation for FPGA-based Configurable Computing Machines (Abstract)

Bill Lin , University of California, San Diego
Xiaohan Zhu , University of California, San Diego
pp. 697-702

0.18μm CMOS and Beyond (Abstract)

D. J. Eaglesham , Bell Labs, Lucent Technologies, Murray Hill, NJ
pp. 703-708

SO1 Digital CMOS VLSI - A Design Perspective (Abstract)

R. Puri , IBM T. J. Watson Research Center, Yorktown Heights, NY
C. T. Chuang , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 709-714

Equivalent Elmore Delay for RLC Trees (Abstract)

Jose L. Neves , IBM Microelectronics, East Fishkill, New York
Yehea I. Ismail , University of Rochester, New York
Eby G. Friedman , University of Rochester, New York
pp. 715-720

Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits (Abstract)

Yehea I. Ismail , University of Rochester, New York
Eby G. Friedman , University of Rochester, New York
pp. 721-724

Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints (Abstract)

Robert K. Brayton , University of California, Berkeley, CA
Abdallah Tabbara , University of California, Berkeley, CA
A. Richard Newton , University of California, Berkeley, CA
pp. 725-730

Functional Timing Analysis for IP Characterization (Abstract)

Robert Palermo , Cadence Design Systems, San Jose, CA
Karem Sakallah , University of Michigan, Ann Arbor
Hakan Yalcin , Cadence Design Systems, San Jose, CA
Cyrus Bamji , Cadence Design Systems, San Jose, CA
Mohammad Mortazavi , Cadence Design Systems, San Jose, CA
pp. 731-736

Detecting False Timing Paths: Experiments on PowerPC™ Microprocessors (Abstract)

Richard Raimi , Motorola Corp., Austin, TX
Jacob Abraham , The University of Texas at Austin
pp. 737-741

On ILP Formulations for Built-In Self-Testable Data Path Synthesis (PDF)

Han Bin Kim , Virginia Tech, Blacksburg
Dong Sam Ha , Virginia Tech, Blacksburg
Takeshi Takahashi , Advantest Lab. Ltd., Japan
pp. 742-747

Improving The Test Quality for Scan-Based BIST Using A General Test Application Scheme (Abstract)

Huan-Chih Tsai , University of California, Santa Barbara
Kwang-Ting Cheng , University of California, Santa Barbara
Sudipta Bhawmik , Lucent Technologies, Princeton, NJ
pp. 748-753

Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices (Abstract)

Yi-Min Jiang , University of California, Santa Barbara
Kwang-Ting Cheng , University of California, Santa Barbara
pp. 760-765

A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs (Abstract)

Seong-Ok Bae , LG Corporate Institute of Technology, Korea
Joon-Seo Yim , LG Corporate Institute of Technology, Korea
Chong-Min Kyung , KAIST, Korea
pp. 766-771

Digital Detection of Analog Parametric Faults in SC Filters (Abstract)

Ramesh Harjani , University of Minnesota, Minneapolis
Bapiraju Vinnakota , University of Minnesota, Minneapolis
pp. 772-777

Application of High Level Interface-Based Design to Telecommunications System Hardware (Abstract)

M.M. Kamal Hashmi , International Computers Ltd., UK
Dyson Wilkes , Ericsson Components Ltd., UK
pp. 778-783

Hardware Reuse at the Behavioral Level (Abstract)

Patrick Schaumont , IMEC vzw, Belgium
Ivo Bolsens , IMEC vzw, Belgium
Marc Engels , IMEC vzw, Belgium
Serge Vernalde , IMEC vzw, Belgium
Radim Cmar , IMEC vzw, Belgium
pp. 784-789

Description and Simulation of Hardware/Software Systems with Java (Abstract)

Tommy Kuhn , University of T?bingen, Germany
Wolfgang Rosenstiel , University of T?bingen, Germany
Udo Kebschull , University of Leipzig, Germany
pp. 790-793

Java Driven Codesign and Prototyping of Networked Embedded Systems (Abstract)

Klaus Buchenrieder , Siemens AG, Germany
Rainer Kress , Siemens AG, Germany
Josef Fleischmann , Technical University of Munich, Germany
pp. 794-797

Subwavelength Lithography and its Potential Impact on Design and EDA (Abstract)

Y. C. Pati , Numerical Technologies, Inc., Santa Clara, CA
Andrew B. Kahng , UCLA Department of Computer Science
pp. 799-804

Synthesis of Embedded Software Using Free-Choice Petri Nets (Abstract)

Yosinori Watanabe , Cadence Design Systems
Alberto Sangiovanni-Vincentelli , University of California, Berkeley, CA
Luciano Lavagno , Cadence Design Systems
Marco Sgroi , University of California, Berkeley, CA
pp. 805-810

Exact Memory Size Estimation for Array Computations without Loop Unrolling (Abstract)

Ying Zhao , Princeton University, New Jersey
Sharad Malik , Princeton University, New Jersey
pp. 811-816

Constraint Driven Code Selection for Fixed-Point DSPs (Abstract)

Rainer Leupers , University of Dortmund, Germany
Steven Bashford , University of Dortmund, Germany
pp. 817-822

Rapid Development of Optimized DSP Code From a High Level Description Through Software Estimations (Abstract)

Michel Auguin , Universit? de Nice, France
Alain Pegatoquet , VLSI Technology, France
Luc Bianco , Universit? de Nice, France
Emmanuel Gresset , VLSI Technology, France
pp. 823-826

Software Environment for a Multiprocessor DSP (Abstract)

Asawaree Kalavade , Lucent Technologies, Murray Hill, NJ
Joe Othmer , Lucent Technologies, NJ
K. J. Singh , Lucent Technologies, NJ
Bryan Ackland , Lucent Technologies, NJ
pp. 827-830

Effective Iterative Techniques for Fingerprinting Design IP (Abstract)

Hyun-Jin Choi , UCLA Computer Science Dept.
Miodrag Potkonjak , UCLA Computer Science Dept.
Jennifer L. Wong , UCLA Computer Science Dept.
Andrew E. Caldwell , UCLA Computer Science Dept.
Andrew B. Kahng , UCLA Computer Science Dept.
Gang Qu , UCLA Computer Science Dept.
Stefanus Mantik , UCLA Computer Science Dept.
pp. 843-848

Behavioral Synthesis Techniques for Intellectual Property Protection (Abstract)

Miodrag Potkonjak , University of California, Los Angeles, CA
Inki Hong , Synopsys, Inc., Mountain View, CA; University of California, Los Angeles, CA
pp. 849-854

Design and Implementation of a Scalable Encryption Processor with Embedded Variable DC/DC Converter (Abstract)

Abram P. Dancy , SynQor, Hudson, MA
Anantha Chandrakasan , Massachusetts Institute of Technology, Cambridge, MA
James Goodman , Massachusetts Institute of Technology, Cambridge, MA
pp. 855-860

Design Considerations for Battery-Powered Electronics (Abstract)

Massoud Pedram , University of Southern California, Los Angeles
Qing Wu , University of Southern California, Los Angeles
pp. 861-866

Cycle-Accurate Simulation of Energy Consumption in Embedded Systems (Abstract)

Giovanni De Micheli , Stanford University, Italy
Luca Benini , Stanford University, Italy
Tajana Simunic , Stanford University, Italy
pp. 867-872

Lowering power consumption in clock by using Globally Asynchronous Locally Synchronous design style (Abstract)

P. Ellervee , KTH, Sweden
P. Nilsson , Lund University, Sweden
D. Lundqvist , Ericsson Radio Systems AB, Stockholm, Sweden
S. Kumar , Indian Institute of Technology, New Delhi, India
T. Olsson , Lund University, Sweden
T. Meincke , KTH, Sweden
A. Postula , University of Queensland, Brisbane, Australia
A. Hemani , KTH, Sweden
J. Oberg , KTH, Sweden
pp. 873-878

A CAD Tool for Optical MEMS (Abstract)

Kurt R. Prough , University of Pittsburgh, PA
Philippe J. Marchand , University of California, San Diego
Steven P. Levitan , University of Pittsburgh, PA
Jose A. Martinez , University of Pittsburgh, PA
Donald M. Chiarulli , University of Pittsburgh, PA
Timothy P. Kurzweg , University of Pittsburgh, PA
pp. 879-884

On Thermal Effects in Deep Sub-Micron VLSI Interconnects (Abstract)

Alberto Sangiovanni-Vincentelli , University of California, Berkeley, CA
Chenming Hu , University of California, Berkeley, CA
Amit Mehrotra , University of California, Berkeley, CA
Kaustav Banerjee , University of California, Berkeley, CA
pp. 885-891

Converting a 64b PowerPC Processor from CMOS Bulk to SOI Technology (Abstract)

D. Behrends , IBM Corporation, Rochester, MN
B. Stanisic , IBM Corporation, Rochester, MN
D. Allen , IBM Corporation, Rochester, MN
pp. 892-897

A Framework for Collaborative and Distributed Web-Based Design (Abstract)

Anantha Chandrakasan , Massachusetts Institute of Technology, Cambridge, MA
Gangadhar Konduri , Massachusetts Institute of Technology, Cambridge, MA
pp. 898-903

Dealing with Inductance in High-Speed Chip Design (Abstract)

Albert Ruehli , IBM T. J. Watson Research Center, Yorktown Heights, NY
Steven G. Walker , IBM T. J. Watson Research Center, Yorktown Heights, NY
Phillip Restle , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 904-909

Interconnect Analysis: From 3-D Structures to Circuit Models (Abstract)

M. Kamon , Massachusetts Institute of Technology, Cambridge, MA
N. Marques , Massachusetts Institute of Technology, Cambridge, MA
J. White , Massachusetts Institute of Technology, Cambridge, MA
L. Silveira , Massachusetts Institute of Technology, Cambridge, MA
Y. Massoud , Massachusetts Institute of Technology, Cambridge, MA
pp. 910-914

IC Analyses Including Extracted Inductance Models (Abstract)

Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Michael W. Beattie , Carnegie Mellon University, Pittsburgh, PA
pp. 915-920

On-chip Inductance Issues in Multiconductor Systems (Abstract)

Shannon V. Morton , Compaq Computer Corporation, Shrewsbury, MA
pp. 921-926

A Methodology for Accurate Performance Evaluation in Architecture Exploration (Abstract)

Pietro Russo , Massachusetts Institute of Technology, Cambridge, MA
Srinivas Devadas , Massachusetts Institute of Technology, Cambridge, MA
George Hadjiyiannis , Massachusetts Institute of Technology, Cambridge, MA
pp. 927-932

LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures (Abstract)

Andreas Hoffmann , Aachen University of Technology, Germany
Heinrich Meyr , Aachen University of Technology, Germany
Vojin Zivojnovic , AXYS Design Automation, Inc., Irvine, CA
Stefan Pees , Aachen University of Technology, Germany
pp. 933-938

Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software (Abstract)

Chong-Min Kyung , Korea Advanced Institute of Science and Technology, Taejon, Korea
Ju Hwan Yi , Korea Advanced Institute of Science and Technology, Taejon, Korea
Jong-Yeol Lee , Korea Advanced Institute of Science and Technology, Taejon, Korea
In-Cheol Park , Korea Advanced Institute of Science and Technology, Taejon, Korea
Hoon Choi , Korea Advanced Institute of Science and Technology, Taejon, Korea
pp. 939-944

MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells (Abstract)

Rodney Phelps , Carnegie Mellon University, Pittsburgh, Pennsylvania
L. Richard Carley , Carnegie Mellon University, Pittsburgh, Pennsylvania
Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, Pennsylvania
Michael Krasnicki , Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 945-950

Behavioral Synthesis of Analog Systems using Two-Layered Design Space Exploration (Abstract)

Adrian Nunez-Aldana , University of Cincinnati, OH
Nagu Dhanwada , University of Cincinnati, OH
Sree Ganesan , University of Cincinnati, OH
Alex Doboli , University of Cincinnati, OH
Ranga Vemuri , University of Cincinnati, OH
pp. 951-957

Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits (Abstract)

Walter Daems , Katholieke Universiteit Leuven, Belgium
Willy Sansen , Katholieke Universiteit Leuven, Belgium
Georges Gielen , Katholieke Universiteit Leuven, Belgium
pp. 958-963

Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification (Abstract)

Dipankar Talukdar , Conexant Systems, Newport Beach, CA
Lisa Guerra , Conexant Systems, Newport Beach, CA
Chris Schl?ger , AXYS GmbH, Germany
Joachim Fitzner , AXYS GmbH, Germany
Bassam Tabbara , UC Berkeley EECS Dept.
Vojin Zivojnovic , AXYS GmbH, Germany
pp. 964-969

A Study in Coverage-Driven Test Generation (Abstract)

Alan Hartman , IBM Science and Technology, Haifa, Israel
Gerard Mas , STMicroelectronics, Meylan, France
Ralph Smeets , STMicroelectronics, Meylan, France
Daniel Geist , IBM Science and Technology, Haifa, Israel
Mike Benjamin , STMicroelectronics, UK
Yaron Wolfsthal , IBM Science and Technology, Haifa, Israel
pp. 970-975

IC Test Using the Energy Consumption Ratio (Abstract)

Bapiraju Vinnakota , University of Minnesota, Minneapolis
Wanli Jiang , University of Minnesota, Minneapolis
pp. 976-981

Design Strategy of On-Chip Inductors for Highly Integrated RF Systems (Abstract)

S. Simon Wong , Stanford University, Stanford, CA
C. Patrick Yue , T-Span Systems Corporation, Palo Alto, CA
pp. 982-987

The Simulation and Design of Integrated Inductors (Abstract)

A. J. Becker , Bell Laboratories, Lucent Technologies, Murray Hill, NJ
M. Tsai , Bell Laboratories, Lucent Technologies, Murray Hill, NJ
K. L. Tokuda , Bell Laboratories, Lucent Technologies, Murray Hill, NJ
N. R. Belk , Bell Laboratories, Lucent Technologies, Holmdel NJ
M. R. Frei , Bell Laboratories, Lucent Technologies, Murray Hill, NJ
pp. 988-993

Optimization of Inductor Circuits via Geometric Programming (Abstract)

Maria del Mar Hershenson , Stanford University, Stanford CA
Sunderarajan S. Mohan , Stanford University, Stanford CA
Thomas H. Lee , Stanford University, Stanford CA
Stephen P. Boyd , Stanford University, Stanford CA
pp. 994-998
96 ms
(Ver )