An Efficient Lyapunov Equation-Based Approach for Generating Reduced-Order Models of Interconnect (Abstract)

Error Bounded Pad? Approximation via Bilinear Conformal Transformation (Abstract)

Model-Reduction of Nonlinear Circuits Using Krylov-Space Techniques (Abstract)

ENOR: Model Order Reduction of RLC Circuits Using Nodal Equations for Efficient Factorization (Abstract)

Why is ATPG Easy? (Abstract)

Using Lower Bounds during Dynamic BDD Minimization (Abstract)

Optimization-Intensive Watermarking Techniques for Decision Problems (Abstract)

Efficient Algorithms for Optimum Cycle Mean and Optimum Cost to Time Ratio Problems (Abstract)

IP-Based Design Methodology (PDF)

ipChinook: An Integrated IP-Based Design Framework for Distributed Embedded Systems (Abstract)

Virtual Simulation of Distributed IP-Based Designs (Abstract)

Common-Case Computation: A High-Level Technique for Power and Performance Optimization (Abstract)

Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-Based Designs (Abstract)

Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications (Abstract)

Synthesis of Low Power CMOS VLSI Circuits using Dual Supply Voltages (Abstract)

HW and SW in Embedded System Design: Loveboat, Shipwreck, or Ships Passing in the Night (PDF)

Reliability-Constrained Area Optimization of VLSI Power/Ground Networks Via Sequence of Linear Programmings (Abstract)

FAR-DS: Full-plane AWE Routing with Driver Sizing (Abstract)

Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation (Abstract)

Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations (Abstract)

Crosstalk Minimization using Wire Perturbations (Abstract)

Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces (Abstract)

Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems (Abstract)

CAD Directions for High Performance Asynchronous Circuits (Abstract)

A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems (Abstract)

Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses (Abstract)

Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems (Abstract)

Memory Exploration for Low Power, Embedded Systems (Abstract)

Distributed Application Development with Inferno (Abstract)

Embedded Application Design Using a Real-Time OS (Abstract)

The Jini™ Architecture: Dynamic Services in a Flexible Network (Abstract)

Verifying Large-Scale Multiprocessor using an Abstract Verification Environment (Abstract)

Functional Verification of the Equator MAP1000 Microprocessor (Abstract)

Micro Architecture Coverage Directed Generation of Test Programs (Abstract)

Verification of a Microprocessor Using Real World Applications (Abstract)

High-Level Test Generation for Design Verification of Pipelined Microprocessors (Abstract)

Developing an Architecture Validation Suite Application to the PowerPC Architecture (Abstract)

Passive Reduced-Order Models for Interconnect Simulation and their Computation via Krylov-Subspace Algorithms (Abstract)

Model Order-Reduction of RC(L) Interconnect including Variational Analysis (Abstract)

Robust Rational Function Approximation Algorithm for Model Generation (Abstract)

Behavioral Network Graph: Unifying the Domains of High-Level and Logic Synthesis (Abstract)

Soft Scheduling in High Level Synthesis (Abstract)

Graph Coloring Algorithms for Fast Evaluation of Curtis Decompositions (Abstract)

Maximizing Performance by Retiming and Clock Skew Scheduling (Abstract)

A Practical Approach to Multiple-Class Retiming (Abstract)

Performance-Driven Integration of Retiming and Resynthesis (Abstract)

Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms (Abstract)

Customized Instruction-Sets For Embedded Processors (Abstract)

System-Level Hardware/Software Trade-Offs (PDF)

Functional Verification - Real Users, Real Problems, Real Opportunities (PDF)

A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning (Abstract)

An O-Tree Representation of Non-Slicing Floorplan and Its Applications (Abstract)

Module Placement for Analog Layout Using the Sequence-Pair Representation (Abstract)

Genetic List Scheduling Algorithm for Scheduling and Allocation on a Loosely Coupled Heterogeneous Multiprocessor System (Abstract)

Performance-Driven Scheduling with Bit-Level Chaining (Abstract)

A Model for Scheduling Protocol-Constrained Components and Environments (Abstract)

A Reordering Technique for Efficient Code Motion (Abstract)

Coverage Estimation for Symbolic Model Checking (Abstract)

Improving Symbolic Traversals by Means of Activity Profiles (Abstract)

Improved Approximate Reachability using Auxiliary State Variables (Abstract)

Symbolic Model Checking using SAT Procedures Instead of BDDs (Abstract)

Power Efficient Mediaprocessors: Design Space Exploration (Abstract)

Global Multimedia System Design Exploration using Accurate Memory Organization Feedback (Abstract)

Implementation of a Scalable MPEG-4 Wavelet-Based Visual Texture Compression System (Abstract)

A 10 Mbit/s Upstream Cable Modem with Automatic Equalization (Abstract)

Cell Libraries-Build vs. Buy; Static vs. Dynamic (PDF)

Multilevel k-Way Hypergraph Partitioning (Abstract)

Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting (Abstract)

Hypergraph Partitioning With Fixed Vertices (Abstract)

Relaxation and Clustering in a Local Search Framework: Application to Linear Placement (Abstract)

An α-Approximate Algorithm for Delay-Constraint Technology Mapping (Abstract)

Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections (Abstract)

Automated Phase Assignment for the Synthesis of Low Power Domino Circuits (Abstract)

Enhancing Simulation with BDDs and ATPG (Abstract)

Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits (Abstract)

Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors (Abstract)

Formal Verification Using Parametric Representations of Boolean Constraints (Abstract)

Vertical Benchmarks for CAD (Abstract)

A Framework for User Assisted Design Space Exploration (Abstract)

Fast Prototyping: A System Design Flow Applied to a Complex System-On-Chip Multiprocessor Design (Abstract)

Verification and Management of a Multimillion-Gate Embedded Core Design (Abstract)

Parasitic Extraction Accuracy; How Much is Enough? (PDF)

Mixed- Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications (Abstract)

Stand-By Power Minimization through Simultaneous Threshold Voltage Selection and Circuit Sizing (Abstract)

Leakage Control With Efficient Use of Transistor Stacks in Single Threshold CMOS (Abstract)

A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design (Abstract)

Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation (Abstract)

Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization (Abstract)

Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique (Abstract)

MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood Search (Abstract)

Buffer Insertion With Accurate Gate and Interconnect Delay Computation (Abstract)

Reducing Cross-Coupling among Interconnect Wires in Deep-Submicron Datapath Design (Abstract)

A Novel VLSI Layout Fabric for Deep Sub-Micron Applications (Abstract)

Improved Delay Prediction for On-Chip Buses (Abstract)

Noise-Aware Repeater Insertion and Wire Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching (Abstract)

Interconnect Estimation and Planning for Deep Submicron Designs (Abstract)

ECL: A Specification Environment for System-Level Design (Abstract)

Representation of Function Variants for Embedded System Optimization and Synthesis (Abstract)

Vex - A CAD Toolbox (Abstract)

Constraint Management for Collaborative Electronic Design (Abstract)

MEMS CAD Beyond Multi-Million Transistors (PDF)

A Multiscale Method for Fast Capacitance Extraction (Abstract)

Efficient Capacitance Computation for Structures with Non-Unifrom Adaptive Surface Meshes (Abstract)

Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation (Abstract)

Dynamic Power Management Based on Continuous-Time Markov Decision Processes (Abstract)

Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning (Abstract)

Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic (Abstract)

A Methodology For the Verification of a "System on Chip" (Abstract)

ICEBERG: An Embedded In-circuit Emulator Synthesizer for Microcontrollers (Abstract)

Microprocessor Based Testing for Core-Based System on Chip (Abstract)

Using Partitioning to Help Convergence in the Standard-Cell Design Automation Methodology (Abstract)

Comparing RTL and Behavioral Design Methodologies in the Case of a 2M-Transistor ATM Shaper (Abstract)

Engineering Change: Methodology and Applications to Behavioral and System Synthesis (Abstract)

Reconfigurable Computing: What, Why, and Implications for Design Automation (Abstract)

An Automated Temporal Partitioning and Loop Fission Approach for FPGA based Reconfigurable Synthesis of DSP Applications (Abstract)

Dynamically Reconfigurable Architecture for Image Processor Applications (Abstract)

Multi-Time Simulation of Voltage-Controlled Oscillators (Abstract)

Efficient Computation of Quasi-Periodic Circuit Operating Conditions via a Mixed Frequency/Time Approach (Abstract)

Time-Mapped Harmonic Balance (Abstract)

Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor (Abstract)

PROPTEST: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction (Abstract)

Multiple Error Diagnosis Based on Xlists (Abstract)

Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage (Abstract)

A Two-State Methodology for RTL Logic Simulation (Abstract)

An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications (Abstract)

A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware (Abstract)

Dynamic Fault Diagnosis on Reconfigurable Hardware (Abstract)

Hardware Compilation for FPGA-based Configurable Computing Machines (Abstract)

0.18μm CMOS and Beyond (Abstract)

SO1 Digital CMOS VLSI - A Design Perspective (Abstract)

Equivalent Elmore Delay for RLC Trees (Abstract)

Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits (Abstract)

Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints (Abstract)

Functional Timing Analysis for IP Characterization (Abstract)

Detecting False Timing Paths: Experiments on PowerPC™ Microprocessors (Abstract)

On ILP Formulations for Built-In Self-Testable Data Path Synthesis (PDF)

Improving The Test Quality for Scan-Based BIST Using A General Test Application Scheme (Abstract)

Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences (Abstract)

Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices (Abstract)

A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs (Abstract)

Digital Detection of Analog Parametric Faults in SC Filters (Abstract)

Application of High Level Interface-Based Design to Telecommunications System Hardware (Abstract)

Hardware Reuse at the Behavioral Level (Abstract)

Description and Simulation of Hardware/Software Systems with Java (Abstract)

Java Driven Codesign and Prototyping of Networked Embedded Systems (Abstract)

Subwavelength Lithography: How Will it Affect Your Design Flow? (PDF)

Subwavelength Lithography and its Potential Impact on Design and EDA (Abstract)

Synthesis of Embedded Software Using Free-Choice Petri Nets (Abstract)

Exact Memory Size Estimation for Array Computations without Loop Unrolling (Abstract)

Constraint Driven Code Selection for Fixed-Point DSPs (Abstract)

Rapid Development of Optimized DSP Code From a High Level Description Through Software Estimations (Abstract)

Software Environment for a Multiprocessor DSP (Abstract)

Robust FPGA Intellectual Property Protection Through Multiple Small Watermarks (Abstract)

Robust Techniques For Watermarking Sequential Circuit Designs (Abstract)

Effective Iterative Techniques for Fingerprinting Design IP (Abstract)

Behavioral Synthesis Techniques for Intellectual Property Protection (Abstract)

Design and Implementation of a Scalable Encryption Processor with Embedded Variable DC/DC Converter (Abstract)

Design Considerations for Battery-Powered Electronics (Abstract)

Cycle-Accurate Simulation of Energy Consumption in Embedded Systems (Abstract)

Lowering power consumption in clock by using Globally Asynchronous Locally Synchronous design style (Abstract)

A CAD Tool for Optical MEMS (Abstract)

On Thermal Effects in Deep Sub-Micron VLSI Interconnects (Abstract)

Converting a 64b PowerPC Processor from CMOS Bulk to SOI Technology (Abstract)

A Framework for Collaborative and Distributed Web-Based Design (Abstract)

Dealing with Inductance in High-Speed Chip Design (Abstract)

Interconnect Analysis: From 3-D Structures to Circuit Models (Abstract)

IC Analyses Including Extracted Inductance Models (Abstract)

On-chip Inductance Issues in Multiconductor Systems (Abstract)

A Methodology for Accurate Performance Evaluation in Architecture Exploration (Abstract)

LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures (Abstract)

Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software (Abstract)

MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells (Abstract)

Behavioral Synthesis of Analog Systems using Two-Layered Design Space Exploration (Abstract)

Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits (Abstract)

Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification (Abstract)

A Study in Coverage-Driven Test Generation (Abstract)

IC Test Using the Energy Consumption Ratio (Abstract)

Design Strategy of On-Chip Inductors for Highly Integrated RF Systems (Abstract)

The Simulation and Design of Integrated Inductors (Abstract)

Optimization of Inductor Circuits via Geometric Programming (Abstract)

What is the Proper System on Chip Design Methodology? (PDF)