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Proceedings 1998 Design and Automation Conference. 35th DAC (1998)
San Francisco, CA, USA
June 15, 1998 to June 19, 1998
ISBN: 0-89791-964-5
TABLE OF CONTENTS

Automatic synthesis of interfaces between incompatible protocols (PDF)

R. Passerone , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 8-13

Automated composition of hardware components (PDF)

J. Smith , Stanford Univ., CA, USA
pp. 14-19

Efficient analog test methodology based on adaptive algorithms (PDF)

L. Carro , Dept. de Engenharia Eletrica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 32-37

Design methodology used in a single-chip CMOS 900 MHz spread-spectrum wireless transceiver (PDF)

J. Rael , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 44-49

A video signal processor for MIMD multiprocessing (PDF)

J. Hilgenstock , Lab. fur Informationstechnol., Hannover Univ., Germany
pp. 50-55

A multiprocessor DSP system using PADDI-2 (PDF)

R.A. Sutton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 62-65

Design methodologies for noise in digital integrated circuits (PDF)

K.L. Shepard , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
pp. 94-99

The DT-model: high-level synthesis using data transfers (PDF)

S. Tarafdar , Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
pp. 114-117

Rate optimal VLSI design from data flow graph (PDF)

Moonwook Oh , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
pp. 118-121

Planning for performance (PDF)

R.H.J.M. Otten , California Univ., Berkeley, CA, USA
pp. 122-127

A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together (PDF)

A.H. Salek , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 128-133

Framework encapsulations: a new approach to CAD tool interoperability (PDF)

P.R. Sutton , Cooperative Res. Centre for Satellite Syst., Queensland Univ. of Technol., Brisbane, Qld., Australia
pp. 134-139

A geographically distributed framework for embedded system design and validation (PDF)

K. Hines , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 140-145

WELD-an environment for Web-based electronic design (PDF)

F.L. Chan , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 146-151

Power optimization of variable voltage core-based systems (PDF)

Inki Hong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 176-181

Policy optimization for dynamic power management (PDF)

G.A. Paleologo , Dept. of Eng.-Econ. Syst., Stanford Univ., CA, USA
pp. 182-187

Fast exact minimization of BDDs (PDF)

R. Drechsler , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
pp. 200-205

Boolean matching for large libraries (PDF)

U. Hinsberger , HighTec EDV-Syst. GmbH, Saarbrucken, Germany
pp. 206-211

A fast hierarchical algorithm for 3-D capacitance extraction (PDF)

Weiping Shi , Dept. of Comput. Sci., Univ. of North Texas, Denton, TX, USA
pp. 212-217

Validation of an architectural level power analysis technique (PDF)

Rita Yu Chen , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 242-245

Hierarchical algorithms for assessing probabilistic constraints on system performance (PDF)

G. De Veciana , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 251-256

A tool for performance estimation of networked embedded end-systems (PDF)

A. Kalavade , DSP & VLSI Syst. Res. Dept., Bell Labs., Holmdel, NJ, USA
pp. 257-262

Rate derivation and its applications to reactive, real-time embedded systems (PDF)

A. Dasdan , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 263-268

Generic global placement and floorplanning (PDF)

H. Eisenmann , Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
pp. 269-274

Congestion driven quadratic placement (PDF)

P.N. Parakh , Michigan Univ., Ann Arbor, MI, USA
pp. 275-278

Potential NRG: placement with incomplete data (PDF)

Maogang Wang , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
pp. 279-282

Layout extraction and verification methodology for CMOS I/O circuits (PDF)

Tong Li , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 291-296

A methodology for guided behavioral-level optimization (PDF)

L. Guerra , VLSI Archit. Group, Rockwell Int. Corp., Newport Beach, CA, USA
pp. 309-314

What's between simulation and formal verification? (PDF)

D.L. Dill , Stanford Univ., CA, USA
pp. 328-329

Optimal FPGA mapping and retiming with efficient initial state computation (PDF)

Jason Gong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 330-335

M32: a constructive multilevel logic synthesis system (PDF)

V.N. Kravets , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 336-341

Efficient Boolean division and substitution (PDF)

Shih-Chieh Chang , Nat. Chung Cheng Univ., Chiayi, Taiwan
pp. 342-347

Delay-optimal technology mapping by DAG covering (PDF)

Y. Kukimoto , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 348-351

A fast fanout optimization algorithm for near-continuous buffer libraries (PDF)

D.S. Kung , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 352-355

Performance driven multi-layer general area routing for PCB/MCM designs (PDF)

J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 356-361

Table-lookup methods for improved performance-driven routing (PDF)

J. Lillis , Dept. of Electr. Eng. & Comput. Sci., Chicago Univ., IL, USA
pp. 368-373

Global routing with crosstalk constraints (PDF)

H. Zhou , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 374-377

Timing and crosstalk driven area routing (PDF)

Hsiao-Ping Tseng , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 378-381

Process multi-circuit optimization (PDF)

A. Lokanathan , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 382-387

A statistical performance simulation methodology for VLSI circuits (PDF)

M. Orshansky , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 402-407

RF IC design challenges (PDF)

B. Razavi , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 408-413

Efficient coloring of a large spectrum of graphs (PDF)

D. Kirovski , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 427-432

Arithmetic optimization using carry-save-adders (PDF)

Taewhan Kim , Synopsys Inc., Mountain View, CA, USA
pp. 433-438

Incremental CTL model checking using BDD subsetting (PDF)

A. Pardo , Mentor Graphics Corp., Beaverton, OR, USA
pp. 457-462

PRIMO: probability interpretation of moments for delay calculation (PDF)

R. Kay , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 463-468

ftd: an exact frequency to time domain conversion for reduced order RLC interconnect models (PDF)

Ying Liu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 469-472

Extending moment computation to 2-port circuit representations (PDF)

Fang-Jou Liu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 473-476

Design and optimization of low voltage high performance dual threshold CMOS circuits (PDF)

Liqiong Wei , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 489-494

MTCMOS hierarchical sizing based on mutual exclusive discharge patterns (PDF)

J. Kao , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 495-500

Software synthesis of process-based concurrent programs (PDF)

B. Lin , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 502-505

Don't care-based BDD minimization for embedded software (PDF)

Youpyo Hong , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 506-509

Code compression for embedded systems (PDF)

H. Lekatsas , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 516-521

A decision procedure for bit-vector arithmetic (PDF)

C.W. Barrett , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 522-527

Functional vector generation for HDL models using linear programming and 3-satisfiability (PDF)

F. Fallah , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 528-533

A fast and low cost testing technique for core-based system-on-chip (PDF)

I. Ghosh , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 542-547

Hierarchical functional timing analysis (PDF)

Y. Kukimoto , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 580-585

Making complex timing relationships readable: Presburger formula simplification using don't cares (PDF)

T. Amon , Dept. of Comput. Sci., Southwest Texas State Univ., San Marcos, TX, USA
pp. 586-590

Delay estimation of VLSI circuits from a high-level view (PDF)

M. Nemani , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 591-594

TETA: transistor-level engine for timing analysis (PDF)

F. Dartu , Strategic CAD Labs., Intel Corp., USA
pp. 595-598

Efficient state classification of finite state Markov chains (PDF)

A. Xie , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 605-610

Hybrid verification using saturated simulation (PDF)

A. Aziz , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 615-618

Fast state verification (PDF)

Dechang Sun , Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 619-624

Digital system simulation: methodologies and examples (PDF)

K. Olukotun , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 658-663

Hybrid techniques for fast functional simulation (PDF)

Yufeng Luo , Design Tools Group, Synopsys Inc., Mountain View, CA, USA
pp. 664-667

A reconfigurable logic machine for fast event-driven simulation (PDF)

J. Bauer , Quickturn Design Syst. Inc., San Jose, CA, USA
pp. 668-671

Parallel algorithms for power estimation (PDF)

V. Kim , Dept. of Electr. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
pp. 672-677

A power macromodeling technique based on power sensitivity (PDF)

Zhanping Chen , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 678-683

Maximum power estimation using the limiting distributions of extreme order statistics (PDF)

Qinru Qiu , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 684-689

Technology mapping for large complex PLDs (PDF)

J.H. Anderson , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 698-703

Delay-optimal technology mapping for FPGAs with heterogeneous LUTs (PDF)

J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 704-707

Compatible class encoding in hyper-function decomposition for FPGA synthesis (PDF)

J.-H.R. Jiang , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 712-717

A re-engineering approach to low power FPGA design using SPFD (PDF)

Jan-Min Hwang , Dept. of Comput. Sci., Tsinghua Univ., Beijing, China
pp. 722-725

System-chip test strategies (PDF)

Y. Zorian , LogicVision Inc., San Jose, CA, USA
pp. 752-757

Data security for Web-based CAD (PDF)

S. Hauck , Dept. of Electr. & Eng., Northwestern Univ., Evanston, IL, USA
pp. 788-793

Design of a SPDIF receiver using Protocol Compiler (PDF)

U. Holtmann , Synopsys Inc., Mountain View, CA, USA
pp. 794-799

System-level exploration with SpecSyn (PDF)

D.D. Gajski , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 812-817
Session 35: Panel
Session 15: Panel
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