The Community for Technology Leaders
Design Automation Conference (1998)
San Francisco, California
June 15, 1998 to June 19, 1998
ISBN: 0-89791-964-5
TABLE OF CONTENTS

Reviewers (PDF)

pp. xii
Executive Plenary Panel
Session 1: Interfaces for Design Reuse

Asynchronous Interface Specification, Analysis and Synthesis (Abstract)

Michael Kishinevsky , Intel Corporation, Hillsboro, OR, USA
Jordi Cortadella , Technical University of Catalonia, Barcelona, Spain
Alex Kondratyev , The University of Aizu, Aizu-Wakamatsu, Japan
pp. 2-7

Automatic Synthesis of Interfaces Between Incompatible Protocols (Abstract)

Roberto Passerone , University of California at Berkeley
James A. Rowson , Alta Group of Cadence, Sunnyvale, California
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
pp. 8-13

Automated Composition of Hardware Components (Abstract)

James Smith , Stanford University, CA
Giovanni De Micheli , Stanford University, CA
pp. 14-19
Session 2: Analog and Mixed-Signal Design Tools

Multilevel Integral Equation Methods for the Extraction of Substrate Coupling Parameters in Mixed-Signal IC's (Abstract)

Jacob White , Massachusetts Institute of Technology, Cambridge, MA
Mike Chou , Massachusetts Institute of Technology, Cambridge, MA
pp. 20-25

Phase Noise in Oscillators: A Unifying Theory and Numerical Methods for Characterisation (Abstract)

Amit Mehrotra , Bell Laboratories, Murray Hill, New Jersey
Alper Demir , Bell Laboratories, Murray Hill, New Jersey
Jaijeet Roychowdhury , Bell Laboratories, Murray Hill, New Jersey
pp. 26-31

Efficient Analog Test Methodology based on Adaptive Algorithms (Abstract)

Luigi Carro , Universidade Federal do Rio Grande do Sul
Marcelo Negreiros , Universidade Federal do Rio Grande do Sul
pp. 32-37

General AC Constraint Transformation for Analog ICs (Abstract)

U. Choudhury , Cadence Design Systems, San Jose, CA
E. Malavasi , Cadence Design Systems, San Jose, CA
B. G. Arsintescu , Delft University of Technology, The Netherlands
E. Charbon , Cadence Design Systems, San Jose, CA
W. H. Kao , Cadence Design Systems, San Jose, CA
pp. 38-43
Session 3: University Design Contest

Design Methodology used in a Single-Chip CMOS 900 MHz Spread-Spectrum Wireless Transceiver (Abstract)

Asad Abidi , UCLA Electrical Engineering, Los Angeles, CA
Ahmadreza Rofougaran , UCLA Electrical Engineering, Los Angeles, CA
Jacob Rael , UCLA Electrical Engineering, Los Angeles, CA
pp. 44-49

A Video Signal Processor for MIMD Multiprocessing (Abstract)

Peter Pirsch , Universit?t Hannover, Germany
Jan Otterstedt , Siemens Semiconductors, Munich, Germany
Dirk Niggemeyer , Universit?t Hannover, Germany
J? Hilgenstock , Universit?t Hannover, Germany
Klaus Herrmann , Universit?t Hannover, Germany
pp. 50-55

Realization of a Programmable Parallel DSP for High Performance Image Processing Applications (Abstract)

Mladen Berekovic , Universit?t Hannover, Germany
Jens Peter Wittenburg , Universit?t Hannover, Germany
Martin Ohmacht , Universit?t Hannover, Germany
Willm Hinrichs , Universit?t Hannover, Germany
Hanno Lieske , Universit?t Hannover, Germany
Johannes Kneip , Universit?t Hannover, Germany
Helge Kloos , Universit?t Hannover, Germany
Peter Pirsch , Universit?t Hannover, Germany
pp. 56-61

A Multiprocessor DSP system using PADDI-2 (Abstract)

Vason P. Srini , Data Flux Systems Inc., Berkeley, CA
Jan M. Rabaey , University of California, Berkeley
Roy A. Sutton , University of California, Berkeley
pp. 62-65

Design and Implementation of the NUMAchine Multiprocessor (Abstract)

M. Gusat , University of Toronto, Canada
K. Loveless , University of Toronto, Canada
R. Grindley , University of Toronto, Canada
A. Grbic , University of Toronto, Canada
Z. Vranesic , University of Toronto, Canada
S. Caranci , University of Toronto, Canada
M. Stumm , University of Toronto, Canada
S. Brown , University of Toronto, Canada
Z. Zilic , Lucent Technologies, Allentown, PA
S. Srbljic , University of Zagreb, Croatia
N. Manjikian , Queen's University at Kingston, Canada
G. Lemieux , University of Toronto, Canada
pp. 66-69
Session 4: Embedded System Design and Exploration

Design and Specification of Embedded Systems in Java Using Successive, Formal Refinement (Abstract)

James Shin Young , University of California, Berkeley
A. Richard Newton , University of California, Berkeley
Paul Hilfinger , University of California, Berkeley
Josh MacDonald , University of California, Berkeley
Michael Shilman , University of California, Berkeley
Abdallah Tabbara , University of California, Berkeley
pp. 70-75

Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer (Abstract)

Chantal Ykman-Couvreur , IMEC, Leuven, Belgium
Hugo De Man , IMEC, Leuven, Belgium
Francky Catthoor , IMEC, Leuven, Belgium
Miguel Miranda , IMEC, Leuven, Belgium
Diederik Verkest , IMEC, Leuven, Belgium
Paul Six , IMEC, Leuven, Belgium
Sven Wuytack , IMEC, Leuven, Belgium
Kris Croes , IMEC, Leuven, Belgium
Gjalt de Jong , Alcatel, Antwerp, Belgium
Julio Leao da Silva , IMEC, Leuven, Belgium
pp. 76-81

Design Space Exploration Algorithm For Heterogeneous Multi-processor Embedded System Design (Abstract)

Ireneusz Karkowski , Delft University of Technology, The Netherlands
Henk Corporaal , Delft University of Technology, The Netherlands
pp. 82-87

Modal Processes: Towards Enhanced Retargetability Through Control Composition of Distributed Embedded Systems (Abstract)

Pai Chou , University of Washington, Seattle
Gaetano Borriello , University of Washington, Seattle
pp. 88-93
Session 5: Taming Noise in Deep-Submicron Digital Designs

Design Methodologies for Noise in Digital Integrated Circuits (Abstract)

Kenneth L. Shepard , Columbia University, New York, NY
pp. 94-99
Session 6: Control and Data Driven High Level Synthesis

FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions (Abstract)

Niraj K. Jha , Department of Electrical Engineering, Princeton, NJ
Ganesh Lakshminarayana , Department of Electrical Engineering, Princeton, NJ
pp. 102-107

Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions (Abstract)

Anand Raghunathan , NEC USA, Princeton, NJ
Niraj K. Jha , Princeton University, Princeton, NJ
Ganesh Lakshminarayana , Princeton University, Princeton, NJ
pp. 108-113

The DT-Model: High-Level Synthesis using Data Transfers (Abstract)

Miriam Leeser , Northeastern University, Boston, MA
Shantanu Tarafdar , Northeastern University, Boston, MA
pp. 114

Rate Optimal VLSI Design from Data Flow Graph (Abstract)

Moonwook Oh , Seoul National University, Seoul, Korea
Soonhoi Ha , Seoul National University, Seoul, Korea
pp. 118
Session 7: Synthesis Flow in Deep Submicron Technologies

Planning for Performance (Abstract)

Ralph H. J. M. Otten , University of California at Berkeley, California; Delft University of Technology, The Netherlands and Synopsys Inc.
Robert K. Brayton , University of California at Berkeley, California
pp. 122-127

A DSM Design Flow: Putting Floorplanning, Technology-Mapping, and Gate-Placement Together (Abstract)

Jinan Lou , University of Southern California, Los Angeles, CA
Amir H. Salek , University of Southern California, Los Angeles, CA
Massoud Pedram , University of Southern California, Los Angeles, CA
pp. 128-134
Session 8: Environment for Collaborative Design

Framework Encapsulations: A New Approach to CAD Tool Interoperability (Abstract)

Stephen W. Director , University of Michigan, Ann Arbor
Peter R. Sutton , Queensland University of Technology, Australia
pp. 134-139

A Geographically Distributed Framework for Embedded System Design and Validation (Abstract)

Ken Hines , University of Washington, Seattle
Gaetano Borriello , University of Washington, Seattle
pp. 140-145

WELD-An Environment for Web-Based Electronic Design (Abstract)

A. Richard Newton , University of California at Berkeley
Mark D. Spiller , University of California at Berkeley
Francis L. Chan , University of California at Berkeley
pp. 146-151
Session 9: New Methods in Functional Verification

User Defined Coverage - A Tool Supported Methodology for Design Verification (Abstract)

Michael Orgad , IBM Research Lab in Haifa, Israel
Avi Ziv , IBM Research Lab in Haifa, Israel
Shmuel Ur , IBM Research Lab in Haifa, Israel
Raanan Grinwald , IBM Research Lab in Haifa, Israel
Eran Harel , IBM Research Lab in Haifa, Israel
pp. 158-163

Virtual Chip: Making Functional Models Work on Real Target Systems (Abstract)

Hoon Choi , KAIST, Taejon, Korea
Chong-Min Kyung , KAIST, Taejon, Korea
Seungjong Lee , KAIST, Taejon, Korea
Seungwang Lee , KAIST, Taejon, Korea
Namseung Kim , KAIST, Taejon, Korea
In-Cheolo Park , KAIST, Taejon, Korea
pp. 170-173
Session 10: Panel
Session 11: System-Level Power Optimization

Power Optimization of Variable Voltage Core-Based Systems (Abstract)

Gang Qu , University of California, Los Angeles
Inki Hong , University of California, Los Angeles
Mani B. Srivastava , University of California, Los Angeles
Darko Kirovski , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 176-181

Policy Optimization for Dynamic Power Management (Abstract)

L. Benini , Stanford University, CA
G. A. Paleologo , Stanford University, CA
G. De Micheli , Stanford University, CA
A. Bogliolo , Universit? di Bologna, Italy
pp. 182-187

A Framework for Estimation and Minimizing Energy Dissipation of Embedded HW/SW Systems (Abstract)

J? Henkel , NEC USA, Princeton, NJ
Yanbing Li , Princeton University, NJ
pp. 188-193
Session 12: Boolean Methods

Fast Exact Minimization of BDDs (Abstract)

Wolfgang G?nther , Albert-Ludwigs-University, Germany
Nicole Drechsler , Albert-Ludwigs-University, Germany
Rolf Drechsler , Albert-Ludwigs-University, Germany
pp. 200-205

Boolean Matching for Large Libraries (Abstract)

Reiner Kolla , Universit?t W?rzburg, Germany
Uwe Hinsberger , HighTec EDV-Systeme GmbH, Germany
pp. 206-211
Session 13: Extraction and Modeling for Interconnect

A Fast Hierarchical Algorithm for 3-D Capacitance Extraction (Abstract)

Tiejun Yu , Univ. of North Carolina, Charlotte, NC
Naveen Kakani , Univ. of North Texas, Denton, TX
Weiping Shi , Univ. of North Texas, Denton, TX
Jianguo Liu , Univ. of North Texas, Denton, TX
pp. 212-217

Boundary Element Method Macromodels for 2-D Hierachical Capacitance Extraction (Abstract)

Ronald A. Rohrer , Intersouth Partners, RTP, NC
E. Aykut Dengi , Motorola Inc., Austin, TX
pp. 218-223

Efficient Thee-Dimensional Extraction Based on Static and Full-Wave Layered Green's Functions (Abstract)

Jinsong Zhao , UC Santa Cruz, CA
David E. Long , Lucent Technologies, Murray Hill, NJ
Wayne W. M. Dai , UC Santa Cruz, CA
Sharad Kapur , Lucent Technologies, Murray Hill, NJ
pp. 224-229
Session 14: Processor Design and Simulation

Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor (Abstract)

Madhav P. Desai , Indian Institute of Technology, Mumbai, India
Nevine Nassif , Digital Equipment Corportation, Hudson MA
Dale H. Hall , Digital Equipment Corportation, Hudson MA
pp. 230-235

A Top-Down Design Environment for Developing Pipelined Datapaths (Abstract)

Robert McGraw , RAM Laboratories, Encinitas, CA
James H. Aylor , University of Virginia, Charlottesville
Robert H. Klenke , University of Virginia, Charlottesville
pp. 236-241

Validation of an Architectural Level Power Analysis Technique (Abstract)

Raminder S. Bajwa , Semiconductor Research Laboratory, Hitachi America Ltd.
Mary Jane Irwin , The Pennsylvania State University
Robert M. Owens , The Pennsylvania State University
Rita Yu Chen , The Pennsylvania State University
pp. 242-245

Design Methodology of a 200MHz Superscalar Microprocessor: SH-4 (Abstract)

Tsuyoshi Takahashi , Hitachi, Ltd., Japan
Toshihiro Hattori , Hitachi, Ltd., Japan
Mitsuho Seki , Hitachi, Ltd., Japan
Kunio Uchiyama , Hitachi, Ltd., Japan
Susumu Narita , Hitachi, Ltd., Japan
Ryuichi Satomura , Hitachi, Ltd., Japan
Yusuke Nitta , Hitachi, Ltd., Japan
pp. 246-249
Session 15: Panel
Session 16: Performance Modeling and Characterization for Embedded Systems

Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance (Abstract)

J.-H. Guo , University of Texas at Austin
M. Jacome , University of Texas at Austin
G. de Veciana , University of Texas at Austin
pp. 251-256

A Tool for Performance Estimation of Networked Embedded End-Systems (Abstract)

Asawaree Kalavade , Bell Labs, Holmdel, NJ
Pratyush Mogh? , Bell Labs, Holmdel, NJ
pp. 257-262

Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems (Abstract)

Ali Dasdan , University of Illinois, Urbana
Rajesh K. Gupta , University of California, Irvine
Dinesh Ramanathan , Synopsys, Inc., Mountain View, CA
pp. 263-268
Session 17: Advances in Placement and Partitioning

Generic Global Placement and Floorplanning (Abstract)

Hans Eisenmann , Technical University Munich, Germany
Frank M. Johannes , Technical University Munich, Germany
pp. 269-274

Congestion Driven Quadratic Placement (Abstract)

Phiroze N. Parakh , University Of Michigan, Ann Arbor
Karem A. Sakallah , University Of Michigan, Ann Arbor
Richard B. Brown , University Of Michigan, Ann Arbor
pp. 275-278

Potential-NRG: Placement with Incomplete Data (Abstract)

Prithviraj Banerjee , Northwestern University, Evanston, IL
Majid Sarrafzadeh , Northwestern University, Evanston, IL
Maogang Wang , Northwestern University, Evanston, IL
pp. 279-282

Performance-Driven Multi-FPGA Partitioning using Functional Clustering and Replication (Abstract)

Wen-Jong Fang , Tsing Hua University, Hsinchu, Taiwan
Allen C.-H. Wu , Tsing Hua University, Hsinchu, Taiwan
pp. 283-286

Multi-Pad Power/Ground Network Design for Uniform Distribution of Ground Bounce (Abstract)

Jaewon Oh , Sun Microsystems, Inc., Palo Alto, CA
Massoud Pedram , University of Southern California, Los Angeles, CA
pp. 287-290
Session 18: Parasitic Device Extraction and Interconnect Modeling

Layout Extraction and Verification Methodology CMOS I/O Circuits (Abstract)

Sung-Mo Kang , Univ. of Illinois at Urbana-Champaign
Tong Li , Univ. of Illinois at Urbana-Champaign
pp. 291-296

A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects (Abstract)

Nuno Marques , INESC/Cadence European Laboratories, Lisboa, Portugal
Mattan Kamon , Massachusetts Institute of Technology, Cambridge, MA
Jacob White , Massachusetts Institute of Technology, Cambridge, MA
L. Miguel Silveira , INESC/Cadence European Laboratories, Lisboa, Portugal
pp. 297-302
Session 19: Design Optimization for DSP

A Methodology for Guided Behavioral-Level Optimization (Abstract)

Lisa Guerra , Rockwell Semiconductor Systems, Newport Beach, CA
Miodrag Potkonjak , University of California, Los Angeles, CA
Jan Rabaey , University of California, Berkeley, CA
pp. 309-314

A Programming Environment for the Design of Complex High Speed ASICs (Abstract)

Marc Engels , IMEC vzw, Leuven
Luc Rijnders , IMEC vzw, Leuven
Ivo Bolsens , IMEC vzw, Leuven
Serge Vernalde , IMEC vzw, Leuven
Patrick Schaumont , IMEC vzw, Leuven
pp. 315-320

Media Architecture: General Purpose vs. Multiple Application-Specific Programmable Processor (Abstract)

William H. Mangione-Smith , Electrical Engineering Department, UCLA
Chunho Lee , Computer Science Department, UCLA
Johnson Kin , Electrical Engineering Department, UCLA
Miodrag Potkonjak , Computer Science Department, UCLA
pp. 321-326
Session 20: Panel
Session 21: Bridging the Gap Between Simulation and Formal Verification
Session 22: Logic Optimization

Optimal FPGA Mapping and Retiming with Efficient Initial State Computation (Abstract)

Jason Cong , University of California, Los Angeles, CA
Chang Wu , University of California, Los Angeles, CA
pp. 330-335

M32: A Constructive Multilevel Logic Synthesis System (Abstract)

Victor N. Kravets , University of Michigan, Ann Arbor
Karem A. Sakallah , University of Michigan, Ann Arbor
pp. 336-341

Efficient Boolean Division and Substitution (Abstract)

David Ihsin Cheng , Ultima Interconnect Tech., Sunnyvale, CA
Shih-Chieh Chang , Nationa Chung Cheng University, Taiwan
pp. 342-347

Delay-Optimal Technology Mapping by DAG Covering (Abstract)

Robert K. Brayton , University of California, Berkeley
Yuji Kukimoto , University of California, Berkeley
Prashant Sawkar , Intel Corporation, Hillsboro, OR
pp. 348-351

A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries (Abstract)

David S. Kung , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 352-355
Session 23: Routing for Performance and Crosstalk

Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs (Abstract)

Patrick H. Madden , UCLA Computer Science Department, Los Angeles, California
Jason Cong , UCLA Computer Science Department, Los Angeles, California
pp. 356-361

Buffer Insertion for Noise and Delay Optimization (Abstract)

Stephen T. Quay , IBM Microelectronics Division, Austin, TX
Anirudh Devgan , IBM Austin Research Laboratory, Austin, TX
Charles J. Alpert , IBM Austin Research Laboratory, Austin, TX
pp. 362-367

Table-Lookup Methods for Improved Performance-Driven Touting (Abstract)

Premal Buch , Magma Design Automation, Palo Alto, CA
John Lillis , Magma Design Automation, Palo Alto, CA
pp. 368-373

Global Routing with Crosstalk Constraints (Abstract)

D. F. Wong , University of Texas, Austin, TX
Hai Zhou , University of Texas, Austin, TX
pp. 374-377

Timing and Crosstalk Driven Area Routing (Abstract)

Louis Scheffer , Cadence Design Systems, Inc., San Jose, CA
Hsiao-Ping Tseng , University of Washington, Seattle
Carl Sechen , University of Washington, Seattle
pp. 378-381
Session 24: Practical Optimization Methodologies for High Performance Design

Process Multi-Circuit Optimization (Abstract)

Arun Lokanathan , University of Notre Dame, IN
Jay Brockman , University of Notre Dame, IN
pp. 382-387

Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization (Abstract)

Joe Norton , Advanced System Technologies Lab., Motorola, Austin, TX
David Blaauw , Advanced System Technologies Lab., Motorola, Austin, TX
Rajendran Panda , Advanced System Technologies Lab., Motorola, Austin, TX
Abhijit Dharchoudhury , Advanced System Technologies Lab., Motorola, Austin, TX
Tim Edwards , Advanced System Technologies Lab., Motorola, Austin, TX
pp. 388-391

A Practical Repeater Insertion Method in High Speed VLSI Vircuits (Abstract)

Chaim Amir , Sun Microsystems, Inc., Palo Alto, CA
Julian Culetu , Sun Microsystems, Inc., Palo Alto, CA
John MacDonald , Sun Microsystems, Inc., Palo Alto, CA
pp. 392-395

A Statistical Performance Simulation Methodology for VLSI Circuits (Abstract)

Michael Orshansky , University of California at Berkeley
James C. Chen , University of California at Berkeley
Chenming Hu , University of California at Berkeley
pp. 402-407
Session 25: RF IC Design Methodology

RF IC Design Challenges (Abstract)

Behzad Razavi , University of California, Los Angeles
pp. 408-413

Tools and Methodology for RF IC Design (Abstract)

Al Dunlop , Bell Laboratories, Murray Hill, NJ
Alper Demir , Bell Laboratories, Murray Hill, NJ
David Long , Bell Laboratories, Murray Hill, NJ
Sharad Kapur , Bell Laboratories, Murray Hill, NJ
Peter Feldmann , Bell Laboratories, Murray Hill, NJ
Robert Melville , Bell Laboratories, Murray Hill, NJ
Jaijeet Roychowdhury , Bell Laboratories, Murray Hill, NJ
pp. 414-420
Session 26: Theory and Practice in High Level Synthesis

Efficient Coloring of a Large Spectrum of Graphs (Abstract)

Miodrag Potkonjak , University of California, Los Angeles
Darko Kirovski , University of California, Los Angeles
pp. 427-432

Arithmetic Optimization using Carry-Save-Adders (Abstract)

Taewhan Kim , Synopsys Inc., Mountain View, CA
William Jao , Aimfast Corp., Sunnyvale, CA
Steve Tjiang , Synopsys Inc., Mountain View, CA
pp. 433-438
Session 27: BDD Approximation Techniques

Approximation and Decomposition of Binary Decision Diagrams (Abstract)

Kavita Ravi , University of Colorado
Thomas R. Shiple , Synopsys
Fabio Somenzi , University of Colorado
Kenneth L. McMillan , Cadence Design Systems
pp. 445-450

Approximate Reachability with BDDs using Overlapping Projections (Abstract)

Alan J. Hu , University of British Columbia, Vancouver, Canada
Mark A. Horowitz , Stanford University, CA
Shankar G. Govindaraju , Stanford University, CA
David L. Dill , Stanford University, CA
pp. 451-456

Incremental CTL Model Checking using BDD Subsetting (Abstract)

Gary D. Hachtel , University of Colorado, Boulder
Abelardo Pardo , Mentor Graphics Corporation, Billerica, MA
pp. 457-462
Session 28: Interconnect Modeling and Timing Simulation

PRIMO: Probability Interpretation of Moments for Delay Calculation (Abstract)

Rony Kay , Carnegie Mellon University
Lawrence Pileggi , Carnegie Mellon University
pp. 463-468

ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models (Abstract)

Andrzej J. Strojwas , Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Ying Liu , Carnegie Mellon University, Pittsburgh, PA
pp. 469-472

Extending Moment Computation to 2-Port Circuit Representations (Abstract)

Chung-Kuan Cheng , University of California, San Diego
Fang-Jou Liu , University of California, San Diego
pp. 473-476

Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation (Abstract)

Tuyan V. Nguyen , IBM Austin Research Laboratory, Austin, TX
Anirudh Devgan , IBM Austin Research Laboratory, Austin, TX
Ognen J. Nastov , MIT, Cambridge, MA
pp. 477-482
Session 29: Low Power Design Using Multiple Thresholds and Supplies

Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques (Abstract)

Tadahiro Kuroda , Toshiba Corporation, Japan
Mototsugu Hamada , Toshiba Corporation, Japan
Toshihiro Terazawa , Toshiba Corporation, Japan
Mutsunori Igarashi , Toshiba Corporation, Japan
Kimiyoshi Usami , Toshiba Corporation, Japan
Masahiro Kanazawa , Toshiba Corporation, Japan
Hideho Arakida , Toshiba Corporation, Japan
Takashi Ishikawa , Toshiba Corporation, Japan
Masafumi Takahashi , Toshiba Corporation, Japan
pp. 483-488

Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits (Abstract)

Vivek De , Intel Corp., Hillsboro, OR
Zhanping Chen , Purdue University, W. Lafayette, IN
Liqiong Wei , Purdue University, W. Lafayette, IN
Kaushik Roy , Purdue University, W. Lafayette, IN
Mark Johnson , Purdue University, W. Lafayette, IN
pp. 489-494

MTCMOS Hierarchical Sizing based on Mutual Exclusive Discharge Patterns (Abstract)

Siva Narendra , Massachusetts Institute of Technology
Anantha Chandrakasan , Massachusetts Institute of Technology
James Kao , Massachusetts Institute of Technology
pp. 495-500
Session 30: Panel
Session 31: Software Synthesis and Retargetable Compilation

Software Synthesis of Process-based Concurrent Programs (Abstract)

Bill Lin , University of California, San Diego
pp. 502-505

Don't Care-Based BDD Minimization for Embedded Software (Abstract)

Youpyo Hong , University of Southern California, Los Angeles, CA
Peter A. Beerel , University of Southern California, Los Angeles, CA
Ellen M. Sentovich , Cadence Berkeley Laboratories, Berkeley, CA
Luciano Lavagno , Cadence Berkeley Laboratories, Berkeley, CA
pp. 506-509

Code Compression for Embedded Systems (Abstract)

Haris Lekatsas , Princeton University
Wayne Wolf , Princeton University
pp. 516-521
Session 32: Formal Methods in Functional Verification

A Decision Procedure for Bit-Vector Arithmetic (Abstract)

Jeremy R. Levitt , 0-in Design Automation
David L. Dill , Stanford University, CA
Clark W. Barrett , Stanford University, CA
pp. 522-527

Functional Vector Generation for HDL Models using Linear Programming and 3-Satisfiability (Abstract)

Srinivas Devadas , MIT, Cambridge
Kurt Keutzer , University of California, Berkeley
Farzan Fallah , MIT, Cambridge
pp. 528-533

Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment (Abstract)

Carl-Johan H. Seger , Intel Corporation, Hillsboro, OR
Robert B. Jones , Intel Corporation, Hillsboro, OR
Mark D. Aagaard , Intel Corporation, Hillsboro, OR
pp. 538-541
Session 33: Core Test and BIST

A Fast and Low Cost Testing Technique for Core-Based System-on-Chip (Abstract)

Indradeep Ghosh , Princeton University, NJ
Sujit Dey , University of California, San Diego
Niraj K. Jha , Princeton University, NJ
pp. 542-547

Introducing Redundant Computations in a Behavior for Reducing BIST Resources (Abstract)

Sandeep K. Gupta , University of Southern California, Los Angeles
Melvin A. Breuer , University of Southern California, Los Angeles
Ishwar Parulkar , Sun Microsystems, Sunnyvale, CA
pp. 548-553

A BIST Scheme for RTL Controller-Data Paths based on Symbolic Testability Analysis (Abstract)

Indradeep Ghosh , Princeton University, NJ
Niraj K. Jha , Princeton University, NJ
Sudipta Bhawmik , Lucent Technologies, Princeton, NJ
pp. 554-559
Session 34: Interconnect Analysis and Reliability in Deep Sub-Micron

Figures of Merit to Characterize the Importance of On-Chip Inductance (Abstract)

Yehea I. Ismail , University of Rochester, New York
Jose L. Neves , IBM Microelectronics, East Fishkill, New York
Eby G. Friedman , University of Rochester, New York
pp. 560-565

Layout Techniques for Minimizing On-Chip Interconnect Self Inductance (Abstract)

Jacob White , Mass. Institute of Tech., Cambridge, MA
Steve Majors , Motorola Inc., Austin, TX
Yehia Massoud , Mass. Institute of Tech., Cambridge, MA
Tareq Bustami , Motorola Inc., Austin, TX
pp. 566-571

A Practical Approach to Static Signal Electromigration Analysis (Abstract)

Haldun Haznedar , Texas Instruments, Inc., Houston, TX
NS Nagaraj , Texas Instruments, Inc., Dallas, TX
Frank Cano , Texas Instruments, Inc., Houston, TX
Duane Young , Texas Instruments, Inc., Houston, TX
pp. 572-577
Session 35: Panel
Session 36: Timing Analysis

Hierarchical Functional Timing Analysis (Abstract)

Yuji Kukimoto , University of California, Berkeley
Robert K. Brayton , University of California, Berkeley
pp. 580-585

Making Complex Timing Relationships Readable: Presburger Formula Simplicication using Don't Cares (Abstract)

Tod Amon , Southwest Texas State University, San Macros, TX
Jiwen Liu , Southwest Texas State University, San Macros, TX
Gaetano Borriello , University of Washington, Seattle
pp. 586-590

Delay Estimation VLSI Circuits from a High-Level View (Abstract)

Farid N. Najm , University of Illinois at Urbana-Champaign
Mahadevamurty Nemani , University of Illinois at Urbana-Champaign
pp. 591-594

TETA: Transistor-Level Engine for Timing Analysis (Abstract)

Florentin Dartu , Intel Corporation
Lawrence T. Pileggi , Carnegie Mellon University
pp. 595-598
Session 37: New Techniques in State Space Explorations

Validation with Guided Search of the State Space (Abstract)

David L. Dill , Stanford University, CA
C. Han Yang , Stanford University, CA
pp. 599-604

Efficient State Classification of Finite State Markov Chains (Abstract)

Peter A. Beerel , University of Southern California, Los Angeles
Aiguo Xie , University of Southern California, Los Angeles
pp. 605-610

An Implicit Algorithm for Finding Steady States and Its Application to FSM Verification (Abstract)

Gagan Hasteer , Ambit Design Systems
Prithviraj Banerjee , Northwestern University
Anmol Mathur , Silicon Graphics Inc.
pp. 611-614

Hybrid Verification using Saturated Simulation (Abstract)

Jim Kukula , Synopsys, Inc.
Tom Shiple , Synopsys, Inc.
Adnan Aziz , Univ. of Texas at Austin
pp. 615-618
Session 38: Advanced ATPG Techniques

Fast State Verification (Abstract)

Wanli Jiang , University of Minnesota, Minneapolis
Dechang Sun , University of Minnesota, Minneapolis
Bapiraju Vinnakota , University of Minnesota, Minneapolis
pp. 619-624

A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance (Abstract)

Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
Mark Kassab , Mentor Graphics Corporation, Wilsonville, OR
Aiman El-Maleh , Mentor Graphics Corporation, Wilsonville, OR
pp. 625-631

Fault-Simulation based Design Error Diagnosis for Sequential Circuits (Abstract)

Kuang-Chien Chen , Verplex Systems Inc., Santa Clara, CA
Shi-Yu Huang , National Semiconductor Corp., Santa Clara, CA
Kwang-Ting Cheng , Univ. of California, Santa Barbara
Juin-Yeu Joseph Lu , National Semiconductor Corp., Santa Clara, CA
pp. 632-637
Session 39: Practical Experiences of Functional Verification for Complex ICs

Functional Verification of a Multiple-Issue, Out-of-Order, Superscalar Alpha Processor - The DEC Alpha 21264 Microprocessor (Abstract)

Scott Taylor , Digital Equipment Corporation
Nathan Dohm , Digital Equipment Corporation
Michael Quinn , Digital Equipment Corporation
Carl Ramey , Digital Equipment Corporation
Scot Hildebrandt , Digital Equipment Corporation
James Huggins , Digital Equipment Corporation
Darren Brown , Digital Equipment Corporation
pp. 638-643

Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data (Abstract)

Avi Ziv , IBM Research Lab in Haifa, Israel
Yossi Malka , IBM Research Lab in Haifa, Israel
pp. 644-649

Functional Verification of Large ASICs (Abstract)

Allan Silburt , Nortel, Canada
Thane Brown , Nortel, Canada
Adrian Evans , Nortel, Canada
Gary Vrckovnik , Nortel, Canada
Ying Liu , Nortel, Canada
Tung Ho , Nortel, Canada
Mario Dufresne , Nortel, Canada
Geoffrey Hall , Nortel, Canada
pp. 650-655
Session 40: Panel
Session 41: Fast Functional Simulation

Digital System Simulation: Methodologies and Examples (Abstract)

David Ofelt , Stanford University, CA
Mark Heinrich , Stanford University, CA
Kunle Olukotun , Stanford University, CA
pp. 658-663

Hybrid Techniques for Fast Functional Simulation (Abstract)

Adnan Aziz , University of Texas-Austin, TX
Yufeng Luo , Synopsys, Inc., Mountain View, CA
Tjahjadi Wongsonegoro , University of Texas-Austin, TX
pp. 664-667

A Reconfigurable Logic Machine for Fast Event-Driven Simulation (Abstract)

Paul Vyedin , Quickturn Design Systems, Inc., San Jose, CA
Ian Kaplan , Quickturn Design Systems, Inc., San Jose, CA
Michael Bershteyn , Quickturn Design Systems, Inc., San Jose, CA
Jerry Bauer , Quickturn Design Systems, Inc., San Jose, CA
pp. 668-671
Session 42: Power Estimation and Modeling

Parallel Algorithms for Power Estimation (Abstract)

Victor Kim , Northwestern University, Evanston, Illinois
Prithviraj Banerjee , Northwestern University, Evanston, Illinois
pp. 672-677

A Power Macromodeling Technique based on Power Sensitivity (Abstract)

Zhanping Chen , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 678-683

Maximum Power Estimation using the Limiting Distributions of Extreme Order Statistics (Abstract)

Qing Wu , University of Southern California, Los Angeles, CA
Qinru Qiu , University of Southern California, Los Angeles, CA
Massoud Pedram , University of Southern California, Los Angeles, CA
pp. 684-689

An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits (Abstract)

Eun Sei Park , Hanyang University, Ansan, Korea
Byunggyu Kwak , Samsung Data Systems, Seoul, Korea
pp. 690-693

Using Complementation and Resequencing to Minimize Transitions (Abstract)

Arlindo Oliveira , Cadence European Labs./IST-INESC
Masahiro Fujita , Fujitsu Laboratories of America, Inc.
Rajeev Murgai , Fujitsu Laboratories of America, Inc.
pp. 694-697
Session 43: Technology Mapping for Programmable Logic

Technology Mapping for Large Complex PLDs (Abstract)

Stephen Dean Brown , University of Toronto, Canada
Jason Helge Anderson , University of Toronto, Canada
pp. 698-703

Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs (Abstract)

Songjie Xu , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 704-707

Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs (Abstract)

D. F. Wong , The University of Texas at Austin
Madhukar R. Korupolu , The University of Texas at Austin
K. K. Lee , The University of Texas at Austin
pp. 708

Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis (Abstract)

Jing-Yang Jou , National Chiao Tung University
Jie-Hong R. Jiang , National Chiao Tung University
Juinn-Dar Huang , National Chiao Tung University
pp. 712

In-Place Power Optimization for LUT-Based FPGAs (Abstract)

Enrico Macii , Politecnico di Torino, Italy
Luca Benini , Universit? di Bologna, Italy
Balakrishna Kumthekar , University of Colorado, Boulder
Fabio Somenzi , University of Colorado, Boulder
pp. 718

A Re-engineering Approach to Low Power FPGA Design Using SPFD (Abstract)

Jan-Min Hwang , Tsing Hua University, Taiwan
Feng-Yi Chiang , Tsing Hua University, Taiwan
TingTing Hwang , Tsing Hua University, Taiwan
pp. 722
Session 44: Power Dissipation and Distribution in High Performance Processors

Power Considerations in the Design of the Alpha 21264 Microprocessor (Abstract)

Michael K. Gowan , Digital Equipment Corporation, Hudson, Massachusetts
Larry L. Biro , Digital Equipment Corporation, Hudson, Massachusetts
Daniel B. Jackson , Digital Equipment Corporation, Hudson, Massachusetts
pp. 726-731

Reducing Power in High-Performance Microprocessors (Abstract)

Franklin Baez , Intel Corporation, Santa Clara, CA
Suresh Rajgopal , Intel Corporation, Santa Clara, CA
Rakesh Patel , Intel Corporation, Santa Clara, CA
Gaurav Mehta , Intel Corporation, Santa Clara, CA
Vivek Tiwari , Intel Corporation, Santa Clara, CA
Deo Singh , Intel Corporation, Santa Clara, CA
pp. 732-737

Design and Analysis of Power Distribution Networks in PowerPC Microprocessors (Abstract)

David Blaauw , Advanced System Technologies Lab, Motorola, Austin, TX
Rajendran Panda , Advanced System Technologies Lab, Motorola, Austin, TX
David Bearden , Somerset Design Center, Austin, TX
Bogdan Tutuianu , Somerset Design Center, Austin, TX
Ravi Vaidyanathan , Advanced System Technologies Lab, Motorola, Austin, TX
Abhijit Dharchoudhury , Advanced System Technologies Lab, Motorola, Austin, TX
pp. 738-743

Full-Chip Verification Methods for DSM Power Distribution Systems (Abstract)

Syed Zakir Hussain , Simplex Solutions, Inc.
David Overhauser , Simplex Solutions, Inc.
Steffen Rochel , Simplex Solutions, Inc.
Gregory Steele , Simplex Solutions, Inc.
pp. 744-749
Session 45: Challenge in the Test on System-On-A-Chip Era

System-Chip Test Strategies (Abstract)

Yervant Zorian , LogicVision, Inc., San Jose, California
pp. 752-757
Session 46: Controller Decomposition for Power and Area Minimization

Finite State Machine Decomposition for Low Power (Abstract)

Jos? C. Monteiro , IST-INESC, Portugal
Arlindo L. Oliveira , Cadence European Labs/IST-INESC, Portugal
pp. 758-763

Computational Kernels and Their Application to Sequential Power Optimization (Abstract)

L. Benini , Stanford University, CA
A. Lioy , Politecnico di Torino, Italy
E. Macii , Politecnico di Torino, Italy
G. Odasso , Politecnico di Torino, Italy
G. De Micheli , Stanford University, CA
M. Poncino , Politecnico di Torino, Italy
pp. 764-769
Session 47: IP Protection Technologies

Watermarking Techniques for Intellectual Property Protection (Abstract)

H. Wang , UCLA Computer Science Dept., Los Angeles, CA
I. L. Markov , UCLA Computer Science Dept., Los Angeles, CA
P. Tucker , UCSD Computer Science & Engineering Dept., La Jolla, CA
S. Mantik , UCLA Computer Science Dept., Los Angeles, CA
W. H. Mangione-Smith , UCLA Electrical Engineering Dept., Los Angeles, CA
J. Lach , UCLA Electrical Engineering Dept., Los Angeles, CA
A. B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
G. Wolfe , UCLA Computer Science Dept., Los Angeles, CA
M. Potkonjak , UCLA Computer Science Dept., Los Angeles, CA
pp. 776-781

Robust IP Watermarking Methodologies for Physical Design (Abstract)

Igor L. Markov , UCLA Computer Science Dept., Los Angeles, CA
Paul Tucker , UCSD Computer Science & Engineering Dept., La Jolla, CA
Huijuan Wang , UCLA Computer Science Dept., Los Angeles, CA
Gregory Wolfe , UCLA Computer Science Dept., Los Angeles, CA
Miodrag Potkonjak , UCLA Computer Science Dept., Los Angeles, CA
Stefanus Mantik , UCLA Computer Science Dept., Los Angeles, CA
Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
pp. 782-787

Data Security for Web-Based CAD (Abstract)

Stephen Knol , Northwestern University, Evanston, IL
Scott Hauck , Northwestern University, Evanston, IL
pp. 788-793
Session 48: Case Studies of New Design Methods

Design of a SPDIF Receiver Using Protocol Compiler (Abstract)

Peter Blinzer , Technical University of Braunschweig
Ulrich Holtmann , Synopsys, Inc., Mountain View, CA
pp. 794-799

MetaCore: An Application Specific DSP Development System (Abstract)

Seung-Hoon Hwang , KAIST, Taejon, Korea
Jong-Sun Kim , KAIST, Taejon, Korea
Jin-Hyuk Yang , KAIST, Taejon, Korea
Jang-Ho Cho , KAIST, Taejon, Korea
Sang-Jun Nam , KAIST, Taejon, Korea
Jong-Yeol Lee , KAIST, Taejon, Korea
Chang-Ho Ryu , KAIST, Taejon, Korea
Chong-Min Kyung , KAIST, Taejon, Korea
Jun-Sung Kim , KAIST, Taejon, Korea
Hyun-Dhong Yoon , KAIST, Taejon, Korea
Young-Su Kwon , KAIST, Taejon, Korea
Kwang-11 Park , KAIST, Taejon, Korea
In-Cheol Park , KAIST, Taejon, Korea
Kyu-Ho Park , KAIST, Taejon, Korea
In-Hyung Kim , KAIST, Taejon, Korea
Sung-won Seo , KAIST, Taejon, Korea
Jae-Yeol Kim , KAIST, Taejon, Korea
Kun-Moo Lee , KAIST, Taejon, Korea
Dae-Hyun Lee , KAIST, Taejon, Korea
Chan-Soo Hwang , KAIST, Taejon, Korea
Yong-Hoon Lee , KAIST, Taejon, Korea
Byoung-Woon Kim , KAIST, Taejon, Korea
pp. 800-803

A Case Study in Embedded System Design: An Engine Control Unit (Abstract)

Attila Jurecska , Magneti Marelli, Venaria Reale, Italy
Luciano Lavagno , Politecnico di Torino - Cadence Eurpoeans Labs, Italy
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
Claudio Passeronge , Politecnico di Torino - Cadence Eurpoeans Labs, Italy
Tullio Cuatto , Politecnico di Torino, Italy
Claudio Sanso? , Politecnico di Torino, Italy
Antonino Damiano , Magneti Marelli, Venaria Reale, Italy
pp. 804-807

System-Level Exploration with SpecSyn (Abstract)

Frank Vahid , University of California, Riverside
Sanjiv Narayan , Ambit Design Systems, Santa Clara
Jie Gong , Qualcomm Inc, San Diego, CA
Daniel D. Gajski , University of California, Irvine
pp. 812-817

Author Index (PDF)

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