The Community for Technology Leaders
Design Automation Conference (1997)
Anaheim, CA
June 9, 1997 to June 13, 1997
ISBN: 0-89791-920-3
TABLE OF CONTENTS

Reviewers (PDF)

pp. xii
Session 1: Sequential Synthesis

An Improved Algorithm for Minimum-Area Retiming (Abstract)

Naresh Maheshwari , Iowa State University, Ames
Sachin S. Sapatnekar , Iowa State University, Ames
pp. 2

Efficient Latch Optimization Using Exclusive Sets (Abstract)

Ellen M. Sentovich , Cadence Berkeley Labs
Horia Toma , CMA - Ecole des Mines de Paris
G?rard Berry , CMA - Ecole des Mines de Paris
pp. 8

Sequence Compaction for Probabilistic Analysis of Finite-State Machines (Abstract)

Massoud Pedram , University of Southern California, Los Angeles
Radu Marculescu , University of Southern California, Los Angeles
Diana Marculescu , University of Southern California, Los Angeles
pp. 12

Synthesis of Speed-Independent Circuits from STG-unfolding Segment (Abstract)

E. Pastor , Universitat Polit?cnica de Catalunya, Spain
A. Semenov , University of Newcastle, England
J. Cortadella , Universitat Polit?cnica de Catalunya, Spain
A. Yakovlev , University of Newcastle, England
M. A. Pe? , Universitat Polit?cnica de Catalunya, Spain
pp. 16

Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control (Abstract)

Luca Benini , Stanford University, CA
Enrico Macii , Politecnico di Torino, Italy
Massimo Poncino , Politecnico di Torino, Italy
pp. 22
Session 2: Interconnect Modeling

Zeros and Passivity of Arnoldi-Reduced-Order Models for Interconnect Networks (Abstract)

David D. Ling , IBM T. J. Watson Research Center, Yorktown Heights, NY
I. M. Elfadel , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 28

Lumped Interconnect Models Via Gaussian Quadrature (Abstract)

Jacob K. White , Massachusetts Institute of Technology, Cambridge, MA
Ketih Nabors , Cadence Design Systems, San Jose, CA
Kenneth S. Kundert , Cadence Design Systems, San Jose, CA
Hung-Wen Chang , Cadence Design Systems, San Jose, CA
Tze-Ting Fang , Cadence Design Systems, San Jose, CA
pp. 40

Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling (Abstract)

Florentin Dartu , Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
pp. 46
Session 3: Novel Techniques for Software Scheduling

Schedule Validation for Embedded Reactive Real-Time Systems (Abstract)

Alberto Sangiovanni-Vincentelli , University of California at Berkeley
Felice Balarin , Cadence Berkeley Laboratories
pp. 52

Incorporating Imprecise Computation into System-Level Design of Application-Specific Heterogeneous Multiprocessors (Abstract)

Yosef G. Tirat-Gefen , Mentor Graphics Corp., Wilsonville, OR
Alice C. Parker , Univ. of Southern California, Los Angeles
Diogenes C. Silva , Univ. of Southern California, Los Angeles
pp. 58

Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets (Abstract)

J. A. Peperstraete , Katholieke Universiteit Leuven, Belgium
Rudy Lauwereins , Katholieke Universiteit Leuven, Belgium
Marleen Ad? , Katholieke Universiteit Leuven, Belgium
pp. 64
Session 4: Embedded Tutorial

Tools and Methodologies for Low Power Design (Abstract)

Jerry Frenkil , Sente, Inc., Chelmsford, MA
pp. 76
Panel
Session 5: Simulation Techniques for Microprocessors

A C-Based RTL Design Verification Methodology for Complex Microprocessor (Abstract)

Hoon Choi , KAIST, Taejon, Korea
In-Cheol Park , KAIST, Taejon, Korea
Joon-Seo Yim , KAIST, Taejon, Korea
Woo-Seung Yang , KAIST, Taejon, Korea
Chang-Jae Park , KAIST, Taejon, Korea
Chong-Min Kyung , KAIST, Taejon, Korea
Yoon-Ho Hwang , KAIST, Taejon, Korea
Hun-Seung Oh , KAIST, Taejon, Korea
pp. 83

Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors (Abstract)

J?rg Walter , IBM Deutschland Entwicklung GmbH, Germany
Jens Leenstra , IBM Deutschland Entwicklung GmbH, Germany
Gerhard D?ttling , IBM Deutschland Entwicklung GmbH, Germany
Bernd Leppla , IBM Deutschland Entwicklung GmbH, Germany
Bruce Wile , IBM Corp., NY
Kevin Kark , IBM Corp., NY
Hans-J?rgen M?nster , IBM Deutschland Entwicklung GmbH, Germany
pp. 89

Efficient Testing of Clock Regenerator Circuits in Scan Designs (Abstract)

Robert Molyneaux , IBM Corporation, Austin, TX
Charles Njinda , Advanced Micro Devices, Sunnyvale, CA
Robert Bailey , Motorola Inc., Austin, TX
Rajesh Raina , Motorola Inc., Austin, TX
Charlie Beh , IBM Corporation, Austin, TX
pp. 95

A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications (Abstract)

Allen C.-H. Wu , Tsing Hua University, Taiwan
Wen-Jong Fang , Tsing Hua University, Taiwan
Ti-Yen Yen , Quickturn Design Systems, Inc., Mountain View, CA
pp. 101
Session 6: Combinational Logic Synthesis

A Graph-Based Synthesis Algorithm for AND/XOR Networks (Abstract)

Yibin Ye , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 107

Optimizing Designs Containing Black Boxes (Abstract)

Adnan Aziz , The University of Texas, Austin
Vigyan Singhal , Cadence Berkeley Labs, Berkeley, CA
Khurram Sajid , The University of Texas, Austin
Tai-Hung Liu , The University of Texas, Austin
pp. 113

Solving Covering Problems Using LPR-Based Lower Bounds (Abstract)

Stan Liao , Advanced Technology Group, Synopsys, Inc.
Srinivas Devadas , Department of EECS, MIT
pp. 117

Exact Coloring of Real-Life Graphs is Easy (Abstract)

Olivier Coudert , Synopsys, Inc., Mountain View, CA
pp. 121
Session 7: Interconnect Parasitic Extraction

Hierarchical 2-D Field Solution for Capacitance Extraction for VLSI Interconnect Modeling (Abstract)

E. Aykut Dengi , Motorola Inc., Austin, TX
Ronald A. Rohrer , Carnegie Mellon University, Pittsburgh, PA
pp. 127

Bounds for BEM Capacitance Extraction (Abstract)

Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Michael W. Beattie , Carnegie Mellon University, Pittsburgh, PA
pp. 133

SPIE: Sparse Partial Inductance Extraction (Abstract)

Lawrence Pileggi , Carnegie Mellon University, Pittsburgh, PA
Zhijiang He , Carnegie Mellon University, Pittsburgh, PA
Mustafa Celik , Carnegie Mellon University, Pittsburgh, PA
pp. 137

A Fast Method of Moments Solver for efficient parameter extraction of MCMs (Abstract)

Sharad Kapur , Bell Labs Lucent Technologies, Murray Hill, NJ
Jinsong Zhao , UC Santa Cruz, CA
pp. 141
Session 8: Advances in Timing Analysis for Embedded Software

Static Timing Analysis of Embedded Software (Abstract)

Margaret Martonosi , Princeton University
Sharad Malik , Princeton University
Yau-Tsun Steven Li , Princeton University
pp. 147

A Task-Level Hierarchical Memory Model for System Synthesis of Multiprocessors (Abstract)

Wayne Wolf , Princeton University, NJ
Yanbing Li , Princeton University, NJ
pp. 153

Predicting Timing Behavior in Architectural Design Exploration of Real-Time Embedded Systems (Abstract)

Xiaobo (Sharon) Hu , University of Notre Dame, IN
Rajeshkumar S. Sambandam , Level One Communications, Inc., Sacramento, CA
pp. 157
Session 9: Applications of Formal Verification

Formal Verification of a Superscalar Execution Unit (Abstract)

Kyle L. Nelson , IBM Corporation, Rochester, MN
Alok Jain , Carnegie Mellon University, Pittsburgh, PA
Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
pp. 161

Formal Verification of Content Addressable Memories using Symbolic Trajectory Evaluation (Abstract)

Randal E. Bryant , Science, Carnegie Mellon University Pittsburgh, PA
Magdy S. Abadir , Motorola Inc., Austin, TX
Manish Pandey , Science, Carnegie Mellon University Pittsburgh, PA
Richard Raimi , Motorola Inc., Austin, TX
pp. 167

Formal Verification of FIRE: A Case Study (Abstract)

Carl Pixley , Motorola Inc., Austin, TX
Shaz Qadeer , University of California, Berkeley
Matt Kaufmann , Motorola Inc., Austin, TX
Jae-Young Jang , University of Colorado, Boulder
pp. 173
Session 10: System-Level Exploration and Refinement

Interface-Based Design (Abstract)

Alberto Sangiovanni-Vincentelli , University of California at Berkeley
James A. Rowson , Alta Group of Cadence Design Systems Inc.
pp. 178

An Integrated Design Environment for Performance and Dependability Analysis (Abstract)

Barry W. Johnson , University of Virginia, Charlottesville
Ramesh Rao , University of Virginia, Charlottesville
Anup Ghosh , University of Virginia, Charlottesville
Robert H. Klenke , University of Virginia, Charlottesville
James H. Aylor , University of Virginia, Charlottesville
Moshe Meyassed , University of Virginia, Charlottesville
pp. 184

A Dynamic Design Estimation and Exploration Environment (Abstract)

Ole Bentz , Silicon Graphics, Inc., Mountain View, CA
David Lidsky , University of California, Berkeley, CA
Jan M. Rabaey , University of California, Berkeley, CA
pp. 190
Session 11: Binary Decision Diagrams

Remembrance of Things Past: Locality and Memory in BDDs (Abstract)

Srilatha Manne , University of Colorado, Boulder
Fabio Somenzi , University of Colorado, Boulder
Dirk Grunwald , University of Colorado, Boulder
pp. 196

Linear Sifting of Decision Diagrams (Abstract)

Christoph Meinel , Universit?t Trier, Germany
Thorsten Theobald , Universit?t Trier, Germany
Fabio Somenzi , University of Colorado at Boulder
pp. 202

Safe BDD Minimization Using Don't Cares (Abstract)

Youpyo Hong , University of Southern California, Los Angeles
Jerry R. Burch , Cadence Berkeley Laboratories, Berkeley, CA
Peter A. Beerel , University of Southern California, Los Angeles
Kenneth L. McMillan , Cadence Berkeley Laboratories, Berkeley, CA
pp. 208
Session 12: Timing Analysis

Exact Required Time Analysis via False Path Detection (Abstract)

Yuji Kukimoto , University of California, Berkeley, CA
Robert K. Brayton , University of California, Berkeley, CA
pp. 220

Symbolic Timing Verification of Timing Diagrams using Presburger Formulas (Abstract)

Tod Amon , Southwest Texas State University, San Marcos, TX
Jiwen Liu , Southwest Texas State University, San Marcos, TX
Taokuan Hu , Southwest Texas State University, San Marcos, TX
Gaetano Borriello , University of Washington, Seattle
pp. 226
Session 13: Embedded Tutorial

Code Generation for Core Processors (Abstract)

Peter Marwedel , Universit?t Dortmund, Germany
pp. 232
Session 14: Panel
Session 15: System-Level Optimization and Verification

Interface Timing Verification Drives System Design (Abstract)

Peter R. Suaris , Interconnectix, a Mentor Graphics Business, Portland, OR
Ajay J. Daga , Interconnectix, a Mentor Graphics Business, Portland, OR
pp. 240

Memory-CPU Size Optimization for Embedded System Designs (Abstract)

Mitsuhiro Yasuda , Mitsubishi Electric Company, Yokohama, Japan
Hisao Koizumi , Mitsubishi Electric Company, Yokohama, Japan
Hiroyuki Tomiyama , Kyushu University, Kasuga-shi, Japan
Hiroto Yasuura , Kyushu University, Kasuga-shi, Japan
Barry Shackleford , Hewlett-Packard Laboratories, Palo Alto, CA; Mitsubishi Electric Company, Yokohama, Japan
Etsuko Okushi , Mitsubishi Electric Company, Yokohama, Japan
pp. 246

Methodology for Behavioral Synthesis-based Algorithm-level Design Space Exploration: DCT Case Study (Abstract)

Miodrag Potkonjak , University of California, Los Angeles
Ramesh Karri , University of Massachusetts, Amherst
Kyosun Kim , University of Massachusetts, Amherst
pp. 252
Session 16: Formal Verification

Formal Verification In a Commercial Setting (Abstract)

R. P. Kurshan , Bell Laboratories, Murray Hill, NJ
pp. 258

Equivalence Checking Using Cuts and Heaps (Abstract)

Florian Krohm , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Andreas Kuehlmann , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 263
Session 17: Analog Simulation

Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances (Abstract)

C.-J. Richard Shi , University of Iowa, Iowa City
Michael W. Tian , University of Iowa, Iowa City
pp. 275

SWITTEST: Automatic Switch-level Fault Simulation and Test Evaluation of Switched-Capacitor Systems (Abstract)

S. Mir , Instituto de Microelectr?nica de Sevilla, Sevilla, Spain
E. Peral?as , Instituto de Microelectr?nica de Sevilla, Sevilla, Spain
J. L. Huertas , Instituto de Microelectr?nica de Sevilla, Sevilla, Spain
T. Olbrich , AMS - Austria Mikro Systeme Int. AG, Austria
A. Rueda , Instituto de Microelectr?nica de Sevilla, Sevilla, Spain
pp. 281
Session 18: Software Synthesis for Embedded Systems

System Level Fixed-Point Design Based on an Interpolative Approach (Abstract)

Holger Keding , Aachen University of Technology, Germany
Markus Willems , Aachen University of Technology, Germany
Heinrich Meyr , Aachen University of Technology, Germany
Volker B?rsgens , Aachen University of Technology, Germany
Thorsten Gr?tker , Aachen University of Technology, Germany
pp. 293

ISDL: An Instruction Set Description Language for Retargetability (Abstract)

Srinivas Devadas , Department of EECS, MIT
Silvina Hanono , Department of EECS, MIT
George Hadjiyiannis , Department of EECS, MIT
pp. 299

Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign (Abstract)

Douglas D. Dunlop , Alta Group of Cadence Design Systems, Inc.
Soumya Desai , Alta Group of Cadence Design Systems, Inc.
Edwin A. Harcourt , Alta Group of Cadence Design Systems, Inc.
James A. Rowson , Alta Group of Cadence Design Systems, Inc.
Neeti Khullar , Alta Group of Cadence Design Systems, Inc.
Prakash D. Reddy , Alta Group of Cadence Design Systems, Inc.
Mark R. Hartoog , Alta Group of Cadence Design Systems, Inc.
pp. 303
Session 19: Experiences in System Design and Education at Universities

Education for the Deep Submicron Age: Business as Usual? (Abstract)

H. De Man , Katholieke Universiteit Leuven/IMEC, Belgium
pp. 307

InfoPad - An Experiment in System Level Design and Integration (PDF)

Robert Brodersen , Dept. of EECS University of California, Berkeley
pp. 313

Very Rapid Prototyping of Wearable Computers: A Case Study of Custom versus Off-the-Shelf Design Methodologies (Abstract)

Asim Smailagic , Carnegie Mellon University, Pittsburgh, PA
Richard Martin , Carnegie Mellon University, Pittsburgh, PA
John Stivoric , Carnegie Mellon University, Pittsburgh, PA
Daniel P. Siewiorek , Carnegie Mellon University, Pittsburgh, PA
pp. 315
Session 20: Standard Cell and Physical Design Methods

CAD at the Design-Manufacturing Interface (Abstract)

P. K. Nag , Carnegie Mellon University, Pittsburgh, PA
J. Khare , Level One Communications, Sacramento, CA
C. Ouyang , Carnegie Mellon University, Pittsburgh, PA
H. T. Heineken , Level One Communications, Sacramento, CA
W. A. Pleskacz , Warsaw University of Technology, Poland
W. Maly , Carnegie Mellon University, Pittsburgh, PA
pp. 321

CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries (Abstract)

Larry G. Jones , Motorola, Inc., Austin, Texas
Srilata Raman , Motorola, Inc., Austin, Texas
Daniel Dulitz , Motorola, Inc., Austin, Texas
Mohan Guruswamy , Motorola, Inc., Austin, Texas
Andrea Fernandez , Motorola, Inc., Austin, Texas
Robert L. Maziasz , Motorola, Inc., Austin, Texas
Venkat Chiluvuri , Motorola, Inc., Austin, Texas
pp. 327

Developing A Concurrent Methodology For Standard-Cell Library Generation (Abstract)

T. G. Matheson , Mentor Graphics Corporation
Thomas Varga , LSI Logic Corporation
Robert C. Armstrong , LSI Logic Corporation
Donald G. Baltus , LSI Logic Corporation
John Duh , Mentor Graphics Corporation
pp. 333

A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis (Abstract)

John F. Croix , Advanced Micro Devices, Inc., Austin, TX
D. F. Wong , The University of Texas at Austin
pp. 337
Session 21: Modeling and Transformations in Synthesis

Limited Exception Modeling and Its Use in Presynthesis Optimizations (Abstract)

Jian Li , University of Illinois, Urbana-Champaign
Rajesh K. Gupta , University of California, Irvine
pp. 341

Potential-Driven Statistical Ordering of Transformations (Abstract)

Inki Hong , UCLA Computer Science Department, Los Angeles, CA
Miodrag Potkonjak , UCLA Computer Science Department, Los Angeles, CA
Darko Kirovski , UCLA Computer Science Department, Los Angeles, CA
pp. 347

Synthesis of Application Specific Programmable Processors (Abstract)

Kyosun Kim , University of Massachusetts, Amherst
Ramesh Karri , University of Massachusetts, Amherst
Miodrag Potkonjak , University of California, Los Angeles
pp. 353

Symbolic Evaluation of Performance Models for Tradeoff Visualization (Abstract)

Ranga Vemuri , University of Cincinnati, Ohio
Jeffrey Walrath , University of Cincinnati, Ohio
pp. 359
Session 22: Statistical Power Estimation Techniques

Power Macromodeling for High Level Power Estimation (Abstract)

Farid N. Najm , University of Illinois at Urbana-Champaign
Subodh Gupta , University of Illinois at Urbana-Champaign
pp. 365

Statistical Estimation of the Cumulative Distribution Function for Power Dissipation in VLSI Circuits (Abstract)

Chih-Shun Ding , Rockwell International Corporation, Newport Beach, CA
Qing Wu , University of Southern California, Los Angeles, CA
Massoud Pedram , University of Southern California, Los Angeles, CA
Cheng-Ta Hsieh , University of Southern California, Los Angeles, CA
pp. 371

Statistical Estimation of Average Power Dissipation in Sequential Circuits (Abstract)

Li-Pen Yuan , Univ. of Illinois at Urbana-Champaign
Chin-Chi Teng , Avant! Corporation, Sunnyvale, CA
Sung-Mo Kang , Univ. of Illinois at Urbana-Champaign
pp. 377

Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits (Abstract)

Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
Angela Krstic , University of California, Santa Barbara
pp. 383
Session 23: Co-Simulation

Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis (Abstract)

Claudio Passerone , Politecnico di Torino - Cadence Europeans Labs, Italy
Luciano Lavagno , Politecnico di Torino - Cadence Europeans Labs, Italy
Alberto Sangiovanni-Vincentelli , University of California at Berkeley, USA
Massimiliano Chiodo , Alta Group of Cadence Design Systems, USA
pp. 389

Dynamic Communication Models in Embedded System Co-Simulation (Abstract)

Ken Hines , University of Washington, Seattle
Gaetano Borriello , University of Washington, Seattle
pp. 395
Session 24: Panel
Session 25: Emerging Technologies and Architecture for Low Power

Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks (Abstract)

Vivek De , Intel Corp., Hillsboro, OR
Abhijit Chatterjee , Georgia Institute of Technology
Pankaj Pant , Georgia Institute of Technology
pp. 403

Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology (Abstract)

Anantha Chandrakasan , Massachusetts Institute of Technology, Cambridge
James Kao , Massachusetts Institute of Technology, Cambridge
Dimitri Antoniadis , Massachusetts Institute of Technology, Cambridge
pp. 409

Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT (Abstract)

Thucydides Xanthopoulos , Massachusetts Institute of Technology, Cambridge
Yoshifumi Yaoi , Massachusetts Institute of Technology, Cambridge
Anantha Chandrakasan , Massachusetts Institute of Technology, Cambridge
pp. 415

A Power Estimation Framework for Designing Low Power Portable Video Applications (Abstract)

Chih-Shun Ding , University of Southern California, Los Angeles, CA
Chi-Ying Tsui , Hong Kong Univ. of Science and Technology, Clear Water Bay, H.K.
Kai-Keung Chan , Hong Kong Univ. of Science and Technology, Clear Water Bay, H.K.
Qing Wu , University of Southern California, Los Angeles, CA
Massoud Pedram , University of Southern California, Los Angeles, CA
pp. 421

An Investigation of Power Delay Tradee-offs On PowerPC Circuits (Abstract)

Shantanu Ganguly , Motorola Inc., Austin, TX
Sarma B. K. Vrudhula , University of Arizona. Tucson, AZ
Qi Wang , University of Arizona. Tucson, AZ
pp. 425
Session 26: High Level Synthesis for Low Power

Power Management Techniques for Control-Flow Intensive Designs (Abstract)

Kazutoshi Wakabayashi , NEC Corp., Tokyo, Japan
Anand Raghunathan , Princeton University, NJ
Niraj K. Jhay , Princeton University, NJ
Sujit Dey , NEC USA, Princeton, NJ
pp. 429

Power-conscious High Level Synthesis Using Loop Folding (Abstract)

Daehong Kim , Seoul National University, Korea
Kiyoung Choi , Seoul National University, Korea
pp. 441
Session 27: Module Generation

The Future of Custom Cell Generation in Physical Synthesis (Abstract)

David Marple , Synopsys Inc., Mountain View, CA
Martin Lefebvre , Cadabra Design Libraries Inc., Nepean, Ont.
Carl Sechen , University of Washington, Seattle, WA
pp. 446

CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells (Abstract)

John P. Hayes , University of Michigan, Ann Arbor
Avaneendra Gupta , University of Michigan, Ann Arbor; Intel Corporation, Santa Clara, CA
pp. 452

An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design (Abstract)

S. M. Kang , University of Illinois at Urbana-Champaign
Jaewon Kim , Quickturn Design Systems, Inc., Mountain View, CA
pp. 456

Technology Retargeting for IC Layout (Abstract)

John Lakos , Mentor Graphics Corporation, Warren, NJ
pp. 460
Session 28: BIST and DFT

A Test Synthesis Approach to Reducing BALLAST DFT Overhead (Abstract)

Kwang-Ting Cheng , Univ. of Calif., Santa Barbara
Takashi Aikyo , Fujitsu Limited, Japan
Malgorzata Marek-Sadowska , Univ. of Calif., Santa Barbara
Mike Tien-Chien Lee , Avant! Corp., Sunnyvale, CA
Douglas Chang , Univ. of Calif., Santa Barbara
pp. 466

STARBIST: Scan Autocorrelated Random Pattern Generation (Abstract)

S. Hellebrand , University of Siegen, Germany
M. Marek-Sadowska , University of California, Santa Barbara
K. H. Tsai , University of California, Santa Barbara
J. Rajski , Mentor Graphics Corporation, Wilsonville, OR
pp. 472

A Hybrid Algorithm for Test Point Selection for Scan-Based BIST (Abstract)

Chih-Jen Lin , Intel Corporation, Hillsboro, OR
Huan-Chih Tsai , University of California, Santa Barbara
Kwang-Ting Cheng , University of California, Santa Barbara
Sudipta Bhawmik , Lucent Technologies, Princeton, NJ
pp. 478
Session 29: Panel
Session 30: DSP & Telecommunication System Design

Design and Synthesis of Array Structured Telecommunication Processing Applications (Abstract)

Wolfgang Meyer , Synopsys, Inc., Mountain View, CA
Andrew Seawright , Synopsys, Inc., Mountain View, CA
Fumiya Tada , Hitachi, Ltd., Japan
pp. 486

RASSP Virtual Prototyping of DSP Systems (Abstract)

J. Pridgen , Lockheed Martin Advanced Technology Laboratories, Camden, NJ
W. Kline , Lockheed Martin Advanced Technology Laboratories, Camden, NJ
C. Hein , Lockheed Martin Advanced Technology Laboratories, Camden, NJ
pp. 492

A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders (Abstract)

Claus Schneider , Siemens AG, Corporate Technology, Munich
pp. 498
Session 31: Embedded Tutorial

High-Level Power Modeling, Estimation, and Optimization (Abstract)

Fabio Somenzi , University of Colorado, Boulder
Massoud Pedram , University of Southern California, Los Angeles
Enrico Macii , Politecnico di Torino, Italy
pp. 504
Session 32: Advances in Partitioning

A Network Flow Approach for Hierarchical Tree Partitioning (Abstract)

Chung-Kuan Cheng , University of California, San Diego
Ming-Ter Kuo , Aptix Corporation, San Jose, CA
pp. 512

Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy (Abstract)

Allen C.-H. Wu , Tsing Hua University, Taiwan
Wen-Jong Fang , Tsing Hua University, Taiwan
pp. 518

A Hierarchy-Driven FPGA Partitioning Method (Abstract)

Helena Krupnova , Institut National Polytechnique de Grenoble / CSI, France
Ali Abbara , Institut National Polytechnique de Grenoble / CSI, France
Gabri?le Saucier , Institut National Polytechnique de Grenoble / CSI, France
pp. 522

Multilevel Hypergraph Partitioning: Application in VLSI Domain (Abstract)

Rajat Aggarwal , University of Minnesota, Minneapolis
Vipin Kumar , University of Minnesota, Minneapolis
George Karypis , University of Minnesota, Minneapolis
Shashi Shekhar , University of Minnesota, Minneapolis
pp. 526

Multilevel Circuit Partitioning (Abstract)

Charles J. Alpert , IBM Austin Research Laboratory, Austin, TX
Andrew B. Kahng , Cadence Design Systems, Inc., San Jose, CA
Jen-Hsin Huang , Synopsys, Inc., Mountain View, CA
pp. 530
Session 33: Processor Test Techniques

Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs (Abstract)

Indradeep Ghosh , Princeton University, NJ
Anand Raghunathan , Princeton University, NJ
Niraj K. Jha , Princeton University, NJ
pp. 534

Frequency-Domain Compatibility in Digital Filter BIST (Abstract)

Laurence Goodby , Hewlett-Packard Company, Palo Alto, CA
Alex Orailoglu , University of California, San Diego
pp. 540

A Scheme for Integrated Controller-Datapath Fault Testing (Abstract)

M. Nourani , University of Tehran, Iran
C. Papachristou , Case Western Reserve University, Ohio
J. Carletta , Case Western Reserve University, Ohio
pp. 546
Session 34: Panel

The Next Generation HDL (Abstract)

pp. 552
Session 35: Design Processes and Frameworks

Executable Workflows: A Paradigm for Collaborative Design on the Internet (Abstract)

Krzysztof Kozminski , National Semiconductor Corp., Santa Clara, CA
Amit Khetawat , NC State University, Raleigh
Franc Brglez , NC State University, Raleigh
Hemang Lavana , NC State University, Raleigh
pp. 553

Modeling Design Tasks and Tools - The Link between Product and Flow Model - (Abstract)

Bernd Sch?rmann , University of Kaiserslautern, Germany
Joachim Altmeyer , University of Kaiserslautern, Germany
pp. 564
Session 36: Probabilistic Models of Input Data for Efficient Power Estimation

Hierarchical Sequence Compaction for Power Estimation (Abstract)

Diana Marculescu , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
Radu Marculescu , University of Southern California, Los Angeles
pp. 570

Profile-Driven Program Synthesis for Evaluation of System Power Dissipation (Abstract)

Cheng-Ta Hsieh , University of Southern California, Los Angeles
Gaurav Mehta , Intel Corporation, Santa Clara, CA
Massoud Pedram , University of Southern California, Los Angeles
Fred Rastgar , Intel Corporation, Santa Clara, CA
pp. 576

Analytical Estimation of Transition Activity from Word-Level Signal Statistics (Abstract)

Ibrahim N. Hajj , University of Illinois at Urbana-Champaign
Sumant Ramprasad , University of Illinois at Urbana-Champaign
Naresh R. Shanbhag , University of Illinois at Urbana-Champaign
pp. 582
Session 37: Hot Topics in Routing

Wire Segmenting for Improved Buffer Insertion (Abstract)

Charles Alpert , IBM Austin Research Laboratory, Austin, TX
Anirudh Devgan , IBM Austin Research Laboratory, Austin, TX
pp. 588

More Practical Bounded-Skew Clock Routing (Abstract)

Andrew B. Kahng , Cadence Design Systems, Inc., San Jose, CA
C.-W. Albert Tsao , Cadence Design Systems, Inc., San Jose, CA
pp. 594

An Efficient Approach to Multi-layer Layer Assignment with Application to Via Minimization (Abstract)

Jason Cong , University of California, Los Angeles
Chin-Chih Chang , University of California, Los Angeles
pp. 600

Optimal Wire-Sizing Function with Fringing Capacitance Consideration (Abstract)

Chung-Ping Chen , University of Texas, Austin
D. F. Wong , University of Texas, Austin
pp. 604
Session 38: Test Generation and Fault Simulation

Fault Simulation under the Multiple Observation Time Approach using Backward Implications (Abstract)

Irith Pomeranz , University of Iowa, Iowa City
Sudhakar M. Reddy , University of Iowa, Iowa City
pp. 608

ATPG for Heat Dissipation Minimization during Scan Testing (Abstract)

Sandeep K. Gupta , University of Southern California, Los Angeles
Seongmoon Wang , University of Southern California, Los Angeles
pp. 614

Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits (Abstract)

Enric Pastor , Universitat Polit?cnica de Catalunya, Spain
Jordi Cortadella , Universitat Polit?cnica de Catalunya, Spain
Oriol Roig , Universitat Polit?cnica de Catalunya, Spain
Marco A. Pe? , Universitat Polit?cnica de Catalunya, Spain
pp. 620
Session 39: Panel
Session 40: Deep Submicron Modeling and Analysis

Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology (Abstract)

Jason Cong , UCLA, Los Angeles, CA
Lei He , UCLA, Los Angeles, CA
Nagesh Shirali , Cadence Design Systems, Inc., San Jose, CA
David Noice , Cadence Design Systems, Inc., San Jose, CA
Steve H.-C. Yen , Cadence Design Systems, Inc., San Jose, CA
Andrew B. Kahng , Cadence Design Systems, Inc., San Jose, CA
pp. 627

Accurate and Efficient Macromodel of Submicron Digital Standard Cells (Abstract)

Cristiano Forzan , SGS-THOMSON Microelectronics, Italy
Bruno Franzini , SGS-THOMSON Microelectronics, Italy
Carlo Guardiani , SGS-THOMSON Microelectronics, Italy
pp. 633

Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design (Abstract)

Howard H. Chen , Thomas J. Watson Research Center, Yorktown Heights, NY
David D. Ling , Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 638
Session 41: Technology-Dependent Optimization for Performance and Power

FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits (Abstract)

Jason Cong , University of California, Los Angeles
Chang Wu , University of California, Los Angeles
pp. 644

Technology-dependent Transformations for Low-Power Synthesis (Abstract)

Farid N. Najm , University of Illinois at Urbana-Champaign
Rajendran Panda , Motorola, Inc., Austin, TX
pp. 650

Low Power FPGA Design - A Re-engineering Approach (Abstract)

C. L. Liu , Univ. of Illinois at Urbana-Champaign
Chau-Shen Chen , Tsing Hua University, Hsin-Chu, Taiwan
TingTing Hwang , Tsing Hua University, Hsin-Chu, Taiwan
pp. 656

Post-Layout Logic Restructuring for Performance Optimization (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara
Kwang-Ting Cheng , University of California, Santa Barbara
Yi-Min Jiang , University of California, Santa Barbara
Angela Krstic , University of California, Santa Barbara
pp. 662

Layout Driven Re-synthesis for Low Power Consumption LSIs (Abstract)

Takashi Ishioka , Semiconductor DA & TEST Engineering Center, Kawasaki, Japan
Takashi Mitsuhashi , Semiconductor DA & TEST Engineering Center, Kawasaki, Japan
Masami Murakata , Semiconductor DA & TEST Engineering Center, Kawasaki, Japan
Masako Murofushi , Semiconductor DA & TEST Engineering Center, Kawasaki, Japan
pp. 666
Session 42: CAD Issues for Micro-Electro-Mechanical Systems

Overview of Microelectromechnical Systems and Design Processes (Abstract)

William C. Tang , MEMS Technology Group, Pasadena, California
pp. 670

CAD and Foundries for Microsystems (Abstract)

P. Drake , Mentor Graphics, UK
V. Szekely , Technical University of Budapest, Hungary
H. Boutamine , TIMA Lab., France
J. M. Karam , TIMA Lab., France
M. Glesner , Darmstadt University of Technology, Germany
B. Courtois , TIMA Lab., France
M. Renez , Technical University of Budapest, Hungary
A. Poppe , Technical University of Budapest, Hungary
K. Hofmann , Darmstadt University of Technology, Germany
pp. 674

Structured Design of Microelectromechanical Systems (Abstract)

Gary K. Fedder , Carnegie Mellon University, Pittsburgh, PA
Tamal Mukherjee , Carnegie Mellon University, Pittsburgh, PA
pp. 680

Algorithms for Coupled Domain MEMS Simulation (Abstract)

J. White , Massachusetts Institute of Technology, Cambridge, MA
N. Aluru , Massachusetts Institute of Technology, Cambridge, MA
pp. 686
Session 43: Hardware/Software Partitioning

A Hardware/Software Partitioner using a Dynamically Determined Granularity (Abstract)

Rolf Ernst , Technische Universit?t Braunschweig, Germany
J? Henkel , NEC USA, Princeton, NJ
pp. 691

System-Level Synthesis of Low-Power Hard Real-Time Systems (Abstract)

Darko Kirovski , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 697

COSYN: Hardware-Software Co-Synthesis of Embedded Systems (Abstract)

Ganesh Lakshminarayana , Princeton University, NJ
Bharat P. Dave , Princeton University, NJ
Niraj K. Jha , Princeton University, NJ
pp. 703

Data-flow Assisted Behavioral Partitioning for Embedded Systems (Abstract)

Rajesh K. Gupta , University of California, Irvine
Samir Agrawal , Synopsys, Inc., Mountain View, CA
pp. 709

Hardware/Software Partitioning and Pipelining (Abstract)

Daniel D. Gajski , University of California, Irvine
Smita Bakshi , University of California, Davis
pp. 713
Session 44: Embedded Tutorial

Chip Parasitic Extraction and Signal Integrity Verification (Abstract)

Wayne W.-M. Dai , University of California at Santa Cruz
pp. 717
Panel
Session 45: Designing High Performance and Low Power Microprocessors Using Full Custom Techniques

Designing High Performance CMOS Microprocessors Using Full Custom Techniques (Abstract)

Nicholas L. Rethman , Digital Semiconductor, Hudson, MA
Randy L. Allmon , Digital Semiconductor, Hudson, MA
William J. Grundmann , Digital Semiconductor, Hudson, MA
Dan Dobberpuhl , Digital Semiconductor, Palo Alto, CA
pp. 722
Session 46: Formal Verification Techniques

Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits (Abstract)

Stefano Quer , Politecnico di Torino, Italy
Luciano Lavagno , Politecnico di Torino, Italy
Gianpiero Cabodi , Politecnico di Torino, Italy
Paolo Camurati , Universit? di Udine, Italy
pp. 728

An Efficient Assertion Checker for Combinational Properties (Abstract)

Gagan Hasteer , University of Illinois, Urbana
Anmol Mathur , Silicon Graphics, Mountain View, CA
Prithviraj Banerjee , Northwestern University, Evanston, IL
pp. 734

Toward Formalizing a Validation Methodology Using Simulation Coverage (Abstract)

Aarti Gupta , CCRL, NEC USA, Princeton, NJ
Pranav Ashar , CCRL, NEC USA, Princeton, NJ
Sharad Malik , Princeton University, NJ
pp. 740
Session 47: Placement Techniques

Algorithms for Large-Scale Flat Placement (Abstract)

Jens Vygen , University of Bonn, Germany
pp. 746

Quadratic Placement Revisited (Abstract)

D. J.-H. Huang , UCLA Computer Science Dept., Los Angeles, CA
K. Yan , UCLA Computer Science Dept., Los Angeles, CA
C. J. Alpert , IBM Austin Research Laboratory, Austin, TX
I. Markov , UCLA Mathematics Dept., Los Angeles, CA
T. Chan , UCLA Mathematics Dept., Los Angeles, CA
pp. 752

Unification of Budgeting and Placement (Abstract)

David Knol , Northwestern University, Evanston, IL
Majid Saraafzadeh , Northwestern University, Evanston, IL
Gustavo Tellez , Northwestern University, Evanston, IL
pp. 758

Cluster Refinement for Block Placement (Abstract)

Chung-Kuan Cheng , University of California, San Diego
Jin Xu , University of California, San Diego
Pei-Ning Guo , University of California, San Diego
pp. 762
Session 48: Panel
Session 49: Heterogeneous System Analysis

Computer-Aided Design of Free-Space Opto-Electronic Systems (Abstract)

P. J. Marchand , University of California, San Diego
T. P. Kurzweg , University of Pittsburgh
F. B. McCormick , University of California, San Diego
M. A. Rempel , University of Pittsburgh
S. P. Levitan , University of Pittsburgh
D. M. Chiarulli , University of Pittsburgh
C. Fan , University of California, San Diego
pp. 768

Hardware/Software Co-Simulation in a VHDL-based Test Bench Approach (Abstract)

Matthias Bauer , Siemens AG, Corporate Technology, Munich
Wolfgang Ecker , Siemens AG, Corporate Technology, Munich
pp. 774

An Embedded System Case Study: the FirmWare Development Environment for a Multimedia Audio Processor (Abstract)

Ahmed Jerraya , Laboratoire TIMA, L'Insitut National Polytechnique de Grenoble, France
Clifford Liem , Central Ramp;D, SGS-Thomson Microelectronics, France; Laboratoire TIMA, L'Insitut National Polytechnique de Grenoble, France
Jean-Marc Gentit , Thomson Consumer Electronic Components, France
Jean Lopez , Thomson Consumer Electronic Components, France
Xavier Figari , Thomson Consumer Electronic Components, France
Laurent Bergher , Thomson Consumer Electronic Components, France
Marco Cornero , Central Ramp;D, SGS-Thomson Microelectronics, France
Pierre Paulin , Central Ramp;D, SGS-Thomson Microelectronics, France
Miguel Santana , Central Ramp;D, SGS-Thomson Microelectronics, France
pp. 780

Author Index (PDF)

pp. 786
97 ms
(Ver )