The Community for Technology Leaders
Design Automation Conference (1996)
Las Vegas, Nevada
June 3, 1996 to June 7, 1996
ISBN: 0-89791-833-9
TABLE OF CONTENTS
Papers

Package and Interconnect Modeling of the HFA3624, a 2.4GHz RF to IF Converter (Abstract)

Mattan Kamon , Massachusetts Institute of Technology, Cambridge, Massachusetts
Steve S. Majors , Harris Semiconductor, Melbourne, Florida
pp. 2-7

HEAT: Hierarchical Energy Analysis Tool (Abstract)

Keshab K. Parhi , University of Minnesota, Minneapolis
Janardhan H. Satyanarayana , University of Minnesota, Minneapolis
pp. 9-14

POSE: Power Optimization and Synthesis Environment (Abstract)

Sasan Iman , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
pp. 21-26

Early Power Exploration - A World Wide Web Application (Abstract)

David Lidsky , University of California, Berkeley
Jan M. Rabaey , University of California, Berkeley
pp. 27-32

Behavioral Synthesis (PDF)

Raul Camposano , Synopsys, Inc. Mountain View, CA
pp. 33-34

A Register File and Scheduling Model for Application Specific Processor Synthesis (Abstract)

C. Papachristou , Case Western Reserve University, Cleveland, Ohio
E. Ercanli , Case Western Reserve University, Cleveland, Ohio
pp. 35-40

Optimized Code Generation of Multiplication-Free Linear Transforms (Abstract)

G. Venkatesh , Indian Institute of Technology, Powai, India
Mahesh Mehendale , Texas Instrumentals (India) Ltd., Bangalore, India
S. D. Sherlekar , Indian Institute of Technology, Powai, India
pp. 41-46

Concurrent Analysis Techniques for Data Path Timing Optimization (Abstract)

Chuck Monahan , University of California, Santa Barbara
Forrest Brewer , University of California, Santa Barbara
pp. 47-50

HDL Optimization Using Timed Decision Tables (Abstract)

Rajesh K. Gupta , University of Illinois, Urbana-Champaign
Jian Li , University of Illinois, Urbana-Champaign
pp. 51-54

Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems (Abstract)

Gjalt de Jong , IMEC, Leuven, Belgium
Bill Lin , IMEC, Leuven, Belgium
Eric Verlind , IMEC, Leuven, Belgium
pp. 55-58

Verification of Asynchronous Circuits using Time Petri Net Unfolding (Abstract)

Alexandre Yakovlev , University of Newcastle, England
Alexei Semenov , University of Newcastle, England
pp. 59-62

Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis (Abstract)

Michael Kishinevsky , The University of Aizu, Japan
Alex Yakovlev , University of Newcastle upon Tyne, United Kingdom
Alex Kondratyev , The University of Aizu, Japan
Luciano Lavagno , Politecnico di Torino, Italy
Jordi Cortadella , Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 63-66

A Technique for Synthesizing Distributed Burst-Mode Circuits (Abstract)

Prabhakar Kudva , IBM T.J. Watson Research Center, Yorktown Heights
Hans Jacobson , University of Utah
Ganesh Gopalakrishnan , University of Utah
pp. 67-70

Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic (Abstract)

Steven M. Nowick , Columbia University, New York, NY
Tao Wu , Columbia University, New York, NY
Michael Theobald , Columbia University, New York, NY
pp. 71-76

Synthesis of Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes (Abstract)

Steven M. Nowick , Columbia University
Hans Jacobson , University of Utah
Prabhakar Kudva , IBM T.J. Watson Research Center, Yorktown Heights
Ganesh Gopalakrishnan , University of Utah
pp. 77-82

Partitioning of VLSI Circuits and Systems (Abstract)

Frank M. Johannes , Technical University of Munich, Germany
pp. 83-87

New Spectral Linear Placement and Clustering Approach (Abstract)

Jianmin Li , University of California, San Diego
John Lillis , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
Lung-Tien Liu , University of California, San Diego
pp. 88-93

Characterization and Parameterized Random Generation of Digital Circuits (Abstract)

Derek Corneil , University of Toronto, Ontario
J. P. Grossman , University of Toronto, Ontario
Jonathan Rose , University of Toronto, Ontario
Michael Hutton , University of Toronto, Ontario
pp. 94-99

A Probability-Based Approach to VLSI Circuit Partitioning (Abstract)

Wenyong Deng , University of Minnesota, Minneapolis
Shantanu Dutt , University of Minnesota, Minneapolis
pp. 100-105

Verification of Electronic Systems (Abstract)

Alexander Saldanha , Cadence Berkeley Laboratories - Berkeley CA
Patrick C. McGeer , Cadence Berkeley Laboratories - Berkeley CA
Alberto L. Sangiovanni-Vincentelli , University of California - Berkeley CA
pp. 106-111

Design Considerations and Tools for Low-voltage Digital System Design (Abstract)

Anantha Chandrakasan , Massachusetts Institute of Technology, Cambridge
Dimitri Antoniadis , Massachusetts Institute of Technology, Cambridge
Carlin Vieri , Massachusetts Institute of Technology, Cambridge
Isabel Yang , Massachusetts Institute of Technology, Cambridge
pp. 113-118

VAMP: A VHDL Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems (Abstract)

Klaus D. M?ller-Glaser , Universit?t Karlsruhe, Germany
Bernhard Wunder , Universit?t Karlsruhe, Germany
Gunther Lehmann , Universit?t Karlsruhe, Germany
pp. 119-124

A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU design using circuit simulation (Abstract)

Y. T. Yen , Digital Equipment Corp, Hudson MA
Madhav P. Desai , Digital Equipment Corp, Hudson MA
pp. 125-130

High-Level Synthesis for Testability: A Survey and Perspective (Abstract)

Kenneth D. Wagner , Synopsys, Inc., Mountain View, CA
Sujit Dey , NEC USA, Inc., Princeton, NJ
pp. 131-136

Introspection: A Low Overhead Binding Technique During Self-Diagnosing Microarchitecture Synthesis (Abstract)

Ramesh Karri , University of Massachusetts at Amherst, MA
Balakrishnan Iyer , University of Massachusetts at Amherst, MA
pp. 137-142

Lower Bounds on Test Resources for Scheduled Data Flow Graphs (Abstract)

Sandeep K. Gupta , University of Southern California, Los Angeles
Ishwar Parulkar , University of Southern California, Los Angeles
Melvin A. Breuer , University of Southern California, Los Angeles
pp. 143-148

Oscillation Control in Logic Simulation using Dynamic Dominance Graphs (Abstract)

Peter Dahlgren , Chalmers University of Technology, Sweden
pp. 155-160

Compact Vector Generation for Accurate Power Simulation (Abstract)

Kuang-Chien Chen , Fujitsu Labs of America, Santa Clara, CA
Tien-Chien Lee , Fujitsu Labs of America, Santa Clara, CA
Kwang-Ting Cheng , Univ. of California, Santa Barbara
Shi-Yu Huang , Univ. of California, Santa Barbara
pp. 161-164

Improving the Efficiency of Power Simulators by Input Vector Compaction (Abstract)

Diana Marculescu , University of Southern California, Los Angeles, CA
Chi-ying Tsui , Hong Kong University of Science and Technology, Clear Water Bay, Hong Kong
Massoud Pedram , University of Southern California, Los Angeles, CA
Radu Marculescu , University of Southern California, Los Angeles, CA
pp. 165-168

Efficient Communication in a Design Environment (Abstract)

Helena Sarmento , INESC - Instituto de Engenharia de Sistemas e Computadores, Portugal
Paulo Ver?ssimo , INESC - Instituto de Engenharia de Sistemas e Computadores, Portugal
Idalina Videira , INESC - Instituto de Engenharia de Sistemas e Computadores, Portugal
pp. 169-174

A Description Language for Design Process Management (Abstract)

Peter R. Sutton , Carnegie Mellon University, Pittsburgh PA
Stephen W. Director , Carnegie Mellon University, Pittsburgh PA
pp. 175-180

Improved Tool and Data Selection in Task Management (Abstract)

John W. Hagerman , Carnegie Mellon University, Pittsburgh, PA
Stephen W. Director , Carnegie Mellon University, Pittsburgh, PA
pp. 181-184

Application of a Markov Model to the Measurement, Simulation, and Diagnosis of an Iterative Design Process (Abstract)

Eric W. Johnson , University of Notre Dame, IN
Luis A. Castillo , University of Notre Dame, IN
Jay B. Brockman , University of Notre Dame, IN
pp. 185-188

Tutorial: Design of a Logic Synthesis System (Abstract)

Richard Rudell , Synopsys, Inc., Mountain View, CA
pp. 191-196

On Solving Covering Problems (Abstract)

Olivier Coudert , Synopsys Inc., Mountain View, CA
pp. 197-202

A New Complete Diagnosis Patterns for Wiring Interconnects (Abstract)

Sungju Park , Hanyang University, Korea
pp. 203-208

A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuits (Abstract)

Chih-Ang Chen , University of Southern California, Los Angeles
Sandeep K. Gupta , University of Southern California, Los Angeles
pp. 209-214

On Static Compaction of Test Sequences for Synchronous Sequential Circuits (Abstract)

Irith Pomeranz , University of Iowa, Iowa City
Sudhakar M. Reddy , University of Iowa, Iowa City
pp. 215-220

An O(n) Algorithm for Transistor Stacking with Performance Constraints (Abstract)

Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, PA
pp. 221-226

Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC Design (Abstract)

Alberto L. Sangiovanni-Vincentelli , University of California, Berkeley, CA
Iasson Vassiliou , University of California, Berkeley, CA
Paolo Miliozzi , University of California, Berkeley, CA
Edoardo Charbon , University of California, Berkeley, CA
Enrico Malavasi , Cadence Design Systems, Inc., CA
pp. 227-232

Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits (Abstract)

Erich Barke , University of Hanover, Germany
Lars Hedrich , University of Hanover, Germany
Carsten Borchers , University of Hanover, Germany
pp. 237-240

Multilevel Logic Synthesis for Arithmetic Functions (Abstract)

Chien-Chung Tsai , Mentor Graphics Corporation, Wilsonville, OR
Malgorzata Marek-Sadowska , University of California, Santa Barbara, CA
pp. 242-247

Synthesis by Spectral Translation Using Boolean Decision Diagrams (Abstract)

Jeffery P. Hansen , Toshiba ULSI Research Laboratories, Japan
Masatoshi Sekine , Toshiba ULSI Research Laboratories, Japan
pp. 248-253

Delay Minimal Decomposition of Multiplexers in Technology Mapping (Abstract)

Shashidhar Thakur , Synopsys Inc., Mountainview, CA
D. F. Wong , University of Texas at Austin
Shankar Krishnamoorthy , Synopsys Inc., Mountainview, CA
pp. 254-257

Error Correction Based on Verification Techniques (Abstract)

Shi-Yu Huang , U. of California, Santa Barbara
Kwang-Ting Cheng , U. of California, Santa Barbara
Kuang-Chien Chen , Fujitsu Labs of America, Santa Clara, CA
pp. 258-261

Layout Driven Selecting and Chaining of Partial Scan Flip-Flops (Abstract)

TingTing Hwang , Tsing Hua University, Taiwan
Chau-Shen Chen , Tsing Hua University, Taiwan
Kuang-Hui Lin , Tsing Hua University, Taiwan
pp. 262-267

Test Point Insertion: Scan Paths through Combinational Logic (Abstract)

Chih-chang Lin , Mentor Graphics, San Jose, CA
Malgorzata Marek-Sadowska , Univ. of California, Santa Barbara, CA
Mike Tien-Chien Lee , Fujitsu Lab. of America, Santa Clara, CA
Kwang-Ting Cheng , Univ. of California, Santa Barbara, CA
pp. 268-273

Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming (Abstract)

Chung-Kuan Cheng , University of California, San Diego
Huoy-Yu Liou , University of California, San Diego
Ting-Ting Y. Lin , University of California, San Diego
pp. 274-279

Homotopy Techniques for Obtaining a DC Solution of Large-Scale MOS Circuits (Abstract)

J. S. Roychowdhury , AT&T Bell Laboratories, Murray Hill, NJ
R. C. Melville , AT&T Bell Laboratories, Murray Hill, NJ
pp. 286-291

Efficient AC and Noise Analysis of Two-Tone RF Circuits (Abstract)

Jacob White , Massachusetts Institute of Technology, Cambridge, Massachusetts
Ricardo Telichevesky , Cadence Design Systems, San Jose California
Ken Kundert , Cadence Design Systems, San Jose California
pp. 292-297

Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies (Abstract)

Georges G. E. Gielen , Katholieke Universiteit Leuven, Belgium
Willy M. C. Sansen , Katholieke Universiteit Leuven, Belgium
Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, PA
L. Richard Carley , Carnegie Mellon University, Pittsburgh, PA
pp. 298-303

Code Generation and Analysis for the Functional Verification of Microprocessors (Abstract)

Dimitrios Mavroidis , Silicon Graphics Inc., Mountain View, CA
Anoosh Hosseini , Silicon Graphics Inc., Mountain View, CA
Pavlos Konas , Silicon Graphics Inc., Mountain View, CA
pp. 305-310

Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Proccessor (Abstract)

Val Popescu , Metaflow Technologies, Inc., La Jolia, CA
Bill McNamara , Zycad Corporation, Irvine, CA
pp. 311-314

Hardware Emulation for Functional Verification of K5 (Abstract)

Ming Wang , Quickturn Design Systems, Mountain View, CA
Ram Narayan , Advanced Micro Devices, Austin, TX
Denzil Fernandez , Advanced Micro Devices, Austin, TX
Gopi Ganapathy , Advanced Micro Devices, Austin, TX
Glenn Jorden , Advanced Micro Devices, Austin, TX
Jim Nishimura , Quickturn Design Systems, Mountain View, CA
pp. 315-318

Functional Verification Methodology for the PowerPC 604™ Microprocessor (Abstract)

David Holloway , Somerset Design Center, Austin, TX
Rajesh Raina , Somerset Design Center, Austin, TX
James Monaco , Somerset Design Center, Austin, TX
pp. 319-324

I'm Done Simulating; Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha microprocessor (Abstract)

Lisa M. Noack , Digital Equipment Corporation, Hudson, MA
Michael Kantrowitz , Digital Equipment Corporation, Hudson, MA
pp. 325-330

Glitch Analysis and Reduction in Register Transfer Level Power Optimization (Abstract)

Niraj K. Jha , Princeton University, NJ
Sujit Dey , NEC USA, Inc., Princeton, NJ
Anand Raghunathan , Princeton University, NJ
pp. 331-336

Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-based Approach (Abstract)

Mani Srivastava , AT&T Bell Laboratories, Murray Hill, NJ
Miodrag Potkonjak , University of California, Los Angeles, CA
pp. 343-348

Scheduling Techniques to Enable Power Management (Abstract)

Srinivas Devadas , MIT, Cambridge, MA
Jos? Monteiro , MIT, Cambridge, MA
Pranav Ashar , NEC USA, Princeton, NJ
Ashutosh Mauskar , Synopsys, Inc., Mountain View, CA
pp. 349-352

Electromigration Reliability Enhancement via Bus Activity Distribution (Abstract)

Aurobindo Dasgupta , University of Massachusetts, Amherst, MA
Ramesh Karri , University of Massachusetts, Amherst, MA
pp. 353-356

A Sparse Image Method for BEM Capacitance Extraction (Abstract)

Aykut Dengi , SEMATECH Inc., Austin, TX
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Byron Krauter , IBM Corp., Austin, TX
Yu Xia , AMD Corp., Austin, TX
pp. 357-362

A Parallel Precorrected FFT Based Capacitance Extraction Program for Signal Integrity Analysis (Abstract)

J. White , Massachusetts Institute of Technology, Cambridge, MA
V. B. Nadkarni , Massachusetts Institute of Technology, Cambridge, MA
N. R. Aluru , Massachusetts Institute of Technology, Cambridge, MA
pp. 363-366

Multiple Accelerated Capacitance Calculation for Structures with Multiple Dielectrics with High Permittivity Ratios (Abstract)

Jacob White , MIT Department of EECS, Cambridge, MA
Johannes Tausch , MIT Department of EECS, Cambridge, MA
pp. 367-370

Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance (Abstract)

Wayne Wei-Ming Dai , University of California, Santa Cruz
Weikai Sun , University of California, Santa Cruz
Wei Hong , Southeast Uni., Nanjing, PRC
pp. 371-376

Efficient Full-Wave Electromagnetic Analysis via Model-Order Reduction of Fast Integral Transforms (Abstract)

Eli Chiprout , IBM T. J. Watson Research Center, Yorktown Heights, NY
Joel R. Phillips , MIT Department of EECS, Cambridge, MA
David D. Ling , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 377-382

Useful-Skew Clock Routing with Gate Sizing for Low Power Design (Abstract)

Joe G. Xi , University of California, Santa Cruz
Wayne W.-M. Dai , University of California, Santa Cruz
pp. 383-388

Sizing of Clock Distribution Networks for High Performance CPU Chips (Abstract)

Radenko Cvijetic , Digital Equipment Corporation, Hudson, MA
James Jensen , Digital Equipment Corporation, Hudson, MA
Madhav P. Desai , Digital Equipment Corporation, Hudson, MA
pp. 389-394

New Performance Driven Routing Techniques with Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing (Abstract)

Ting-Ting Y. Lin , UCSD, La Jolla, CA
John Lillis , UCSD, La Jolla, CA
Ching-Yen Ho , LSI Logic Corp., Milpitas, CA
Chung-Kuan Cheng , UCSD, La Jolla, CA
pp. 395-400

Constructing Lower and Upper Bounded Delay Routing Trees using Linear Programming (Abstract)

Massoud Pedram , University of Southern California, Los Angeles, CA
Jaewon Oh , University of Southern California, Los Angeles, CA
Iksoo Pyo , Intel Corporation, Hillsboro, OR
pp. 401-404

Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation (Abstract)

D. F. Wong , University of Texas, Austin, Texas
Chung-Ping Chen , University of Texas, Austin, Texas
Yao-Wen Chang , University of Texas, Austin, Texas
pp. 405-408

How to Write Awk and Perl Scripts to Enable your EDA Tools to Work Together (Abstract)

Shankar Hemmady , Guru Technologies Inc., Cupertino, CA
Robert C. Hutchins , SMC (Standard Microsystems), Irvine, CA
pp. 409-414

The Automatic Generation of Functional Test Vectors for Rambus Designs (Abstract)

J. P. Privitera , Rambus Inc., Mountain View, CA
K. D. Jones , Rambus Inc., Mountain View, CA
pp. 415-420

Functional Verification Methodology of Chameleon Processor (Abstract)

Christian Berthet , SGS-THOMSON Microelectronics
Fran?ois Pogodalla , SGS-THOMSON Microelectronics
Jeremy Eggleton , SGS-THOMSON Microelectronics
Anthony McIsaac , SGS-THOMSON Microelectronics
Fr?d?ric Rocheteau , SGS-THOMSON Microelectronics
Mike Bartley , SGS-THOMSON Microelectronics
Fran?oise Casaubieilh , SGS-THOMSON Microelectronics
Geoff Barrett , SGS-THOMSON Microelectronics
Mike Benjamin , SGS-THOMSON Microelectronics
G?rard Mas , SGS-THOMSON Microelectronics
Mohamed Belhadj , SGS-THOMSON Microelectronics
pp. 421-426

Experience in Designing a Large-Scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools (Abstract)

Z. Zilic , University of Toronto, Canada
S. Caranci , University of Toronto, Canada
R. Grindley , University of Toronto, Canada
S. Brown , University of Toronto, Canada
Z. Vranesic , University of Toronto, Canada
K. Loveless , University of Toronto, Canada
M. Gusat , University of Toronto, Canada
S. Srbljic , University of Toronto, Canada
N. Manjikian , University of Toronto, Canada
A. Grbic , University of Toronto, Canada
pp. 427-432

Power Estimation of Cell-Based CMOS Circuits (Abstract)

Bruno Ricc? , DEIS - University of Bologna
Luca Benini , CSL - Stanford University, CA
Alessandro Bogliolo , CSL - Stanford University, CA
pp. 433-438

A New Hybrid Methodology for Power Estimation (Abstract)

Kwang-Ting Cheng , Univ. of California, Santa Barbara, CA
Deborah C. Wang , LSI Logic Corp., Milpitas, CA
David Ihsin Cheng , Mentor Graphics Corp., San Jose, CA
Malgorzata Marek-Sadowska , Univ. of California, Santa Barbara, CA
pp. 439-444

A Statistical Approach to the Estimation of Delay-Dependent Switching Activities in CMOS Combinational Circuits (Abstract)

Yong Je Lim , University of Washington, Seattle, WA
Heung-Joon Park , University of Washington, Seattle, WA
Mani Soma , University of Washington, Seattle, WA
Kyung-Im Son , University of Washington, Seattle, WA
pp. 445-450

Engineering Change in a Non-Deterministic FSM Setting (Abstract)

Amit Narayan , University of California, Berkeley, CA
Robert. K. Brayton , University of California, Berkeley, CA
A. Sangiovanni-Vincentelli , University of California, Berkeley, CA
Sriram C. Krishnan , University of California, Berkeley, CA
Kenneth L. McMillan , Cadence Berkeley Laboratories, Berkeley, CA
Sunil P. Khatri , University of California, Berkeley, CA
pp. 451-456

Identifying Sequential Redundancies Without Search (Abstract)

David E. Long , Lucent Technologies - Bell Labs., Murray Hill, NJ
Mahesh A. Iyer , Synopsys, Inc., Mountain View, CA
Miron Abramovici , Lucent Technologies - Bell Labs., Murray Hill, NJ
pp. 457-462

A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines (Abstract)

Hiroyuki Higuchi , Fujitsu Laboratories Ltd., Japan
Yusuke Matsunaga , Fujitsu Laboratories Ltd., Japan
pp. 463-466

Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques (Abstract)

Massimo Poncino , Politecnico di Torino, Italy
Donatella Sciuto , Politecnico di Milano, Italy
Fabrizio Ferrandi , Politecnico di Milano, Italy
Enrico Macii , Politecnico di Torino, Italy
Franco Fummi , Politecnico di Milano, Italy
pp. 467-470

Module Compaction in FPGA-Based Regular Datapaths (Abstract)

Andreas Koch , Tech. Univ. of Braunschweig, Germany
pp. 471-476

Network Partitioning into Tree Hierarchies (Abstract)

Chung-Kuan Cheng , University of California, San Diego
Lung-Tien Liu , AT&T Bell Laboratories, Murray Hill, New Jersey
Ming-Ter Kuo , University of California, San Diego
pp. 477-482

Efficient Approximation Algorithms for Floorplan Area Minimization (Abstract)

Danny Z. Chen , University of Notre Dame, IN
Xiaobo (Sharon) Hu , Western Michigan University, MI
pp. 483-486

Optimal Wire-Sizing Formula Under the Elmore Delay Model. (Abstract)

Yao-Ping Chen , University of Texas, Austin, Texas
Chung-Ping Chen , University of Texas, Austin, Texas
D. F. Wong , University of Texas, Austin, Texas
pp. 487-490

VLSI Design and System Level Verification for the Mini-Disc (Abstract)

Tetsuya Fujimoto , Sharp Corporation, Japan
Takashi Kambe , Sharp Corporation, Japan
pp. 491-496

Design Methodologies for Consumer-Use Video Signal Processing LSIs (Abstract)

Satoshi Ikawa , Matsushita Electric Industrial, Co., Ltd., Japan
Hisakazu Edamatsu , Matsushita Electric Industrial, Co., Ltd., Japan
Katsuya Hasegawa , Matsushita Electric Industrial, Co., Ltd., Japan
pp. 497-502

Design Methodology for Analog High Frequency ICs (Abstract)

Yoshitomo Oumi , Toshiba Corp., Japan
Seijiro Moriyama , Toshiba Corp., Japan
Yasunori Miyahara , Toshiba Corp., Japan
pp. 503-508

Issues and Answers in CAD Tool Interoperability (Abstract)

Yatin Trivedi , Seva Technologies, Fremont, CA
Mike Murray , Acuson, Mountain View, CA
Bill Berg , Mentor Graphics, Wilsonville, OR
Bill McCaffrey , High Level Design Systems, Santa Clara, CA
Uwe B. Meding , Concurrent CAE Solutions, Santa Clara, CA
Ted Vucurevich , Cadence Design Systems, San Jose, CA
pp. 509-514

The Design of Mixed Hardware/Software Systems (Abstract)

Jay K. Adams , Synopsys, Inc., Mountain View, CA
Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
pp. 515-520

Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications (Abstract)

Steven Vercauteren , IMEC, Leuven, Belgium
Hugo De Man , IMEC, Leuven, Belgium
Bill Lin , IMEC, Leuven, Belgium
pp. 521-526

A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts (Abstract)

Nobuyuki Hikichi , Software Research Associates, Inc., Japan
Akichika Shiomi , Shizuoka University, Japan
Masaharu Imai , Osaka University, Japan
Nguyen Ngoc Binh , Osaka University, Japan
pp. 527-532

Analysis of RC Interconnections Under Ramp Input (Abstract)

Sudhakar Muddu , UCLA Computer Science Department, Los Angeles, CA
Andrew B. Kahng , UCLA Computer Science Department, Los Angeles, CA
pp. 533-538

An AWE Technique for Fast Printed Circuit Board Delays (Abstract)

Bernie Sheehan , Mentor Graphics, San Jose, CA
pp. 539-544

RC-Interconnect Macromodels for Timing Simulation (Abstract)

Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Florentin Dartu , Carnegie Mellon University, Pittsburgh, PA
Bogdan Tutuianu , University of Texas at Austin
pp. 544-547

iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips (Abstract)

Yi-Kan Cheng , Univ. of Illinois at Urbana-Champaign
Chin-Chi Teng , Univ. of Illinois at Urbana-Champaign
Abhijit Dharchoudhury , Motorola Inc., Austin, TX
Elyse Rosenbaum , Univ. of Illinois at Urbana-Champaign
Sung-Mo Kang , Univ. of Illinois at Urbana-Champaign
pp. 548-551

Techniques for Verifying Superscalar Microprocessors (Abstract)

Jerry R. Burch , Cadence Berkeley Laboratories
pp. 552-557

A Scalable Formal Verification Methodology for Pipelined Microprocessors (Abstract)

Jeremy Levitt , Stanford University, CA
Kunle Olukotun , Stanford University, CA
pp. 558-563

State Reduction Using Reversible Rules (Abstract)

C. Norris Ip , Stanford University, CA
David L. Dill , Stanford University, CA
pp. 564-567

Formal Verification of Embedded Systems Based on CFSM Networks (Abstract)

Luciano Lavagno , Politecnico di Torino, Italy
Harry Hsieh , University of California at Berkeley, USA
Felice Balarin , Cadence Berkeley Laboratories, USA
Alberto Sangiovanni-Vincentelli , University of California at Berkeley, USA
pp. 568-571

Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis (Abstract)

I. Bolsens , IMEC, Belgium
E. Berrebi , TIMA, France
J. Fr?hel , SGS-Thomson Microelectronics, France
S. De Troch , IMEC, Belgium
A. A. Jerraya , TIMA, France
S. Vernalde , IMEC, Belgium
P. Kission , TIMA, France
J. C. Herluison , SGS-Thomson Microelectronics, France
pp. 573-578

FADIC: Architectural Synthesis Applied in IC Design (Abstract)

F. Welten , Philips Research Laboratories, Eindhoven, The Netherlands
J. Huisken , Philips Research Laboratories, Eindhoven, The Netherlands
pp. 579-584

Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design using VHDL (Abstract)

Ben Chen , Fujitsu Ltd., Japan
Yu-Chin Hsu , Univ. of California, Riverside
Mike Tien-Chien Lee , Fujitsu Laboratories of America, Santa Clara, CA
Masahiro Fujita , Fujitsu Laboratories of America, Santa Clara, CA
pp. 585-590

Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures (Abstract)

Mike Tien-Chien Lee , Fujitsu Laboratories of America, San Jose, CA
Guido Araujo , Princeton University, NJ
Sharad Malik , Princeton University, NJ
pp. 591-596

Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures (Abstract)

Clifford Liem , TIMA Laboratory, Inst. Nat. Polytech. de Grenoble (INPG), France; SGS-Thomson Microelectronics (ST), France
Ahmed Jerraya , TIMA Laboratory, Inst. Nat. Polytech. de Grenoble (INPG), France
Pierre Paulin , SGS-Thomson Microelectronics (ST), France
pp. 597-600

Analysis of Operation Delay and Execution Rate Constraints for Embedded Systems (Abstract)

Rajesh K. Gupta , University of Illinois, Urbana-Champaign
pp. 601-604

An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response (Abstract)

Bogdan Tutuianu , The University of Texas at Austin
Lawrence Pileggi , Carnegie Mellon University, Pittsburgh, PA
Florentin Dartu , Carnegie Mellon University, Pittsburgh, PA
pp. 611-616

Optimal Clock Skew Scheduling Tolerant to Process Variations (Abstract)

Jos? Luis Neves , University of Rochester, New York
Eby G. Friedman , University of Rochester, New York
pp. 623-628

An Efficient Equivalence Checker for Combinational Circuits (Abstract)

Yusuke Matsunaga , Fujitsu Laboratories Ltd., Japan
pp. 629-634

High Performance BDD Package By Exploiting Memory Hierarchy (Abstract)

Jagesh V. Sanghavi , University of California at Berkeley
Robert K. Brayton , University of California at Berkeley
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
Rajeev K. Ranjan , University of California at Berkeley
pp. 635-641

Implementation of an Efficient Parallel BDD Package (Abstract)

Tony Stornetta , University of California, Santa Barbara
Forrest Brewer , University of California, Santa Barbara
pp. 641-644

Word Level Model Checking - Avoiding the Pentium FDIV Error (Abstract)

X. Zhao , Intel Corporation, Hillsboro, OR; Carnegie Mellon University, Pittsburgh, PA
E. M. Clarke , Carnegie Mellon University, Pittsburgh, PA
M. Khaira , Intel Corporation, Hillsboro, OR
pp. 645-648

Formal Verification of PowerPC™ Arrays using Symbolic Trajectory Evaluation (Abstract)

Richard Raimi , Motorola Inc., Austin, TX
Derek L. Beatty , Motorola Inc., Austin, TX
Randal E. Bryant , Carnegie Mellon University Pittsburgh, PA
Manish Pandey , Carnegie Mellon University Pittsburgh, PA
pp. 649-654

RuleBase: An Industry-Oriented Formal Verification Tool (Abstract)

Avner Landver , IBM Haifa Research Laboratory, Haifa, Israel
Cindy Eisner , IBM Haifa Research Laboratory, Haifa, Israel
Ilan Beer , IBM Haifa Research Laboratory, Haifa, Israel
Shoham Ben-David , IBM Haifa Research Laboratory, Haifa, Israel
pp. 655-660

Bit-Level Analysis of an SRT Divider Circuit (Abstract)

Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
pp. 661-665

A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded Architectures (Abstract)

Hugo De Man , IMEC, Leuven, Belgium
Steven Vercauteren , IMEC, Leuven, Belgium
Bill Lin , IMEC, Leuven, Belgium
pp. 678-683

Software Development in a Hardware Simulation Environment (Abstract)

Benny Schnaider , MayaLee Consulting, Santa Clara, CA
Einat Yogev , Cisco Systems, San Jose, CA
pp. 684-689

Compiled HW/SW Co-Simulation (Abstract)

Vojin Zivojnovic , Aachen University of Technology, Germany
Heinrich Meyr , Aachen University of Technology, Germany
pp. 690-694

Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation (Abstract)

Massoud Pedram , University of Southern California, Los Angeles, CA
Diana Marculescu , University of Southern California, Los Angeles, CA
Radu Marculescu , University of Southern California, Los Angeles, CA
pp. 696-701

Energy Characterization Based on Clustering (Abstract)

Robert Michael Owens , The Pennsylvania State University, PA
Mary Jane Irwin , The Pennsylvania State University, PA
Huzefa Mehta , The Pennsylvania State University, PA
pp. 702-707

Architectural Retiming: Pipelining Latency-Constrained Circuits (Abstract)

Carl Ebeling , University of Washington, Seattle
Soha Hassoun , University of Washington, Seattle
pp. 708-713

Optimizing Systems for Effective Block-Processing: Optimizing Systems for Effective Block-Processing: (Abstract)

Marios C. Papaefthymiou , Yale University, New Haven, CT
Kumar N. Lalgudi , Yale University, New Haven, CT
Miodrag Potkonjak , University of California, Los Angeles, CA
pp. 714-719

Optimal Clock Period FPGA Technology Mapping for Sequential Circuits (Abstract)

Peichen Pan , Clarkson University, Potsdam, NY
C. L. Liu , University of Illinois at Urbana-Champaign
pp. 720-725

Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-Based FPGA Design (Abstract)

Jason Cong , University of California, Los Angeles
Yean-Yow Hwang , University of California, Los Angeles
pp. 726-729

A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs (Abstract)

Klaus Eckl , Technical University of Munich, Germany
Christian Legl , Technical University of Munich, Germany
Bernd Wurth , Synopsys, Inc., Mountain View, CA
pp. 730-733

New Algorithms for Gate Sizing: A Comparative Study (Abstract)

Ramsey Haddad , Synopsys Inc., Mountain View, CA
Srilatha Manne , University of Colorado, Boulder
Olivier Coudert , Synopsys Inc., Mountain View, CA
pp. 734-739

Post-Layout Optimization for Deep Submicron Design (Abstract)

Hideyuki Emura , NEC Corporation, Kawasaki, Japan
Masamichi Kawarabayashi , NEC Corporation, Kawasaki, Japan
Naotaka Maeda , NEC Corporation, Kawasaki, Japan
Koichi Sato , NEC Corporation, Kawasaki, Japan
pp. 740-745

Enhanced Network Flow Algorithm for Yield Optimization (Abstract)

Enrico Malavasi , Cadence Design Systems, Inc. - San Jose, CA
Cyrus Bamji , Cadence Design Systems, Inc. - San Jose, CA
pp. 746-751

Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects (Abstract)

Elyse Rosenbaum , University of Illinois at Urbana-Champaign
Yi-Kan Cheng , University of Illinois at Urbana-Champaign
Sung-Mo Kang , University of Illinois at Urbana-Champaign
Chin-Chi Teng , University of Illinois at Urbana-Champaign
pp. 752-757

Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction (Abstract)

A. J. van Genderen , Delft University of Technology, The Netherlands
N. P. van der Meijs , Delft University of Technology, The Netherlands
pp. 758-763

Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency (Abstract)

N. P. van der Meijs , Delft University of Technology, The Netherlands
P. J. H. Elias , Delft University of Technology, The Netherlands
pp. 764-769

VHDL Development System and Coding Standard (Abstract)

J?rg Pleickhardt , Lucent Technologies - Bell Labs Innovations, Germany
Johannes Schuck , Lucent Technologies - Bell Labs Innovations, Germany
Stefan Sp?th , Philips ADC N?rnberg, Germany
Claus Mayer , Lucent Technologies - Bell Labs Innovations, Germany
Hans Sahm , Lucent Technologies - Bell Labs Innovations, Germany
pp. 777-782

An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing (Abstract)

Majid Sarrafzadeh , Northwestern University, Evanston, IL
De-Sheng Chen , Industrial Technology Research Institute, HsinChu, Taiwan
pp. 783-788

Reducing Power Dissipation after Technology Mapping by Structural Transformations (Abstract)

Bernhard Rohfleisch , Technical University of Munich, Germany
Bernd Wurth , Synopsys, Inc., Mountain View, CA
Alfred K?lbl , Technical University of Munich, Germany
pp. 789-794

Desensitization for Power Reduction in Sequential Circuits (Abstract)

Peicheng Pan , University of Illinois at Urbana-Champaig
C. L. Liu , University of Illinois at Urbana-Champaig
Xiangfeng Chen , University of Illinois at Urbana-Champaig
pp. 795-800

Serial Fault Emulation (Abstract)

Fr?d?ric Reblewski , Meta Systems, France
Luc Burgun , Meta Systems, France
Olivier Lepape , Meta Systems, France
G?rard Fenelon , Meta Systems, France
Jean Barbier , Meta Systems, France
pp. 801-806

Partial Scan Design Based on Circuit State Information (Abstract)

Janak H. Patel , University of Illinois at Urbana-Champaign
Dong Xiang , University of Illinois at Urbana-Champaign
W. Kent Fuchs , University of Illinois at Urbana-Champaign
Srikanth Venkataraman , University of Illinois at Urbana-Champaign
pp. 807-812

Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths (Abstract)

Alex Orailoglu , University of California, San Diego
Laurence Goodby , University of California, San Diego
pp. 813-818

Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing (Abstract)

Ramesh Karri , University of Massachusetts, Amherst
Aurobindo Dasgupta , University of Massachusetts, Amherst
pp. 819-824

A Methodology for Concurrent Fabrication Process/Cell Library Optimization (Abstract)

Jay B. Brockman , University of Notre Dame
John E. Renaud , University of Notre Dame
Arun N. Lokanathan , University of Notre Dame
pp. 825-830

Computing Parametric Yield Adaptively using Local Linear Models (Abstract)

Linda Milor , University of Maryland at College Park
Mien Li , University of Maryland at College Park
pp. 831-836
103 ms
(Ver )