Proceedings of 33rd Design Automation Conference (PDF)

Package and interconnect modeling of the HFA3624, a 2.4 GHz RF to IF converter (PDF)

HEAT: hierarchical energy analysis tool (PDF)

Opportunities and obstacles in low-power system-level CAD (PDF)

POSE: power optimization and synthesis environment (PDF)

Early power exploration-a World Wide Web application [high-level design] (PDF)

Behavioral synthesis (PDF)

A register file and scheduling model for application specific processor synthesis (PDF)

Optimized code generation of multiplication-free linear transforms (PDF)

Concurrent analysis techniques for data path timing optimization (PDF)

HDL optimization using timed decision tables (PDF)

Efficient partial enumeration for timing analysis of asynchronous systems (PDF)

Verification of asynchronous circuits using time Petri net unfolding (PDF)

Methodology and tools for state encoding in asynchronous circuit synthesis (PDF)

A technique for synthesizing distributed burst-mode circuits (PDF)

Espresso-HF: a heuristic hazard-free minimizer for two-level logic (PDF)

Synthesis of hazard-free customized CMOS complex-gate networks under multiple-input changes (PDF)

Partitioning of VLSI circuits and systems (PDF)

New spectral linear placement and clustering approach (PDF)

Characterization and parameterized random generation of digital circuits (PDF)

A probability-based approach to VLSI circuit partitioning (PDF)

Verification of electronic systems (PDF)

Design considerations and tools for low-voltage digital system design (PDF)

VAMP: a VHDL based concept for accurate modeling and post layout timing simulation of electronic systems (PDF)

A systematic technique for verifying critical path delays in a 300 MHz Alpha CPU design using circuit simulation (PDF)

High-level synthesis for testability: a survey and perspective (PDF)

Introspection: a low overhead binding technique during self-diagnosing microarchitecture synthesis (PDF)

Lower bounds on test resources for scheduled data flow graphs (PDF)

Symphony: a simulation backplane for parallel mixed-mode co-simulation of VLSI systems (PDF)

Oscillation control in logic simulation using dynamic dominance graphs (PDF)

Compact vector generation for accurate power simulation (PDF)

Improving the efficiency of power simulators by input vector compaction (PDF)

Efficient communication in a design environment (PDF)

A description language for design process management (PDF)

Improved tool and data selection in task management (PDF)

Application of a Markov model to the measurement, simulation, and diagnosis of an iterative design process (PDF)

The SPICE FET models: pitfalls and prospects (Are you an educated model consumer?) (PDF)

Tutorial: design of a logic synthesis system (PDF)

On solving covering problems [logic synthesis] (PDF)

A new complete diagnosis patterns for wiring interconnects (PDF)

A satisfiability-based test generator for path delay faults in combinational circuits (PDF)

On static compaction of test sequences for synchronous sequential circuits (PDF)

An O(n) algorithm for transistor stacking with performance constraints (PDF)

Use of sensitivities and generalized substrate models in mixed-signal IC design (PDF)

RTL Emulatlon: The Next Leap In System Verification (PDF)

Equation-based behavioral model generation for nonlinear analog circuits (PDF)

Multilevel logic synthesis for arithmetic functions (PDF)

Synthesis by spectral translation using Boolean decision diagrams (PDF)

Delay minimal decomposition of multiplexers in technology mapping (PDF)

Error correction based on verification techniques (PDF)

Layout driven selecting and chaining of partial scan flip-flops (PDF)

Test point insertion: scan paths through combinational logic (PDF)

Area efficient pipelined pseudo-exhaustive testing with retiming (PDF)

Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations (PDF)

Homotopy techniques for obtaining a DC solution of large-scale MOS circuits (PDF)

Efficient AC and noise analysis of two-tone RF circuits (PDF)

Synthesis tools for Mixed-Signal ICs: progress on frontend and backend strategies (PDF)

Code generation and analysis for the functional verification of microprocessors (PDF)

Innovative verification strategy reduces design cycle time for high-end SPARC processor (PDF)

Hardware emulation for functional verification of K5 (PDF)

Functional verification methodology for the PowerPC 604 microprocessor (PDF)

I'm done simulating; now what? Verification coverage analysis and correctness checking of the DECchip 21164 Alpha microprocessor (PDF)

Glitch analysis and reduction in register transfer level power optimization (PDF)

An effective power management scheme for RTL design based on multiple clocks (PDF)

Power optimization in programmable processors and ASIC implementations of linear systems: transformation-based approach (PDF)

Scheduling techniques to enable power management (PDF)

Electromigration reliability enhancement via bus activity distribution (PDF)

A sparse image method for BEM capacitance extraction (PDF)

A parallel precorrected FFT based capacitance extraction program for signal integrity analysis (PDF)

Multipole accelerated capacitance calculation for structures with multiple dielectrics with high permittivity ratios (PDF)

Fast parameters extraction of general three-dimension interconnects using geometry independent measured equation of invariance (PDF)

Efficient full-wave electromagnetic analysis via model-order reduction of fast integral transforms (PDF)

Useful-skew clock routing with gate sizing for low power design (PDF)

Sizing of clock distribution networks for high performance CPU chips (PDF)

New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing (PDF)

Constructing lower and upper bounded delay routing trees using linear programming (PDF)

Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation (PDF)

How to write Awk and Perl scripts to enable your EDA tools to work together (PDF)

The automatic generation of functional test vectors for Rambus designs (PDF)

Functional verification methodology of Chameleon processor (PDF)

Experience in designing a large-scale multiprocessor using field-programmable devices and advanced CAD tools (PDF)

A Parallel Precorrected FFT Based Capacitance Extraction Program for Signal Integrity Analysis (Abstract)

A new hybrid methodology for power estimation (PDF)

A statistical approach to the estimation of delay-dependent switching activities in CMOS combinational circuits (PDF)

Engineering change in a non-deterministic FSM setting (PDF)

Identifying sequential redundancies without search (PDF)

A fast state reduction algorithm for incompletely specified finite state machines (PDF)

Symbolic optimization of FSM networks based on sequential ATPG techniques (PDF)

Module compaction in FPGA-based regular datapaths (PDF)

Network partitioning into tree hierarchies (PDF)

Efficient approximation algorithms for floorplan area minimization (PDF)

Optimal wire-sizing formula under the Elmore delay model (PDF)

VLSI design and system level verification for the Mini-Disc (PDF)

Design methodologies for consumer-use video signal processing LSIs (PDF)

Design methodology for analog high frequency ICs (PDF)

Issues and answers in CAD tool interoperability (PDF)

The design of mixed hardware/software systems (PDF)

Constructing application-specific heterogeneous embedded architectures from custom HW/SW applications (PDF)

A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts (PDF)

Analysis of RC interconnections under ramp input (PDF)

An AWE technique for fast printed circuit board delays (PDF)

RC-interconnect macromodels for timing simulation (PDF)

iCET: a complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips (PDF)

Techniques for verifying superscalar microprocessors (PDF)

A scalable formal verification methodology for pipelined microprocessors (PDF)

State reduction using reversible rules (PDF)

Formal verification of embedded systems based on CFSM networks (PDF)

Combined control flow dominated and data flow dominated high-level synthesis (PDF)

FADIC: architectural synthesis applied in IC design (PDF)

Domain-specific high-level modeling and synthesis for ATM switch design using VHDL (PDF)

Using register-transfer paths in code generation for heterogeneous memory-register architectures (PDF)

Address calculation for retargetable compilation and exploration of instruction-set architectures (PDF)

Analysis of operation delay and execution rate constraints for embedded systems (PDF)

Efficient software performance estimation methods for hardware/software codesign (PDF)

An explicit RC-circuit delay approximation based on the first three moments of the impulse response (PDF)

Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time (PDF)

Optimal clock skew scheduling tolerant to process variations (PDF)

An efficient equivalence checker for combinational circuits (PDF)

High performance BDD package by exploiting memory hierarchy (PDF)

Implementation of an efficient parallel BDD package (PDF)

Word level model checking-avoiding the Pentium FDIV error (PDF)

Formal verification of PowerPC arrays using symbolic trajectory evaluation (PDF)

RuleBase: an industry-oriented formal verification tool (PDF)

Bit-level analysis of an SRT divider circuit (PDF)

Integrating formal verification methods with a conventional project design flow (PDF)

A system design methodology for software/hardware co-development of telecommunication network applications (PDF)

A strategy for real-time kernel support in application-specific HW/SW embedded architectures (PDF)

Software development in a hardware simulation environment (PDF)

Compiled HW/SW co-simulation (PDF)

Stochastic sequential machine synthesis targeting constrained sequence generation (PDF)

Energy characterization based on clustering (PDF)

Architectural retiming: pipelining latency-constrained circuits (PDF)

Optimizing systems for effective block-processing: the k-delay problem (PDF)

Optimal clock period FPGA technology mapping for sequential circuits (PDF)

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design (PDF)

A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs (PDF)

New algorithms for gate sizing: a comparative study (PDF)

Post-layout optimization for deep submicron design (PDF)

Enhanced network flow algorithm for yield optimization (PDF)

Hierarchical electromigration reliability diagnosis for VLSI interconnects (PDF)

Using articulation nodes to improve the efficiency of finite-element based resistance extraction (PDF)

Extracting circuit models for large RC interconnections that are accurate up to a predefined signal frequency (PDF)

VHDL and Verilog compared and contrasted-plus modeled example written in VHDL, Verilog and C (PDF)

VHDL development system and coding standard (PDF)

An exact algorithm for low power library-specific gate re-sizing (PDF)

Reducing power dissipation after technology mapping by structural transformations (PDF)

Desensitization for power reduction in sequential circuits (PDF)

Serial fault emulation (PDF)

Partial scan design based on circuit state information (PDF)

Pseudorandom-pattern test resistance in high-performance DSP datapaths (PDF)

Hot-carrier reliability enhancement via input reordering and transistor sizing (PDF)

A methodology for concurrent fabrication process/cell library optimization (PDF)

Computing parametric yield adaptively using local linear models (PDF)

Conference Author/ Panelist Index (PDF)

Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency (Abstract)

VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C. (Abstract)

VHDL Development System and Coding Standard (Abstract)

An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing (Abstract)

Reducing Power Dissipation after Technology Mapping by Structural Transformations (Abstract)

Desensitization for Power Reduction in Sequential Circuits (Abstract)

Serial Fault Emulation (Abstract)

Partial Scan Design Based on Circuit State Information (Abstract)

Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths (Abstract)

Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing (Abstract)

A Methodology for Concurrent Fabrication Process/Cell Library Optimization (Abstract)

Computing Parametric Yield Adaptively using Local Linear Models (Abstract)