The Community for Technology Leaders
Design Automation Conference (1996)
Las Vegas, Nevada
June 3, 1996 to June 7, 1996
ISBN: 0-89791-833-9
TABLE OF CONTENTS

HEAT: hierarchical energy analysis tool (PDF)

J.H. Satyanarayana , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 9-14

Opportunities and obstacles in low-power system-level CAD (PDF)

A. Wolfe , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 15-20

POSE: power optimization and synthesis environment (PDF)

S. Iman , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 21-26

Behavioral synthesis (PDF)

R. Camposano , Synopsys Inc., Mountain View, CA, USA
pp. 33-34

A register file and scheduling model for application specific processor synthesis (PDF)

E. Ercanli , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 35-40

Concurrent analysis techniques for data path timing optimization (PDF)

C. Monahan , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 47-50

HDL optimization using timed decision tables (PDF)

Jian Li , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 51-54

Verification of asynchronous circuits using time Petri net unfolding (PDF)

A. Semenov , Dept. of Comput. Sci., Newcastle upon Tyne Univ., UK
pp. 59-62

A technique for synthesizing distributed burst-mode circuits (PDF)

P. Kudva , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 67-70

Espresso-HF: a heuristic hazard-free minimizer for two-level logic (PDF)

M. Theobald , Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
pp. 71-76

Partitioning of VLSI circuits and systems (PDF)

F.M. Johannes , Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
pp. 83-87

New spectral linear placement and clustering approach (PDF)

Jianmin Li , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 88-93

A probability-based approach to VLSI circuit partitioning (PDF)

Shantanu Dutt , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 100-105

Design considerations and tools for low-voltage digital system design (PDF)

A. Chandrakasan , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 113-118

High-level synthesis for testability: a survey and perspective (PDF)

K.D. Wagner , Synopsys Inc., Mountain View, CA, USA
pp. 131-136

Introspection: a low overhead binding technique during self-diagnosing microarchitecture synthesis (PDF)

B. Iyer , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 137-142

Lower bounds on test resources for scheduled data flow graphs (PDF)

I. Parulkar , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 143-148

Oscillation control in logic simulation using dynamic dominance graphs (PDF)

P. Dahlgren , Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
pp. 155-160

Compact vector generation for accurate power simulation (PDF)

Shi-yu Huang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 161-164

Improving the efficiency of power simulators by input vector compaction (PDF)

Chi-ying Tsui , Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong
pp. 165-168

A description language for design process management (PDF)

P.R. Sutton , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 175-180

Improved tool and data selection in task management (PDF)

J.W. Hagerman , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 181-184

Tutorial: design of a logic synthesis system (PDF)

R. Rudell , Synopsys Inc., Mountain View, CA, USA
pp. 191-196

On solving covering problems [logic synthesis] (PDF)

O. Coudert , Synopsys Inc., Mountain View, CA, USA
pp. 197-202

A new complete diagnosis patterns for wiring interconnects (PDF)

Sungju Park , Dept. of Comput. Sci. & Eng., Hanyang Univ., Ansan, South Korea
pp. 203-208

A satisfiability-based test generator for path delay faults in combinational circuits (PDF)

Chih-Ang Chen , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 209-214

On static compaction of test sequences for synchronous sequential circuits (PDF)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 215-220

An O(n) algorithm for transistor stacking with performance constraints (PDF)

B. Basaran , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 221-226

Equation-based behavioral model generation for nonlinear analog circuits (PDF)

C. Borchers , Inst. of Microelectron. Syst., Hannover Univ., Germany
pp. 236-239

Multilevel logic synthesis for arithmetic functions (PDF)

Chien-Chung Tsai , Mentor Graphics Corp., Wilsonville, OR, USA
pp. 242-247

Synthesis by spectral translation using Boolean decision diagrams (PDF)

J.P. Hansen , Toshiba ULSI Res. Labs., Kawasaki, Japan
pp. 248-253

Error correction based on verification techniques (PDF)

Shi-Yu Huang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 258-261

Area efficient pipelined pseudo-exhaustive testing with retiming (PDF)

Huoy-Yu Liu , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 274-279

Efficient AC and noise analysis of two-tone RF circuits (PDF)

R. Telichevesky , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 292-297

Synthesis tools for Mixed-Signal ICs: progress on frontend and backend strategies (PDF)

L.R. Carley , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 298-303

An effective power management scheme for RTL design based on multiple clocks (PDF)

C. Papachristou , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 337-342

Scheduling techniques to enable power management (PDF)

J. Monteiro , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 349-352

Electromigration reliability enhancement via bus activity distribution (PDF)

A. Dasgupta , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 353-356

Useful-skew clock routing with gate sizing for low power design (PDF)

J.G. Xi , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 383-388

Constructing lower and upper bounded delay routing trees using linear programming (PDF)

Jaewon Oh , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 401-404
Papers

A Parallel Precorrected FFT Based Capacitance Extraction Program for Signal Integrity Analysis (Abstract)

N. R. Aluru , Massachusetts Institute of Technology, Cambridge, MA
V. B. Nadkarni , Massachusetts Institute of Technology, Cambridge, MA
J. White , Massachusetts Institute of Technology, Cambridge, MA
pp. 363-366

Engineering change in a non-deterministic FSM setting (PDF)

S.P. Khatri , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 451-456

Identifying sequential redundancies without search (PDF)

M.A. Iyer , Synopsys Inc., Mountain View, CA, USA
pp. 457-462

Module compaction in FPGA-based regular datapaths (PDF)

A. Koch , Dept. for Integrated Circuit Design, Tech. Univ. Braunschweig, Germany
pp. 471-476

Network partitioning into tree hierarchies (PDF)

Ming-Ter Kuo , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 477-482

Efficient approximation algorithms for floorplan area minimization (PDF)

D.Z. Chen , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 483-486

Optimal wire-sizing formula under the Elmore delay model (PDF)

Chung-Ping Chen , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 487-490

Design methodologies for consumer-use video signal processing LSIs (PDF)

H. Edamatsu , Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Moriguchi, Japan
pp. 497-502

Design methodology for analog high frequency ICs (PDF)

Y. Miyahara , Multi Media Eng. Lab., Toshiba Corp., Yokohama, Japan
pp. 503-508

The design of mixed hardware/software systems (PDF)

J.K. Adams , Synopsys Inc., Mountain View, CA, USA
pp. 515-520

Analysis of RC interconnections under ramp input (PDF)

A.B. Kahng , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 533-538

An AWE technique for fast printed circuit board delays (PDF)

B. Sheehan , Syst. on Board Div., Mentor Graphics, San Jose, CA, USA
pp. 539-543

RC-interconnect macromodels for timing simulation (PDF)

F. Dartu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 544-547

Techniques for verifying superscalar microprocessors (PDF)

J.R. Burch , Cadence Berkeley Lab., USA
pp. 552-557

A scalable formal verification methodology for pipelined microprocessors (PDF)

J. Levitt , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 558-563

State reduction using reversible rules (PDF)

C.N. Ip , Dept. of Comput. Sci., Stanford Univ., CA, USA
pp. 564-567

FADIC: architectural synthesis applied in IC design (PDF)

J. Huisken , Philips Res. Lab., Eindhoven, Netherlands
pp. 579-584

Analysis of operation delay and execution rate constraints for embedded systems (PDF)

R.K. Gupta , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 601-604

Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time (PDF)

V. Chandramouli , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 617-622

Optimal clock skew scheduling tolerant to process variations (PDF)

J.L. Neves , Dept. of Electr. Eng., Rochester Univ., NY, USA
pp. 623-628

An efficient equivalence checker for combinational circuits (PDF)

Y. Matsunaga , Fujitsu Labs. Ltd., Kawasaki, Japan
pp. 629-634

High performance BDD package by exploiting memory hierarchy (PDF)

J.V. Sanghavi , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 635-640

Implementation of an efficient parallel BDD package (PDF)

T. Stornetta , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 641-644

Word level model checking-avoiding the Pentium FDIV error (PDF)

E.M. Clarke , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 645-648

Formal verification of PowerPC arrays using symbolic trajectory evaluation (PDF)

M. Pandey , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 649-654

RuleBase: an industry-oriented formal verification tool (PDF)

I. Beer , IBM Israel Sci. & Technol. Center, Haifa, Israel
pp. 655-660

Bit-level analysis of an SRT divider circuit (PDF)

R.E. Bryant , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 661-665

Integrating formal verification methods with a conventional project design flow (PDF)

A.T. Eiriksson , Silicon Graphics Comput. Syst., Mountain View, CA, USA
pp. 666-671

Software development in a hardware simulation environment (PDF)

B. Schnaider , MayaLee Consulting, Santa Clara, CA, USA
pp. 684-689

Compiled HW/SW co-simulation (PDF)

V. Zivojnovic , Integrated Syst. for Signal Process., Aachen Univ. of Technol., Germany
pp. 690-695

Stochastic sequential machine synthesis targeting constrained sequence generation (PDF)

D. Marculescu , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 696-701

Energy characterization based on clustering (PDF)

H. Mehta , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 702-707

Architectural retiming: pipelining latency-constrained circuits (PDF)

S. Hassoun , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 708-713

Optimal clock period FPGA technology mapping for sequential circuits (PDF)

Peichen Pan , Dept. of Electr. & Comput. Eng., Clarkson Univ., Potsdam, NY, USA
pp. 720-725

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design (PDF)

J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 726-729

A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs (PDF)

C. Legl , Inst. of Electron. Design Automation, Tech. Univ. Munchen, Germany
pp. 730-733

New algorithms for gate sizing: a comparative study (PDF)

O. Coudert , Synopsys Inc., Mountain View, CA, USA
pp. 734-739

Post-layout optimization for deep submicron design (PDF)

K. Sato , Advanced CAD Dev. Lab., NEC Corp., Kawasaki, Japan
pp. 740-745

Enhanced network flow algorithm for yield optimization (PDF)

C. Bamji , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 746-751

VHDL development system and coding standard (PDF)

H. Sahm , Lucent Technols.-Bell Labs. Innovations, Nurnberg, Germany
pp. 777-782

An exact algorithm for low power library-specific gate re-sizing (PDF)

De-Sheng Chen , Electron. Res. & Service Org., Ind. Technol. Res. Inst., Hsinchu, Taiwan
pp. 783-788

Reducing power dissipation after technology mapping by structural transformations (PDF)

B. Rohfleisch , Inst. of Electronic Design Automation, Tech. Univ. Munchen, Germany
pp. 789-794

Desensitization for power reduction in sequential circuits (PDF)

Xiangfeng Chen , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 795-800

Serial fault emulation (PDF)

L. Burgun , META Syst., Saclay, France
pp. 801-806

Partial scan design based on circuit state information (PDF)

Dong Xiang , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 807-812

Pseudorandom-pattern test resistance in high-performance DSP datapaths (PDF)

L. Goodby , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 813-818

Hot-carrier reliability enhancement via input reordering and transistor sizing (PDF)

A. Dasgupta , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 819-824

A methodology for concurrent fabrication process/cell library optimization (PDF)

A.N. Lokanathan , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 825-830

Computing parametric yield adaptively using local linear models (PDF)

Mien Li , Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
pp. 831-836
Papers

Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency (Abstract)

P. J. H. Elias , Delft University of Technology, The Netherlands
N. P. van der Meijs , Delft University of Technology, The Netherlands
pp. 764-769

VHDL Development System and Coding Standard (Abstract)

Hans Sahm , Lucent Technologies - Bell Labs Innovations, Germany
Claus Mayer , Lucent Technologies - Bell Labs Innovations, Germany
J?rg Pleickhardt , Lucent Technologies - Bell Labs Innovations, Germany
Johannes Schuck , Lucent Technologies - Bell Labs Innovations, Germany
Stefan Sp?th , Philips ADC N?rnberg, Germany
pp. 777-782

An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing (Abstract)

De-Sheng Chen , Industrial Technology Research Institute, HsinChu, Taiwan
Majid Sarrafzadeh , Northwestern University, Evanston, IL
pp. 783-788

Reducing Power Dissipation after Technology Mapping by Structural Transformations (Abstract)

Bernhard Rohfleisch , Technical University of Munich, Germany
Alfred K?lbl , Technical University of Munich, Germany
Bernd Wurth , Synopsys, Inc., Mountain View, CA
pp. 789-794

Desensitization for Power Reduction in Sequential Circuits (Abstract)

Xiangfeng Chen , University of Illinois at Urbana-Champaig
Peicheng Pan , University of Illinois at Urbana-Champaig
C. L. Liu , University of Illinois at Urbana-Champaig
pp. 795-800

Serial Fault Emulation (Abstract)

Luc Burgun , Meta Systems, France
Fr?d?ric Reblewski , Meta Systems, France
G?rard Fenelon , Meta Systems, France
Jean Barbier , Meta Systems, France
Olivier Lepape , Meta Systems, France
pp. 801-806

Partial Scan Design Based on Circuit State Information (Abstract)

Dong Xiang , University of Illinois at Urbana-Champaign
Srikanth Venkataraman , University of Illinois at Urbana-Champaign
W. Kent Fuchs , University of Illinois at Urbana-Champaign
Janak H. Patel , University of Illinois at Urbana-Champaign
pp. 807-812

Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths (Abstract)

Laurence Goodby , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 813-818

Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing (Abstract)

Aurobindo Dasgupta , University of Massachusetts, Amherst
Ramesh Karri , University of Massachusetts, Amherst
pp. 819-824

A Methodology for Concurrent Fabrication Process/Cell Library Optimization (Abstract)

Arun N. Lokanathan , University of Notre Dame
Jay B. Brockman , University of Notre Dame
John E. Renaud , University of Notre Dame
pp. 825-830

Computing Parametric Yield Adaptively using Local Linear Models (Abstract)

Mien Li , University of Maryland at College Park
Linda Milor , University of Maryland at College Park
pp. 831-836
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