The Community for Technology Leaders
32nd Design Automation Conference (1995)
San Francisco, CA
June 12, 1995 to June 16, 1995
ISSN: 0738-100X
ISBN: 0-89791-725-1
TABLE OF CONTENTS

Awards pages (PDF)

pp. vii

Call for papers (PDF)

pp. viii

Reviewers (PDF)

pp. x-xii

1995 Keynote Address (PDF)

A. Richard Newton , Dept. of EE & CS, Univ. of California at Berkeley, Berke;ey, CA
pp. xiii

Table of contents (PDF)

pp. xiv-xxiv

System Design Methodology of UltraSPARC ™ -I (PDF)

Lawrence Yang , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
pp. 7-12

UltraSPARC ™ -I Emulation (PDF)

James Gateley , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
pp. 13-18

CAD Methodology for the Design of UltraSPARC ™-I Microprocessor at Sun Microsystems Inc. (PDF)

A. Cao , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
pp. 19-22

Computing the Maximum Power Cycles of a Sequential Circuit (PDF)

Srilatha Manne , University of Colorado, Dept. of Electrical and Computer Engineering, Boulder, CO
pp. 23-28

Register Allocation and Binding for Low Power (PDF)

Massoud Pedram Jui-Ming Chang , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA
pp. 29-35

Memory Segmentation to Exploit Sleep Mode Operation (PDF)

Gustavo E. Tellez Amir H. Farrahi , Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL
pp. 36-41

Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level (Abstract)

John P. Knight Raul San Martin , Department of Electronics, Carleton University, Ottawa, Ontario, Canada
pp. 42-47

Boolean Matching for Incompletely Specified Functions (PDF)

TingTing Hwang Kuo-Hua Wang , Department of Computer Science and Information Engineering, National Chiao Tung University, HsinChu, Taiwan
pp. 48-53

Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm (PDF)

Klaus Eckl Bernd Wurth , Institute of Electronic Design Automation, Technical University of Munich, Munich, Germany
pp. 54-59

A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis (Abstract)

Carl Sechen Ted Stanion , Department of Electrical Engineering, University of Washington
pp. 60-64

Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping (PDF)

Juinn-Dar Huang Wen-Zen Shen , Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, the Republic of China
pp. 65-69

Minimizing the Routing Cost During Logic Extraction (PDF)

Massoud Pedram Hirendu Vaishnav , Department of EE - Systems, University of Southern California, Los Angeles, CA
pp. 70-75

Requirements-Based Design Evaluation (PDF)

Steven P. Levitan Stephen T. Frezza , Dept. of Electrical Engineering, University of Pittsburgh
pp. 76-81

Incorporating Design Schedule Management into a Flow Management System (PDF)

Jay B. Brockman Eric W. Johnson , Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN
pp. 82-87

Generating ECAD Framework Code from Abstract Models (PDF)

Bernd Schurmann Joachim Altmeyer , University of Kaiserslautern, Kaiserslautern, Germany
pp. 88-93

Panel: Managing Design Change - Lessons Learned (PDF)

Donald Reinertsen , Reinertsen & Associates, Redondo Beach, CA
pp. 100

Scheduling Using Behavioral Templates (PDF)

Tai Ly , Synopsys Inc., Mountain View, CA
pp. 101-106

Fast Identification of Robust Dependent Path Delay Faults (Abstract)

U. Sparmann , Computer Science Dept., University of Saarland, Saarbrucken, Germany
pp. 119-125

On Synthesis-for-Testability of Combinational Logic Circuits (Abstract)

Sudhakar M. Reddy Irith Pomeranz , Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA
pp. 126-132

Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits using Compact Lists (Abstract)

Srikanth Venkataraman , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
pp. 133-138

Parallel Logic Simulation of VLSI Systems (PDF)

Roger D. Chamberlain , Computer and Communications Research Center, Department of Electrical Engineering, Washington University, St. Louis, MO
pp. 139-143

A General Method for Compiling Event-Driven Simulations (PDF)

Robert S. French , Computer Systems Laboratory, Stanford University, CA
pp. 151-156

Panel: Power Minimization in IC Design (PDF)

Massoud Pedram , Univ. of Southern California, Los Angeles, CA
pp. 157

A Transformation-Based Approach for Storage Optimization (PDF)

Youn-Long Lin Wei-Kai Cheng , Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan, R.O.C.
pp. 158-163

Register Minimization beyond Sharing among Variables (PDF)

Youn-Long Lin Tsung-Yi Wu , Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan, R.O.C.
pp. 164-169

Constrained Register Allocation in Bus Architectures (PDF)

Salil Raje Elof Frank , German National Research Center for Computer Science (GMD), St. Augustin, Germany
pp. 170-175

On Test Set Preservation of Retimed Circuits (Abstract)

Aiman El-Maleh , MACS Laboratory, McGill University, Montreal, Canada
pp. 176-182

Partial Scan with Pre-selected Scan Signals (PDF)

C.L. Liu Peichen Pan , Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 189-194

Spectral Partitioning: The More Eigenvectors, The Better (PDF)

So-Zen Yao Charles J. Alpert , UCLA Computer Science Department, Los Angeles, CA
pp. 195-200

Multi-way Partitioning For Minimum Delay For Look-Up Table Based FPGAs (PDF)

Donald Thomas Prashant Sawkar , Electrical and Computer Engineering Dept., Carnegie-Mellon University, Pittsburgh, PA
pp. 201-205

Performance-Driven Partitioning Using a Replication Graph Approach (PDF)

Lung-Tien Liu , Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA
pp. 206-210

Timing Driven Placement for Large Standard Cell Circuits (PDF)

Carl Sechen William Swartz , TimberWolf Systems, Inc., Dallas, TX
pp. 211-215

Quantified Suboptimality of VLSI Layout Heuristics (PDF)

Dennis J.-H. Huang Lars W. Hagen , Cadence Design Systems, Inc., San Jose, CA
pp. 216-221

Digital Receiver Design Using VHDL Generation From Data Flow Graphs (Abstract)

Thorsten Grotker Peter Zepter , Integrated Systems for Signal Processing, Aachen University of Technology, Aachen, Germany
pp. 228-233

Panel: University-Industry Ties: How Can They Be Improved? (PDF)

Randal E. Bryant , Carnegie Mellon Univ., Pittsburgh, PA
pp. 241

A Survey of Optimization Techniques Targeting Low Power VLSI Circuits (PDF)

Sharad Malik Srinivas Devadas , Massachusetts Institute of Technology, Department of EECS
pp. 242-247

Logic Extraction and Factorization for Low Power (PDF)

Massoud Pedram Sasan Iman , Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
pp. 248-253

Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool (PDF)

Luciano Lavagno , Cadence Berkeley Laboratories, Berkeley, CA
pp. 254-260

The Aurora RAM Compiler (Abstract)

Ajay Chandna , University of Michigan, Department of Electrical Engineering & Computer Science, Ann Arbor, MI
pp. 261-266

Automatic Layout Synthesis of Leaf Cells (PDF)

J. Donald Trotter Sanjay Rekhi , Microsystems Prototyping Laboratory, NSF Engineering Research Center, Mississippi State University, Starkville, MS
pp. 267-272

Delayed Frontal Solution for Finite-Element based Resistance Extraction (Abstract)

A.J. van Genderen N.P. van der Meijs , Delft University of Technology, Department of Electrical Engineering, Delft, The Netherlands
pp. 273-278

Test Program Generation for Functional Verification of PowePC Processors in IBM (PDF)

Aharon Aharon , IBM Israel - Haifa Research Lab, IBM AS/400 Division, Rochester, MN
pp. 279-285

Design-Flow and Synthesis for ASICs: A Case Study (PDF)

Massimo Bombana , ITALTEL SIT - Settimo Milanese, Italy
pp. 292-297

Model Checking in Industrial Hardware Design (Abstract)

Jorg Bormann , Siemens Corporate R&D, Munich, Germany
pp. 298-303

DelaY: An Efficient Tool for Retiming with Realistic Delay Modeling (PDF)

Marios C. Papaefthymiou Kumar N. Lalgudi , Department of Electrical Engineering, Yale University, New Haven, CT
pp. 304-309

A Fresh Look at Retiming via Clock Skew Optimization (PDF)

Sachin S. Sapatnekar Rahul B. Deokar , Department of Electrical and Computer Engineering, Iowa State University, Ames, IA
pp. 310-315

The Validity of Retiming Sequential Circuits (PDF)

Vigyan Singhal , Department of EECS, University of California at Berkeley, Berkeley, CA
pp. 316-321

Retiming Synchronous Circuitry with Imprecise Delays (Abstract)

R.H.J.M. Otten I. Karkowski , Delft University of Technology, Faculty of Electrical Engineering, Delft, The Netherlands
pp. 322-326

A Fast State Assignment Procedure for Large FSMs (PDF)

Massoud Pedram Shihming Liu , Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
pp. 327-332

Software Accelerated Functional Fault Simulation for Data-Path Architectures (Abstract)

M. Kassab , Microelectronics and Computer Systems Laboratory, McGill University, Montreal, Canada
pp. 333-338

Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy (Abstract)

B. Becker R. Krieger , Computer Science Department, J.W. Goethe-University, Frankfurt am Main, Germany
pp. 339-344

Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks (PDF)

F. Joel Ferguson Haluk Konuk , Computer Engineering Board of Studies, University of California at Santa Cruz
pp. 345-351

Analysis of Switch-Level Faults by Symbolic Simulation (Abstract)

Jordi Carrabina-Bordoll Lluis Ribas-Xirgo , Centre Nacional de Microelectronica, CNM (CSIC), Universitat Autonoma de Barcelona, UAB, Campus UAB, Bellaterra, Barcelona, Spain
pp. 352-357

Transmission Line Synthesis (PDF)

Byron Krauter , The University of Texas at Austin, Department of Electrical and Computer Engineering, Austin, TX
pp. 358-363

The Elmore Delay as a Bound for RC Trees with Generalized Input Signals (PDF)

Rohini Gupta , The University of Texas at Austin, Department of Electrical and Computer Engineering, Austin, TX
pp. 364-369

Delay Analysis of the Distributed RC Line (PDF)

Vasant B. Rao , IBM EDA Laboratory, Hopewell Junction, NY
pp. 370-375

Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances associated with 3-D Interconnect Structures (PDF)

Mattan Kamon L. Miguel Silveira , Research Laboratory of Electronics, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA
pp. 376-380

Tutorial: ASIC Prototyping (PDF)

Gabriele Saucier , Inst. National Polytech de Grenoble/CSI, Grenoble, France
pp. 388

Symbolic Modeling and Evaluation of Data Paths (PDF)

Forrest Brewer Chuck Monahan , Department of Electrical and Computer Engineering, University of California, Santa Barbara
pp. 389-394

Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead (Abstract)

Sandeep Gupta Ishwar Parulkar , Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
pp. 395-401

Deriving Efficient Area and Delay Estimates by Modeling Layout Tools (PDF)

Dorothy E. Setliff Donald S. Gelosh , Department of Electrical Engineering, University of Pittsburgh, Pittsburgh, PA
pp. 402-407

Efficient OBDD-Based Boolean Manipulation in CAD Beyond Current Limits (PDF)

Christoph Meinel Jochen Bern , FB IV - Informatik, Universitat Trier, Trier, Germany
pp. 408-413

Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment (PDF)

Wolfgang Kunz Subodh M. Reddy , Laboratory for Digital and Computer Systems Research, Department of Computer Science, Texas A&M University, College Station, TX
pp. 414-419

Advanced Verification Techniques Based on Learning (PDF)

Rajarshi Mukherjee Jawahar Jain , Fujitsu Laboratories of America, San Jose CA
pp. 420-426

Efficient Generation of Counterexamples and Witnesses in Symbolic Model Checking (PDF)

E.M. Clarke , School of Computer Science, Carnegie Mellon University, Pittsburgh, PA
pp. 427-432

DARWIN: CMOS opamp Synthesis by Means of a Genetic Algorithm (Abstract)

Domine Leenaerts Wim Kruiskamp , Eindhoven University of Technology, Faculty of Electrical Engineering, Eindhoven, the Netherlands
pp. 433-438

Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels (PDF)

Andrew T. Yang Ivan L. Wemple , Department of Electrical Engineering, University of Washington
pp. 439-444

Direct Performance-Driven Placement of Mismatch-sensitive Analog Circuits (Abstract)

G. Gielen K. Lampaert , Katholieke Universiteit Leuven, Dep. Elektrotechniek, ESAT-MICAS, Heverlee, Belgium
pp. 445-449

System-Level Design for Test of Fully Differential Analog Circuits (PDF)

Ramesh Harjani Bapiraju Vinnakota , Department of Electrical Engineering, University of Minnesota, Minneapolis, MN
pp. 450-454

Performance Analysis of Embedded Software Using Implicit Path Enumeration (PDF)

Sharad Malik Yau-Tsun Steven Li , Department of Electrical Engineering, Princeton University, NJ
pp. 456-461

Interval Scheduling: Fine-Grained Code Scheduling for Embedded Systems (PDF)

Gaetano Borriello Pai Chou , Department of Computer Science and Engineering, University of Washington, Seattle, WA
pp. 462-467

Transient Simulations of Three-dimensional Integrated Circuit Interconnect Using a Mixed Surface-Volume approach (PDF)

Tom Korsmeyer Mike Chou , Department of EECS, Massachusetts Institute of Technology, Cambridge, MA
pp. 485-490

Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution (PDF)

W.-M. Dai Joe G. Xi , Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA
pp. 491-496

Power Optimal Buffered Clock Tree Design (PDF)

Malgorzata Marek-Sadowska Ashok Vittal , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA
pp. 497-502

Power Distribution Topology Design (PDF)

Malgorzata Marek-Sadowska Ashok Vittal , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA
pp. 503-507

On the Bounded-Skew Clock and Steiner Routing Problems (PDF)

Andrew B. Kahng Dennis J.-H. Huang , UCLA Computer Science Dept., Los Angeles, CA
pp. 508-513

Benchmarking An Interdisciplinary Concurrent Design Methodology for Electronic/Mechanical Systems (Abstract)

Asim Smailagic , Engineering Design Research Center, Carnegie Mellon University, Pittsburgh, PA
pp. 514-519

A Methodology for HW-SW Codesign in ATM (PDF)

Dave Yurach Giovanni Mancini , Bell-Northern Research, Ottawa, Ontario, Canada
pp. 520-527

Panel: The ESDA Landscape: Who Will Dominate? (PDF)

Kurt Keutzer , Synopsys, Inc., Mountain View, CA
pp. 534

Residue BDD and Its Application to the Verification of Arithmetic Circuits (PDF)

Shinji Kimura , Graduate School of Information Science, Nara Institute of Science and Technology, Nara, JAPAN
pp. 542-545

Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions (PDF)

Wayne Burleson Zheng Zhou , Department of Electronic & Computer Engineering, University of Massachusetts at Amherst, MA
pp. 546-551

On Optimal Board-Level Routing for FPGA-based Logic Emulation (PDF)

D.F. Wong Wai-Kei Mak , Department of Computer Sciences, University of Texas at Austin, Austin, TX
pp. 552-556

A Performance and Routability Driven Router for FPGAs Considering Path Delays (PDF)

Allen C.-H. Wu Yuh-Sheng Lee , Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan, R.O.C.
pp. 557-561

New Performance-Driven FPGA Routing Algorithms (PDF)

Gabriel Robins Michael J. Alexander , Department of Computer Science, University of Virginia, Charlottesville, VA
pp. 562-567

Effects of FPGA Architecture on FPGA Routing (PDF)

Stephen Trimberger , Xilinx, Inc., San Jose, CA
pp. 574-578

The Case for Design Using the World Wide Web (PDF)

Randy H. Katz Mario J. Silva , Computer Science Division, University of California, Berkeley, Berkeley CA
pp. 579-585

Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores (PDF)

Adwin H. Timmer , Eindhoven University of Technology, Department of Electrical Engineering, Design Automation Section, Eindhoven, The Netherlands and Philips Research Laboratories, Eindhoven, The Netherlands
pp. 593-598

Code Optimization Techniques for Embedded DSP Microprocessors (PDF)

Stan Liao , MIT Department of EECS, Cambridge, MA
pp. 599-604

Retargetable Self-Test Program Generation Using Constraint Logic Programming (PDF)

Peter Marwedel Ulrich Bieker , University of Dortmund, Department of Computer Science, Dortmund, Germany
pp. 605-611

Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits (PDF)

Farid N. Najm , ECE Dept. and Coordinated Science Lab., University of Illinois at Urbana-Champaign, Urbana, IL
pp. 612-617

Accurate Estimation of Combinational Circuit Activity (PDF)

Huzefa Mehta , Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA
pp. 618-622

Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuitsy (PDF)

Michael Y. Zhang Farid N. Najm , ECE Dept. and Coordinated Science Lab., University of Illinois at Urbana-Champaign, Urbana, IL
pp. 623-627

Efficient Power Estimation for Highly Correlated Input Streams (Abstract)

Diana Marculescu Radu Marculescu , Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
pp. 628-634

Power Estimation in Sequential Circuitsy (PDF)

Shashank Goel Farid N. Najm , ECE Dept. and Coordinated Science Lab., University of Illinois at Urbana-Champaign, Urbana, IL
pp. 635-640

Logic Synthesis for Engineering Change (PDF)

Chih-chang Lin , University of California, Santa Barbara
pp. 647-652

Multi-Level Logic Minimization based on Multi-Signal Implications (PDF)

Masayuki Yuguchi , C&C Research Laboratories, NEC Corporation, Kawasaki, Japan
pp. 658-662

Logic Clause Analysis for Delay Optimization (PDF)

Bernd Wurth Bernhard Rohfleisch , Institute of Electronic Design Automation, Technical University of Munich, Munich, Germany
pp. 668-672

Panel: Deep Submicron Design Challenges (PDF)

Mike Smith , Compass Design Automation, San Jose, CA
pp. 673

Productivity Issues in High-Level Design: Are Tools Solving the Real Problems? (PDF)

Reinaldo A. Bergamaschi , IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 674-677

Information Models of VHDL (PDF)

Hilary J Kahn Cristian A Giumale , Department of Computer Science, Technical University of Bucharest, Bucharest, Romania
pp. 678-683

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization (Abstract)

Satyamurthy Pullela Noel Menezes , Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
pp. 690-695

An Algorithm for Incremental Timing Analysis (PDF)

Donald T. Tang Jin-fuw Lee , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 696-701

Automatic Clock Abstraction from Sequential Circuits (PDF)

Randal E. Bryant Samir Jain , Digital Equipment Corporation, Hudson, MA
pp. 707-711
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