The Community for Technology Leaders
32nd Design Automation Conference (1995)
San Francisco, CA
June 12, 1995 to June 16, 1995
ISSN: 0738-100X
ISBN: 0-89791-725-1
TABLE OF CONTENTS

Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level (Abstract)

John P. Knight Raul San Martin , Department of Electronics, Carleton University, Ottawa, Ontario, Canada
pp. 42-47

A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis (Abstract)

Carl Sechen Ted Stanion , Department of Electrical Engineering, University of Washington
pp. 60-64

Fast Identification of Robust Dependent Path Delay Faults (Abstract)

U. Sparmann , Computer Science Dept., University of Saarland, Saarbrucken, Germany
pp. 119-125

On Synthesis-for-Testability of Combinational Logic Circuits (Abstract)

Sudhakar M. Reddy Irith Pomeranz , Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA
pp. 126-132

Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits using Compact Lists (Abstract)

Srikanth Venkataraman , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
pp. 133-138

On Test Set Preservation of Retimed Circuits (Abstract)

Aiman El-Maleh , MACS Laboratory, McGill University, Montreal, Canada
pp. 176-182

Digital Receiver Design Using VHDL Generation From Data Flow Graphs (Abstract)

Thorsten Grotker Peter Zepter , Integrated Systems for Signal Processing, Aachen University of Technology, Aachen, Germany
pp. 228-233

The Aurora RAM Compiler (Abstract)

Ajay Chandna , University of Michigan, Department of Electrical Engineering & Computer Science, Ann Arbor, MI
pp. 261-266

Delayed Frontal Solution for Finite-Element based Resistance Extraction (Abstract)

A.J. van Genderen N.P. van der Meijs , Delft University of Technology, Department of Electrical Engineering, Delft, The Netherlands
pp. 273-278

Model Checking in Industrial Hardware Design (Abstract)

Jorg Bormann , Siemens Corporate R&D, Munich, Germany
pp. 298-303

Retiming Synchronous Circuitry with Imprecise Delays (Abstract)

R.H.J.M. Otten I. Karkowski , Delft University of Technology, Faculty of Electrical Engineering, Delft, The Netherlands
pp. 322-326

Software Accelerated Functional Fault Simulation for Data-Path Architectures (Abstract)

M. Kassab , Microelectronics and Computer Systems Laboratory, McGill University, Montreal, Canada
pp. 333-338

Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy (Abstract)

B. Becker R. Krieger , Computer Science Department, J.W. Goethe-University, Frankfurt am Main, Germany
pp. 339-344

Analysis of Switch-Level Faults by Symbolic Simulation (Abstract)

Jordi Carrabina-Bordoll Lluis Ribas-Xirgo , Centre Nacional de Microelectronica, CNM (CSIC), Universitat Autonoma de Barcelona, UAB, Campus UAB, Bellaterra, Barcelona, Spain
pp. 352-357

Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead (Abstract)

Sandeep Gupta Ishwar Parulkar , Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
pp. 395-401

DARWIN: CMOS opamp Synthesis by Means of a Genetic Algorithm (Abstract)

Domine Leenaerts Wim Kruiskamp , Eindhoven University of Technology, Faculty of Electrical Engineering, Eindhoven, the Netherlands
pp. 433-438

Direct Performance-Driven Placement of Mismatch-sensitive Analog Circuits (Abstract)

G. Gielen K. Lampaert , Katholieke Universiteit Leuven, Dep. Elektrotechniek, ESAT-MICAS, Heverlee, Belgium
pp. 445-449

Benchmarking An Interdisciplinary Concurrent Design Methodology for Electronic/Mechanical Systems (Abstract)

Asim Smailagic , Engineering Design Research Center, Carnegie Mellon University, Pittsburgh, PA
pp. 514-519

Efficient Power Estimation for Highly Correlated Input Streams (Abstract)

Diana Marculescu Radu Marculescu , Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
pp. 628-634

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization (Abstract)

Satyamurthy Pullela Noel Menezes , Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
pp. 690-695
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