The Community for Technology Leaders
Design Automation Conference (1995)
San Francisco, California, United States
June 12, 1995 to June 16, 1995
ISBN: 0-89791-725-1
TABLE OF CONTENTS
Papers

A Fast and Flexible Performance Simulator for Micro-Architecture Trade-Off Analysis on UltraSPARC-I (Abstract)

Atsushi Inoue , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
Les Kohn , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
Guillermo Maturana , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
Marc Tremblay , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
pp. 2-6

System Design Methodology of UltraSPARC-I (Abstract)

David Gao , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
Raju Joshi , Sun Microsystems, Inc., Mountain View, CA
Lawrence Yang , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
Jamshid Mostoufi , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
Paul Loewenstein , Sun Microsystems, Inc., Mountain View, CA
pp. 7-12

UltraSPARC-I (Abstract)

Scott Cooke , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
Dale Greenley , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
Piyush Desai , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
James Gateley , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
Tim Goldsbury , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
Dennis Chen , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
Manjunath Doreswamy , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
Mark Elgood , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
Gary Feierbach , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
Miriam Blatt , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
pp. 13-18

CAD Methodology for the Design of UltraSPARC-I Microprocessor at Sun Microsystems Inc. (Abstract)

P. Dedood , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
M. Wong , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
M. Dell'OcaKhouja , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
P. Delisle , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
P. Patel , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
T. Doan , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
J. MaDonald , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
S. Mitra , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
N. Ross , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
W. Vercruysse , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
R. Sunder , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
S. Simovich , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
D. Greenhill , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
B. Sur , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
J. Irwin , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
R. Yu , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
M. Doreswamy , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
J. Zhou , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
O. Geva , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
S. Rozanski , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
J. Bauman , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
P. Yip , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
M. Ma , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
A. Adalal , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
S. Gopaladhine , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
P. Saggurti , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
R. Puranik , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
L. Lev , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
P. Donehue , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
A. Cao , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
G. Zyner , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
A. Prabhu , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
P. Ferolito , SPARC Technology, Sun Microsystems, Inc., Mountain View, CA
pp. 19-22

Computing the Maximum Power Cycles of a Sequential Circuit (Abstract)

Abelardo Pardo , University of Colorado, Boulder
Gary D. Hachtel , University of Colorado, Boulder
Srilatha Manne , University of Colorado, Boulder
Enrico Macii , Politecnico di Torino, Italy
R. Iris Bahar , University of Colorado, Boulder
Massimo Poncino , Politecnico di Torino, Italy
Fabio Somenzi , University of Colorado, Boulder
pp. 23-28

Register Allocation and Binding for Low Power (Abstract)

Massoud Pedram , University of Southern California, Los Angeles
Jui-Ming Chang , University of Southern California, Los Angeles
pp. 29-35

Memory Segmentation to Exploit Sleep Mode Operation (Abstract)

Amir H. Farrahi , Northwestern University, Evanston, IL
Majid Sarrafzadeh , Northwestern University, Evanston, IL
Gustavo E. T?llez , Northwestern University, Evanston, IL
pp. 36-41

Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level (Abstract)

Raul San Martin , Carleton University, Ontario, Canada
John P. Knight , Carleton University, Ontario, Canada
pp. 42-47

Boolean Matching for Incompletely Specified Functions (Abstract)

Ting-Ting Hwang , National Chiao Tung University, Taiwan
Kuo-Hua Wang , National Tsing Hua University, Taiwan
pp. 48-53

Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm (Abstract)

Klaus Eckl , Technical University of Munich, Germany
Kurt Antreich , Technical University of Munich, Germany
Bernd Wurth , Technical University of Munich, Germany
pp. 54-59

Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping (Abstract)

Juinn-Dar Huang , National Chiao Tung University, Taiwan
Shih-Min Chao , National Chiao Tung University, Taiwan
Wen-Zen Shen , National Chiao Tung University, Taiwan
pp. 65-69

Minimizing the Routing Cost during Logic Extraction (Abstract)

Hirendu Vaishnav , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
pp. 70-75

Requirements-Based Design Evaluation (Abstract)

Panos K. Chrysanthis , University of Pittsburgh
Stephen T. Frezza , University of Pittsburgh
Steven P. Levitan , University of Pittsburgh
pp. 76-81

Incorporating Design Schedule Management into a Flow Management System (Abstract)

Jay B. Brockman , University of Notre Dame, IN
Eric W. Johnson , University of Notre Dame, IN
pp. 82-87

Generating ECAD Framework Code from Abstract Models (Abstract)

Bernd Sch?rmann , University of Kaiserslautern, Germany
Joachim Altmeyer , University of Kaiserslautern, Germany
Martin Sch? , University of Kaiserslautern, Germany
pp. 88-93

Tool Integration and Construction using Generated Graph-Gased Design Representations (Abstract)

Raul Camposano , GMD-SET, Sankt Augustin, Germany
Ansgar Bredenfeld , Synopsys Inc., Mountain View, CA
pp. 94-99

Scheduling using Behavioral Templates (Abstract)

Don MacMillen , Synopsys Inc., Mountain View, CA
David Knapp , Synopsys Inc., Mountain View, CA
Ron Miller , Synopsys Inc., Mountain View, CA
Tai Ly , Synopsys Inc., Mountain View, CA
pp. 101-106

Rephasing: A Transformation Technique for the Manipulation of Timing Constraints (Abstract)

Mani Srivastava , AT&T Bell Laboratories, Murray Hill, NJ
Miodrag Potkonjak , NEC USA, Inc., Princeton, NJ
pp. 107-112

Fast Identification of Robust Dependent Path Delay Faults (Abstract)

K.-T. Cheng , University of California, Santa Barbara
U. Sparmann , University of Saarland, Germany
D. Luxenburger , University of Saarland, Germany
S. M. Reddy , University of Iowa, Iowa City
pp. 119-125

On Synthesis-for-Testability of Combinational Logic Circuits (Abstract)

Sudhakar M. Reddy , University of Iowa, Iowa City
Irith Pomeranz , University of Iowa, Iowa City
pp. 126-132

Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits using Ccompact Lists (Abstract)

Sreejit Chakravarty , State University of New York, Buffalo, NY
Janak H. Patel , University of Illinois, Urbana
Srikanth Venkataraman , University of Illinois, Urbana
Elizabeth M. Rudnick , Motorola Inc., Austin, TX
W. Kent Fuchs , University of Illinois, Urbana
Ismed Hartanto , University of Illinois, Urbana
pp. 133-138

Parallel Logic Simulation of VLSI Systems (Abstract)

Roger D. Chamberlain , Washington University, St. Louis, Missouri
pp. 139-143

Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors (Abstract)

Sumit Ghosh , Brown University, Providence, Rhode Island
Peter A. Walker , Brown University, Providence, Rhode Island
pp. 144-150

A General Method for Compiling Event-Driven Simulations (Abstract)

Jeremy R. Levitt , Stanford University, CA
Robert S. French , Stanford University, CA
Monica S. Lam , Stanford University, CA
Kunle Olukotun , Stanford University, CA
pp. 151-156

A Transformation-Based Approach for Storage Optimization (Abstract)

Wei-Kai Cheng , Tsing Hua University, Taiwan
Youn-Long Lin , Tsing Hua University, Taiwan
pp. 158-163

Register Minimization Beyond Sharing Among Variables (Abstract)

Tsung-Yi Wu , Tsing Hua University, Taiwan
Youn-Long Lin , Tsing Hua University, Taiwan
pp. 164-169

Constrained Register Allocation in Bus Architectures (Abstract)

Elof Frank , Germany National Research Center for Computer Science (GMD), Germany
Majid Sarrafzadeh , Northwestern University, Evanston, IL
Salil Raje , Northwestern University, Evanston, IL
pp. 170-175

On Test Set Preservation of Retimed Circuits (Abstract)

Wojciech Maly , Northwestern University, Evanston, IL
Janusz Rajski , Mentor Graphics Corp., Wilsonville, OR
Aiman El-Maleh , McGill University, Canada
Thomas Marchok , Carnegie Mellon University, Pittsburgh, PA
pp. 176-182

Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation (Abstract)

Elizabeth M. Rudnick , Motorola, Incorporated, Austin, TX
Janak H. Patel , University of Illinois, Urbana, IL
pp. 183-188

Partial Scan with Pre-Selected Scan Signals (Abstract)

Peichen Pan , University of Illinois at Urbana-Champaign
C. L. Liu , University of Illinois at Urbana-Champaign
pp. 189-194

Spectral Partitioning: The More Eigenvectors, The Better (Abstract)

So-Zen Yao , Cadence Design Systems, San Jose, CA
Charles J. Alpert , UCLA Computer Science Department, Los Angeles, CA
pp. 195-200

Multi-Way Partitioning for Minimum Delay for Look-Up Table based FPGAs (Abstract)

Prashant Sawkar , Carnegie-Mellon University, Pittsburgh, PA
Donald Thomas , Carnegie-Mellon University, Pittsburgh, PA
pp. 201-210

Timing Driven Placement for Large Standard Cell Circuits (Abstract)

William Swartz , TimberWolf Systems, Inc., Dallas, TX
Carl Sechen , University of Washington, Seattle
pp. 211-215

Quantified Suboptimality of VLSI Layout Heuristics (Abstract)

Andrew B. Kahng , UCLA Department of Computer Science
Lars W. Hagen , Cadence Design Systems, Inc., San Jose, CA
Dennis J. H. Huang , UCLA Department of Computer Science
pp. 216-221

Digital Receiver Design using VHDL Generation from Data Flow Graphs (Abstract)

Peter Zepter , Aachen University of Technology, Germany
Heinrich Meyr , Aachen University of Technology, Germany
Thorsten Gr?tker , Aachen University of Technology, Germany
pp. 228-233

Logic Verification Methodology for PowerPC Microprocessors (Abstract)

Max Dieudonn? , Motorola Inc., Austin, Texas
Charles H. Malley , IBM Corporation, Austin, Texas
pp. 234-240

A Survey of Optimization Techniques Targeting Low Power VLSI Circuits (Abstract)

Srinivas Devadas , Massachusetts Institute of Technology
Sharad Malik , Princeton University
pp. 242-247

Logic Extraction and Factorization for Low Power (Abstract)

Sasan Iman , University of Southern California, Los Angeles, CA
Massoud Pedram , University of Southern California, Los Angeles, CA
pp. 248-253

Timed Shared Circuits: A Power-Efficient Design Style and Synthesis Tool (Abstract)

Alberto L. Sangiovanni-Vincentelli , Cadence Berkeley Laboratories, Berkeley, CA
Patrick C. McGeer , Cadence Berkeley Laboratories, Berkeley, CA
Alexander Saldanha , Cadence Berkeley Laboratories, Berkeley, CA
Luciano Lavagno , Cadence Berkeley Laboratories, Berkeley, CA
pp. 254-260

The Aurora RAM Compiler (Abstract)

Ajay Chandna , University of Michigan, Ann Arbor
Karem A. Sakallah , University of Michigan, Ann Arbor
C. David Kibler , Hewlett Packard Company, Ft. Collins, CO
Mark Roberts , University of Michigan, Ann Arbor
Richard B. Brown , University of Michigan, Ann Arbor
pp. 261-266

Automatic Layout Synthesis of Leaf Cells (Abstract)

J. Donald Trotter , Mississippi State University, Starkville, MS
Daniel H. Linder , Mississippi State University, Starkville, MS
Sanjay Rekhi , Mississippi State University, Starkville, MS
pp. 267-272

Delayed Frontal Solution for Finite-Element based Resistance Extraction (Abstract)

N. P. van der Meijs , Delft University of Technology, The Netherlands
A. J. van Genderen , Delft University of Technology, The Netherlands
pp. 273-278

Test Program Generation for Functional Verification of PowerPC Processors in IBM (Abstract)

Yossi Malka , IBM Israel - Haifa Research Lab
Yossi Lichtenstein , IBM Israel - Haifa Research Lab
Gil Shurek , IBM Israel - Haifa Research Lab
Moshe Molcho , IBM Israel - Haifa Research Lab
Charlotte Metzger , IBM Israel - Haifa Research Lab
Moshe Levinger , IBM Israel - Haifa Research Lab
Aharon Aharon , IBM Israel - Haifa Research Lab
Dave Goodman , IBM Israel - Haifa Research Lab
pp. 279-285

Behavioral Synthesis Methodology for HDL-Based Specification and Validation (Abstract)

T. Ly , Synopsys Inc., Mountain View, CA
R. Miller , Synopsys Inc., Mountain View, CA
D. MacMillen , Synopsys Inc., Mountain View, CA
D. Knapp , Synopsys Inc., Mountain View, CA
pp. 286-291

Design-Flow and Synthesis for ASICs: A Case Study (Abstract)

Roger B. Hughes , Abstract Hardware Limited, UK
Giuseppe Zaza , ITALTEL SIT, Italy
Salvatore Conigliaro , ITALTEL SIT, Italy
Massimo Bombana , ITALTEL SIT, Italy
Patrizia Cavalloro , ITALTEL SIT, Italy
Gerry Musgrave , Brunel University, UK
pp. 292-297

Model Checking in Industrial Hardware Design (Abstract)

J? Bormann , Siemens Corporate R&D, Germany
Michael Payer , Siemens Corporate R&D, Germany
Gerd Venzl , Siemens Corporate R&D, Germany
J? Lohse , Siemens Corporate R&D, Germany
pp. 298-303

DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling (Abstract)

Kumar N. Lalgudi , Yale University, New Haven, CT
Marios C. Papaefthymiou , Yale University, New Haven, CT
pp. 304-309

A Fresh Look at Retiming via Clock Skew Optimization (Abstract)

Rahul B. Deokar , Iowa State University, Ames, IA
Sachin S. Sapatnekar , Iowa State University, Ames, IA
pp. 310-315

The Validity of Retiming Sequential Circuits (Abstract)

Robert K. Brayton , University of California at Berkeley
Richard L. Rudell , Synopsys Inc., Mountain View, CA
Vigyan Singhal , University of California at Berkeley
Carl Pixley , Motorola Inc., Austin, TX
pp. 316-321

Retiming Synchronous Circuitry with Imprecise Delays (Abstract)

I. Karkowski , Delft University of Technology, The Netherlands
R. H. J. M. Otten , Delft University of Technology, The Netherlands
pp. 322-326

A Fast State Assignment Procedure for Large FSMs (Abstract)

Alvin M. Despain , University of Southern California, Los Angeles
Shihming Liu , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
pp. 327-332

Software Accelerated Functional Fault Simulation for Data-Path Architectures (Abstract)

M. Kassab , McGill University, Montreal, Canada
J. Rajski , Mentor Graphics Corporation, Wilsonville, OR
N. Mukherjee , McGill University, Montreal, Canada
J. Tyszer , McGill University, Montreal, Canada
pp. 333-338

Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy (Abstract)

R. Krieger , J. W. Goethe-University, Germany
M. Keim , J. W. Goethe-University, Germany
B. Becker , J. W. Goethe-University, Germany
pp. 339-344

Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks (Abstract)

Tracy Larrabee , University of California at Santa Cruz
Haluk Konuk , University of California at Santa Cruz
F. Joel Ferguson , University of California at Santa Cruz
pp. 345-351

Analysis of Switch-Level Faults by Symbolic Simulation (Abstract)

Jordi Carrabina-Bordoll , Universitat Aut?noma de Barcelona, UAB, Spain
Llu? Ribas-Xirgo , Universitat Aut?noma de Barcelona, UAB, Spain
pp. 352-357

Transmission Line Synthesis (Abstract)

Lawrence T. Pileggi , The University of Texas at Austin
Byron Krauter , IBM, Austin, TX
John Willis , The University of Texas at Austin
Rohini Gupta , The University of Texas at Austin
pp. 358-363

The Elmore Delay as Bound for RC Trees with Generalized Input Signals (Abstract)

John Willis , The University of Texas at Austin
Rohini Gupta , The University of Texas at Austin
Lawrence T. Pileggi , The University of Texas at Austin
Bogdan Tutuianu , The University of Texas at Austin
Byron Krauter , IBM, Austin, TX
pp. 364-369

Delay Analysis of the Distributed RC Line (Abstract)

Vasant B. Rao , IBM EDA Laboratory, NY
pp. 370-375

Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances Associated with 3-D Interconnect Structures (Abstract)

Mattan Kamon , Massachusetts Institute of Technology, Cambridge, MA
Jacob White , Massachusetts Institute of Technology, Cambridge, MA
L. Miguel Silveira , Massachusetts Institute of Technology, Cambridge, MA
pp. 376-380

Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs (Abstract)

Sharad Mehrotra , IBM Corporation, Austin, TX
Paul Franzon , North Carolina State University, Raleigh, NC
Michael Steer , North Carolina State University, Raleigh, NC
pp. 381-387

Symbolic Modeling and Evaluation of Data Paths (Abstract)

Forrest Brewer , University of California, Santa Barbara
Chuck Monahan , University of California, Santa Barbara
pp. 389-394

Data Path Allocation for Synthesizing RTL Design with Low BIST Area Overhead (Abstract)

Sandeep Gupta , University of Southern California, Los Angeles
Melvin A. Breuer , University of Southern California, Los Angeles
Ishwar Parulkar , University of Southern California, Los Angeles
pp. 395-401

Deriving Efficient Area and Delay Estimates by Modeling Layout Tools (Abstract)

Donald S. Gelosh , Air Force Institute of Technology, OH
Dorothy E. Setliff , University of Pittsburgh, PA
pp. 402-407

Efficient OBDD-Based Boolean Manipulation in CAD Beyond Current Limits (Abstract)

Christoph Meinel , Universit?t Trier, Germany
Anna Slobodov? , Universit?t Trier, Germany
Jochen Bern , Universit?t Trier, Germany
pp. 408-413

Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment (Abstract)

Wolfgang Kunz , University of Potsdam, Germany
Dhiraj K. Pradhan , Texas A& University, College Station, Texas
Subdodh M. Reddy , Unisys Corporation; Texas A& University, College Station, Texas
pp. 414-419

Advanced Verification Techniques based on Learning (Abstract)

Rajarshi Mukherjee , Fujitsu Laboratories of America, San Jose, CA
Jawahar Jain , Fujitsu Laboratories of America, San Jose, CA
Masahiro Fujita , Fujitsu Laboratories of America, San Jose, CA
pp. 420-426

Efficient Generation of Counterexamples and Witnesses in Symbolic Model Checking (Abstract)

E. M. Clarke , Carnegie Mellon University, Pittsburgh, PA
X. Zhao , Carnegie Mellon University, Pittsburgh, PA
O. Grumberg , The Technion, Israel
K. L. McMillan , Cadence Berkeley Labs., CA
pp. 427-432

DARWIN: CMOS Opamp Synthesis by Means of a Genetic Algorithm (Abstract)

Domine Leenaerts , Eindhoven University of Technology, the Netherlands
Wim Kruiskamp , Eindhoven University of Technology, the Netherlands
pp. 433-438

Mixed-Signal Switching Noise Analysis using Voronoi-Tessellated Substrate Macromodels (Abstract)

Ivan L. Wemple , University of Washington
Andrew T. Yang , University of Washington
pp. 439-444

Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits (Abstract)

K. Lampaert , Katholike Universiteit Leuven, Belgium
W. Sansen , Katholike Universiteit Leuven, Belgium
G. Gielen , National Fund of Scientific Research
pp. 445-449

System-Level Design for Test of Fully Differential Analog Circuits (Abstract)

Bapiraju Vinnakota , University of Minnesota, Minneapolis
Nicholas J. Stessman , University of Minnesota, Minneapolis
Ramesh Harjani , University of Minnesota, Minneapolis
pp. 450-454

Performance Analysis of Embedded Software using Implicit Path Enumeration (Abstract)

Yau-Tsun Steven Li , Princeton University, NJ
Sharad Malik , Princeton University, NJ
pp. 456-461

Interval Scheduling: Fine-Grained Code Scheduling for Embedded Systems (Abstract)

Pai Chou , University of Washington, Seattle
Gaetano Borriello , University of Washington, Seattle
pp. 462-467

Interfacing Incompatible Protocols using Interface Process Generation (Abstract)

Daniel D. Gajski , Univ. of California, Irvine
Sanjiv Narayan , Viewlogic Systems Inc., Marlboro, MA
pp. 468-473

Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm (Abstract)

P. Feldmann , AT&T Bell Laboratories, Murray Hill, NJ
R. W. Freund , AT&T Bell Laboratories, Murray Hill, NJ
pp. 474-479

Efficient Steady-State Analysis Based on Matrix-Free Krylov-Subspace Methods (Abstract)

Jacob K. White , Massachusetts Institute of Technology, Cambridge, Massachusetts
Ricardo Telichevesky , Cadence Design Systems, San Jose, CA
Kenneth S. Kundert , Cadence Design Systems, San Jose, CA
pp. 480-484

Transient Simulations of Three-Dimensional Integrated Circuit Interconnect using a Mixed Surface-Volume Approach (Abstract)

Tom Korsmeyer , Massachusetts Institute of Technology, Cambridge, MA
Jacob White , Massachusetts Institute of Technology, Cambridge, MA
Mike Chou , Massachusetts Institute of Technology, Cambridge, MA
pp. 485-490

Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution (Abstract)

Wayne W. M. Dai , University of California, Santa Cruz
Joe G. Xi , University of California, Santa Cruz
pp. 491-496

Power Optimal Buffered Clock Tree Design (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara, CA
Ashok Vittal , University of California, Santa Barbara, CA
pp. 497-502

Power Distribution Topology Design (Abstract)

Ashok Vittal , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 503-507

On the Bounded-Skew Clock and Steiner Routing Problems (Abstract)

Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
Dennis J. H. Huang , UCLA Computer Science Dept., Los Angeles, CA
Chung-Wen Albert Tsao , UCLA Computer Science Dept., Los Angeles, CA
pp. 508-513

Benchmarking an Interdisciplinary Concurrent Design Methodology for Electronic/Mechanical Systems (Abstract)

Asim Smailagic , Carnegie Mellon University, Pittsburgh, PA
Tom Martin , Carnegie Mellon University, Pittsburgh, PA
John Stivoric , Carnegie Mellon University, Pittsburgh, PA
Daniel P. Siewiorek , Carnegie Mellon University, Pittsburgh, PA
Chris Kasaback , Carnegie Mellon University, Pittsburgh, PA
Drew Anderson , Carnegie Mellon University, Pittsburgh, PA
pp. 514-519

A Methodology for HW-SW Codesign in ATM (Abstract)

Giovanni Mancini , Functionality Inc., Canada
Dave Yurach , Bell-Northern Research, Canada
Spiros Boucouris , Bell-Northern Research, Canada
pp. 520-527

Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation (Abstract)

Mario Dufresne , Bell Northern Research, Ontario, Canada
Allan Silburt , Bell Northern Research, Ontario, Canada
Stacy Nichols , Bell Northern Research, Ontario, Canada
Ian Perryman , Bell Northern Research, Ontario, Canada
Greg Ward , Bell Northern Research, Ontario, Canada
Janick Bergeron , AnalySYS Inc., Ontario, Canada
pp. 528-533

Verification of Arithmetic Circuits with Binary Moment Diagrams (Abstract)

Yirng-An Chen , Carnegie Mellon University, Pittsburgh, PA
Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
pp. 535-541

Residue BDD and Its Application to the Verification of Arithmetic Circuits (Abstract)

Shinji Kimura , Nara Institute of Science and Technology, Japan
pp. 542-545

Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions (Abstract)

Wayne Burleson , University of Massachusetts at Amherst, MA
Zheng Zhou , University of Massachusetts at Amherst, MA
pp. 546-551

On Optimal Board-Level Routing for FPGA-Based Logic Emulation (Abstract)

Wai-Kei Mak , University of Texas at Austin, TX
D. F. Wong , University of Texas at Austin, TX
pp. 552-556

A Performance and Routablity Driven Router for FPGAs Considering Path Delays (Abstract)

Yuh-sheng Lee , Tsing Hua University, Taiwan
Allen C.-H. Wu , Tsing Hua University, Taiwan
pp. 557-561

New Performance-Driven FPGA Routing Algorithms (Abstract)

Gabriel Robins , University of Virginia, Charlottesville, CA
Michael J. Alexander , University of Virginia, Charlottesville, CA
pp. 562-567

Orthogonal Greedy Coupling: A New Optimization Approach to 2-D FPGA Routing (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara, CA
Yu-Liang Wu , Cadence Design Systems, Inc. San Jose, CA
pp. 568-573

Effects of FPGA Architecture on FPGA Routing (Abstract)

Stephen Trimberger , Xilinx, Inc., San Jose, CA
pp. 574-578

The Case for Design using the World Wide Web (Abstract)

Randy H. Katz , University of California, Berkeley
M?rio J. Silva , University of California, Berkeley
pp. 579-585

Synthesis of Software Programs for Embedded Control Application (Abstract)

Ellen Sentovich , Cadence Berkeley Labs, Berkeley, CA
Kei Suzuki , Univ. of California, Berkeley, CA
Paolo Guisto , Magneti Marelli, Italy
Massimiliano Chiodo , Magneti Marelli, Italy
Luciano Lavagno , Politecnico di Torino, Italy
Harry Hsieh , Univ. of California, Berkeley, CA
Attila Jurecska , Magneti Marelli, Italy
Alberto Sangiovanni-Vincentelli , Univ. of California, Berkeley, CA
pp. 587-592

Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores (Abstract)

Jochen A.G. Jess , Eindhoven University of Technology
Adwin H. Timmer , Eindhoven University of Technology; Philips Research Laboratories, The Netherlands
Marino T.J. Strik , Philips Research Laboratories, The Netherlands
Jef L. van Meerbergen , Philips Research Laboratories, The Netherlands
pp. 593-598

Code Optimization Techniques for Embedded DSP Microprocessors (Abstract)

Albert Wang , MIT Department of EECS, Cambridge, MA
Srinivas Devadas , Synopsys, Inc., Mountain View, CA
Kurt Keutzer , MIT Department of EECS, Cambridge, MA
Steve Tjiang , Synopsys, Inc., Mountain View, CA
Stan Liao , Synopsys, Inc., Mountain View, CA
pp. 599-604

Retargetable Self-Test Program Generation using Constraint Logic Programming (Abstract)

Peter Marwedel , University of Dortmund, Germany
Ulrich Bieker , University of Dortmund, Germany
pp. 605-611

Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits (Abstract)

Farid N. Najm , University of Illinois at Urbana-Champaign
pp. 612-617

Accurate Estimation of Combinational Circuit Activity (Abstract)

Huzefa Mehta , The Pennsylvania State University
Robert Michael Owens , The Pennsylvania State University
Manjit Borah , The Pennsylvania State University
Mary Jane Irwin , The Pennsylvania State University
pp. 618-622

Extreme Delay Sensitivity and the Worst-Case Wwitching Activity in VLSI Circuits (Abstract)

Michael Y. Zhang , University of Illinois at Urbana-Champaign
Farid N. Najm , University of Illinois at Urbana-Champaign
pp. 623-627

Efficient Power Estimation for Highly Correlated Input Streams (Abstract)

Radu Marculescu , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
Diana Marculescu , University of Southern California, Los Angeles
pp. 628-634

Power Estimation in Sequential Circuits (Abstract)

Shashank Goel , University of Illinois at Urbana-Champaign
Ibrahim N. Hajj , University of Illinois at Urbana-Champaign
Farid N. Najm , University of Illinois at Urbana-Champaign
pp. 635-640

New Ideas for Solving Covering Problems (Abstract)

Jean Chritophe Madre , Synopsys, Mountain View, CA
Olivier Coudert , Synopsys, Mountain View, CA
pp. 641-646

Logic Synthesis for Engineering Change (Abstract)

Kwang-Ting Cheng , University of California, Santa Barbara
Kuang-Chien Chen , Fujitsu Laboratories of America, INC.
Shih-Chieh Chang , Synopsys Inc.
Malgorzata Marek-Sadowska , University of California, Santa Barbara
Chih-Chang Lin , University of California, Santa Barbara
pp. 647-652

Multi-Level Logic Minimization Based on Multi-Signal Implications (Abstract)

Yuichi Nakamura , NEC Corporation, Japan
Tomoyuki Fujita , NEC Corporation, Japan
Masayuki Yuguchi , NEC Corporation, Japan
Kazutoshi Wakabayashi , NEC Corporation, Japan
pp. 658-662

An Efficient Algorithm for Local Don't Care Sets Calculation (Abstract)

Shih-Chieh Chang , Synopsys Inc.
Kwang-Ting Cheng , University of California at Santa Barbara
Malgorzata Marek-Sadowska , University of California at Santa Barbara
pp. 663-667

Logic Clause Analysis for Delay Optimization (Abstract)

Berhard Rohfleisch , Technical University of Munich, Germany
Kurt Antreich , Technical University of Munich, Germany
Bernd Wurth , Technical University of Munich, Germany
pp. 668-672

Productivity Issues in High-Level Design: Are Tools Solving the Real Problems? (Abstract)

Reinaldo A. Bergamaschi , Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 674-677

Information Models of VHDL (Abstract)

Hilary J. Kahn , University of Manchester, UK
Cristian A. Giumale , Technical University of Bucharest, Romania
pp. 678-683

Measures of Syntactic Complexity for Modeling Behavioral VHDL (Abstract)

John D. Provence , Southern Methodist University, Dallas, Texas
Neal S. Stollon , DSC Communications Corporation, Dallas, Texas
pp. 684-689

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization (Abstract)

Satyamurthy Pullela , The University of Texas at Austin
Lawrence T. Pileggi , The University of Texas at Austin
Noel Menezes , The University of Texas at Austin
pp. 690-695

An Algorithm for Incremental Timing Analysis (Abstract)

Jin-fuw Lee , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Donald T. Tang , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 696-701

An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard Cells (Abstract)

Luigi Croce , SGS-THOMSON Microelectronics, Italy
Alessandro Dal Fabbro , SGS-THOMSON Microelectronics, Italy
Bruno Franzini , SGS-THOMSON Microelectronics, Italy
Carlo Guardiani , SGS-THOMSON Microelectronics, Italy
pp. 702-706

Automatic Clock Abstraction from Sequential Circuits (Abstract)

Samir Jain , Carnegie Mellon University, Pittsburgh, PA
Alok Jain , Digital Equipment Corporation, Hudson, MA
Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
pp. 707-711

Hierarchical Optimization of Asynchronous Circuits (Abstract)

Tilman Kolks , IMEC, Leuven, Belgium
Bill Lin , IMEC, Leuven, Belgium
Gjalt de Jong , IMEC, Leuven, Belgium
pp. 712-717

Externally Hazard-Free Implementations of Asynchronous Circuits (Abstract)

Chantal Ykman-Couvreur , IMEC, Leuven, Belgium
Bill Lin , IMEC, Leuven, Belgium
Milton Sawasaki , IMEC, Leuven, Belgium
pp. 718-724

A Design and Validation System for Asynchronous Circuits (Abstract)

Kurt Keutzer , Synopsys, Inc., Mountain View, CA
Peter Vanbekbergen , Synopsys, Inc., Mountain View, CA
Albert Wang , Synopsys, Inc., Mountain View, CA
pp. 725-730
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