The Community for Technology Leaders
1994 31st Design Automation Conference (1994)
San Diego, CA, USA
June 6, 1994 to June 10, 1994
ISSN: 0738-100X
ISBN: 0-89791-653-0
TABLE OF CONTENTS

Reviewers (PDF)

pp. xi,xii,xiii,xiv,xv

1994 Keynote Address (PDF)

D.G. Fairbairn , Redwood Design Automation, Inc., San Jose, CA
pp. 0-0

Software Scheduling in the Co-Synthesis of Reactive Real-Time Systems (PDF)

Pai Chou , Department of Computer Science and Engineering, University of Washington, Seattle, WA
pp. 1-4

Synthesis of Instruction Sets for Pipelined Microprocessors (PDF)

Ing-Jer Huang , Advanced Computer Architecture Laboratory, Department of Electrical Engineering - Systems, University of Southern California
pp. 5-11

Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs (PDF)

Chi-Ying Tsui , Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
pp. 18-23

ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits (Abstract)

E.S. Ochotta , Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA
pp. 24-30

Simultaneous Placement and Module Optimization of Analog IC's (Abstract)

E. Charbon , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 31-35

Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits (Abstract)

S. Mehrotra , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC
pp. 36-40

Management Issues in EDA (Abstract)

A.M. Prabhu , Deloitte & Touche, New York, NY
pp. 41-47

Panel: Executive Perspective and Vision of the Future of EDA (PDF)

R. Collett , Collett International, Inc., Santa Clara, CA
pp. 48

A Modular Partitioning Approach for Asynchronous Circuit Synthesis (Abstract)

R. Puri , Dept. of Electrical & Computer Engineering, University of Calgary, Calgary, Canada
pp. 63-69

Performance Analysis Based on Timing Simulation (Abstract)

C.D. Nielsen , Department of Computer Science, Technical University of Denmark, Lyngby, DK
pp. 70-76

An Exact Algorithm for Selecting Partial Scan Flip-Flops (Abstract)

S.T. Chakradhar , C & C Research Laboratories, NEC USA, Princeton, NJ
pp. 81-86

Resynthesis and Retiming for Optimum Partial Scan (Abstract)

S.T. Chakradhar , C & C Research Laboratories, NEC USA, Princeton, NJ
pp. 87-93

Clock Grouping: A Low Cost DFT Methodology for Delay Testing (PDF)

Wen-Chang Fang , Electrical Engineering - Systems, University of Southern California, Los Angeles CA
pp. 94-99

Interface Timing Verification with Application to Synthesis (Abstract)

E.A. Walkup , Department of Computer Science and Engineering, University of Washington, Seattle, WA
pp. 106-112

Automated Multi-Cycle Symbolic Timing Verification of Microprocessor-based Designs (Abstract)

A.P. Gupta , ECE Department, Carnegie Mellon University, Pittsburgh, PA
pp. 113-119

The Minimization and Decomposition of Interface State Machines (Abstract)

A.J. Daga , EECS Department, The University of Michigan, Ann Arbor, MI
pp. 120-125

Statistical Delay Modeling in Logic Design and Synthesis (Abstract)

H. Jyu , Department of Electrical Engineering, Princeton University, Princeton, NJ
pp. 126-130

Cost of Silicon Viewed from VLSI Design Perspective (Abstract)

W. Maly , Department of Electrical and Computer Engineering, Carnegie Mellon University , Pittsburgh , PA
pp. 135-142

Memory Estimation for High Level Synthesis (Abstract)

I.M. Verbauwhede , EECS Department, University of California at Berkeley, Berkeley CA
pp. 143-148

Minimization of Memory Traffic in High-Level Synthesis (Abstract)

D.J. Kolson , Department of Information and Computer Science, University of California, Irvine, Irvine, CA
pp. 149-154

Sequencer-Based Data Path Synthesis of Regular Iterative Algorithms (Abstract)

M. Aloqeely , Department of Electrical and Computer Engineering, Syracuse University, Syracuse, NY
pp. 155-160

Intellectual Property Protection in the EDA Industry (Abstract)

D.S. Fernandez , Fenwick & West, Palo Alto, CA
pp. 161-163

Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs (PDF)

Kai Zhu , Department of Computer Sciences, University of Texas at Austin, Austin, TX
pp. 165-170

Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture (PDF)

Yachyang Sun , Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 171-176

A Global Router Optimizing Timing and Area for High-Speed Bipolar LSI's (Abstract)

I. Harada , NTT LSI Laboratories, Kanagawa, JAPAN
pp. 177-181

A Unified Approach to Multilayer Over-the-Cell Routing (Abstract)

S. Madhwapathy , Dept. of Computer Science, Western Michigan University, Kalamazoo, MI
pp. 182-187

Panel: ESDA and Design Abstraction: How High Is Up? (PDF)

B. Geoffrey , Technologies and Transitions Corp., Tigard, OR
pp. 188

Clock Period Optimization During Resource Sharing and Assignment (Abstract)

S. Bhattacharya , Dept. of Computer Science, Duke University, Durham, NC
pp. 195-200

Optimizing Resource Utilization and Testability Using Hot Potato Techniques (Abstract)

M. Potkonjak , C&C Research Laboratories, NEC USA, Princeton, NJ
pp. 201-205

Microarchitectural Synthesis of VLSI Designs with High Test Concurrency (Abstract)

I.G. Harris , Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA
pp. 206-211

Rectification of Multiple Logic Design Errors in Multiple Output Circuits (Abstract)

M. Tomita , The Graduate School of Science and Technology, Kobe University, Kobe, JAPAN
pp. 212-217

Error Diagnosis for Transistor-Level Verification (Abstract)

A. Kuehlmann , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 218-224

Heuristic Minimization of BDDs Using Don't Cares (Abstract)

T.R. Shiple , Department of EECS, University of California, Berkeley, CA
pp. 225-231

Clock Skew Minimization During FPGA Placement (PDF)

Kai Zhu , Department of Computer Sciences, University of Texas at Austin, Austin, TX
pp. 232-237

Experience with Image Compression Chip Design Using Unified System Construction Tools (Abstract)

P. Gupta , Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
pp. 250-256

The Use of CAD Frameworks in a CIM Environment (PDF)

Wang Tek Kee , GINTIC Institute of Manufacturing Technology, Nanyang Technological University
pp. 257-261

Probabilistic Analysis of Large Finite State Machines (Abstract)

G.D. Hachtel , University of Colorado, Dept. of Electrical and Computer Engineering, Boulder, CO
pp. 270-275

New Techniques for Efficient Verification with Implicitly Conjoined BDDs (Abstract)

A.J. Hu , Department of Computer Science, Stanford University
pp. 276-282

BDD Variable Ordering for Interacting Finite State Machines (Abstract)

A. Aziz , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 283-288

Auxiliary Variables for Extending Symbolic Traversal Techniques to Data Paths (Abstract)

G. Cabodi , Politecnico di Torino, Dipartimento di Automatica e Informatica, Turin, Italy
pp. 289-293

Panel: Microprocessor Testing: Which Technique Is Best? (Abstract)

J.A. Abraham , Univ. of Texas, Austin, TX
pp. 294

Placement and Routing for a Field Programmable Multi-Chip Module (Abstract)

S. Lan , Information Systems Laboratory, Stanford University, Stanford, CA
pp. 295-300

Performance-Driven Simultaneous Place and Route for Row-Based FPGAs (Abstract)

S.K. Nag , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
pp. 301-307

Layout Driven Logic Synthesis for FPGAs (PDF)

Shih-Chieh Chang , Electrical and Computer Engineering Department, University of California Santa Barbara
pp. 308-313

Fitting Formal Methods into the Design Cycle (PDF)

K.L. McMillan , AT&T Bell Laboratories, Murray Hill, NJ
pp. 314-319

Panel: Complex System Verification: The Challenge Ahead (PDF)

R. Collett , Collett International, Inc., Santa Clara, CA
pp. 320

A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays (Abstract)

A. Sarabi , Portland State University, Department of Electrical Engineering, Portland, OR
pp. 321-326

Technology Mapping Using Fuzzy Logic (Abstract)

S. Iman , Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
pp. 333-338

Boolean Matching Using Generalized Reed-Muller Forms (PDF)

Chien-Chung Tsai , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA
pp. 339-344

Extraction of a High ­ level Structural Representation from Circuit Descriptions with Applications to DFT/BIST "Lambda (PDF)

I. Parulkar , Department of Electrical Engineering ­ Systems, University of Southern California, Los Angeles, CA
pp. 345-350

DFBT: A Design-for-Testability Method Based on Balance Testing (Abstract)

K. Chakrabarty , Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI
pp. 351-357

Design-for-Testability for Path Delay Faults in Large Combinational Circuits Using Test-Points (PDF)

I. Pomeranz , Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA
pp. 358-364

Generation of High Quality Non-Robust Tests for Path Delay Faults (PDF)

Kwang-Ting Cheng , Department of ECE, University of California, Santa Barbara, CA
pp. 365-369

On Testing Wave Pipelined Circuits (PDF)

Jui-Ching Shyur , Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.0.C.
pp. 370-374

An Efficient Zero-Skew Routing Algorithm (Abstract)

M. Edahiro , C&C Research Laboratories, NEC Corporation, Kawasaki, Japan and Department of Computer Science, Princeton University, Princeton, NJ
pp. 375-380

Rectilinear Steiner Trees with Minimum Elmore Delay (Abstract)

K.D. Boese , CS Dept., University of California at Los Angeles, Los Angeles, CA
pp. 381-386

RC Interconnect Optimization under the Elmore Delay Model (Abstract)

S.S. Sapatnekar , Department of Electrical Engineering and Computer Engineering, Iowa State University, Ames, IA
pp. 387-391

Minimal Delay Interconnect Design Using Alphabetic Trees (Abstract)

A. Vittal , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA
pp. 392-396

Algorithmic Aspects of Three Dimensional MCM Routing (PDF)

Qiong Yu , Department of Computer Science, Western Michigan University, Kalamazoo, MI
pp. 397-401

Routing for Manufacturability (PDF)

Hua Xue , Design Automation Section, Dept. of EE, Eindhoven University of Technology, The Netherlands
pp. 402-406

Panel: Technology Summit - A View from the Top (PDF)

A.J. Graham , CAD Framework Initiative, Inc., Austin, TX
pp. 407

Optimum Functional Decomposition Using Encoding (Abstract)

R. Murgai , Department of EECS, University of California, Berkeley, CA
pp. 408-414

Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams (Abstract)

R. Drechsler , Computer Science Department, Johann Wolfgang Goethe University, Frankfurt am Main, Germany
pp. 415-419

Calculation of Unate Cube Set Algebra Using Zero-Suppressed BDDs (Abstract)

S. Minato , NTT LSI Laboratories, Kanagawa Pref., Japan
pp. 420-424

Random Generation of Test Instances for Logic Optimizers (Abstract)

K. Iwama , Department of Computer Science and Communication Engineering, Kyushu University, Fukuoka, Japan
pp. 430-434

Hardware-Software Co-Design and ESDA (PDF)

K. Keutzer , Synopsys, Inc., Mountain View, CA
pp. 435-436

Manifestations of Heterogeneity in Hardware/Software Codesign (PDF)

A. Kalavade , Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, CA
pp. 437-438

Hardware/Software Co-Simulation (PDF)

J.A. Rowson , Redwood Design Automation Inc., San Jose, CA
pp. 439-440

A System for Incremental Synthesis to Gate-Level and Reoptimization Following RTL Design Changes (Abstract)

S.C. Prasad , Integrated Systems Laboratory, Texas Instruments Incorporated, Dallas, TX
pp. 441-446

Rapid Prototyping of ASIC Based System (Abstract)

P.H. Kelly , Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA
pp. 460-465

Structured Design Methodology for High-Level Design (Abstract)

P. Kission , System-Level Synthesis Group/TIMA/INPG, Grenoble Cedex, France
pp. 466-471

Design Methodology Management Using Graph Grammars (Abstract)

R. Baldwin , Department of Computer Science, Michigan State University
pp. 472-478

Incorporating Speculative Execution in Exact Control-Dependent Scheduling (Abstract)

I. Radivojevic , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA
pp. 479-484

Loop Pipelining for Scheduling Multi-Dimensional Systems via Rotation (Abstract)

N.L. Passos , Dept. of Computer Science & Engineering, University of Notre Dame, Notre Dame, IN
pp. 485-490

Chain Closure: A Problem in Molecular CAD (Abstract)

M.D. Di Benedetto , Dipartimento di Informatica e Sistemistica, Universita di Roma "La Sapienza", Roma, Italy
pp. 497-502

On Improving Fault Diagnosis for Synchronous Sequential Circuits (Abstract)

I. Pomeranz , Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA
pp. 504-509

An Efficient Path Delay Fault Coverage Estimator (Abstract)

K. Heragu , Dept. of Electrical & Computer Eng., Rutgers University, Piscataway, NJ
pp. 516-521

Path Hashing to Accelerate Delay Fault Simulation (Abstract)

M. Henftling , Institute of Electronic Design Automation, Department of Electrical Engineering, Technical University of Munich, Munich, Germany
pp. 522-526

MIST - A Design Aid for Programmable Pipelined Processors (Abstract)

A.E. Casavant , C&C Research Laboratories, NEC USA, Inc., Princeton, NJ
pp. 532-536

Automatic Synthesis of Pipeline Structures with Variable Data Initiation Intervals (PDF)

Hong Shin Jun , CAD & Computer Systems Lab., Sogang University, Seoul, Korea
pp. 537-541

Global Scheduling for High-Level Synthesis Applications (PDF)

Yaw Fann , Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI
pp. 542-546

Protocol Generation for Communication Channels (Abstract)

S. Narayan , Viewlogic Systems Inc., Marlboro, MA
pp. 547-551

Area-EfficientFault Detection During Self-Recovering Microarchitecture Synthesis (PDF)

R. Karri , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, Amherst, MA
pp. 552-556

The Attributed-Behavior Abstraction and Synthesis Tools (Abstract)

L.F. Arnstein , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
pp. 557-561

Panel: Design Reuse: Fact or Fiction? (PDF)

N. Dutt , Univ. of California, Irvine, CA
pp. 562

Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model (Abstract)

A.B. Kahng , UCLA Computer Science Department, Los Angeles, CA
pp. 563-569

A Gate-Delay Model for High-Speed CMOS Circuits (Abstract)

F. Dartu , Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
pp. 576-580

Transient Sensitivity Computation of MOSFET Circuits Using Iterated Timing Analysis and Selective Tracing Waveform Relaxation (PDF)

Chun-Jung Chen , Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C
pp. 581-585

The Design of High-Performance Microprocessors at Digital (Abstract)

T.F. Fox , Semiconductor Engineering Group, Digital Equipment Corporation, Hudson, MA
pp. 586-591

Hitachi - PA/50, SH Series Microcontroller (Abstract)

T. Nishimukai , Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan
pp. 592-593

Low Power CMOS Design Strategies (Abstract)

M. Schobinger , Siemens AG, Corporate Research & Development, Munich, Germany
pp. 594-595

Formally Verifying a Microprocessor Using a Simulation Methodology (Abstract)

D.L. Beatty , Cadence Berkeley Laboratories, Cadence Design Systems, Inc.
pp. 596-602

Automatic Verification of Pipelined Microprocessors (Abstract)

V. Bhagwati , Research Laboratory of Electronics, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA
pp. 603-608

Efficient Simulation of Lossy and Dispersive Transmission Lines (PDF)

Tuyen V. Nguyen , IBM Microelectronics, Hopewell Junction, NY
pp. 622-627

An EfficientApproach to Transmission Line Simulation using Measured or Tabulated S-parameter Data (PDF)

L.M. Silveira , Research Laboratory of Electronics and the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA
pp. 634-639

OTTER: Optimal Termination of Transmission lines Excluding Radiation (Abstract)

R. Gupta , Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
pp. 640-645

Partitioning Very Large Circuits Using Analytical Placement Techniques (Abstract)

B.M. Riess , Institute of Electronic Design Automation, Technical University of Munich, Munich, Germany
pp. 646-651

Multi-Way Partitioning Via Spacefilling Curves and Dynamic Programming (Abstract)

C.J. Alpert , UCLA Computer Science Department, Los Angeles, CA
pp. 652-657

Data Flow Partitioning for Clock Period and Latency Minimization (PDF)

Lung-Tien Liu , Computer Science and Engineering, University of California, San Diego, La Jolla, CA
pp. 658-663

A Fast and Stable Hybrid Genetic Algorithm for the Ratio-Cut Partitioning Problem on Hypergraphs (PDF)

Thang Nguyen Bui , Dept. of Computer Science, Pennsylvania State University, Middletown, PA
pp. 664-669

Acyclic Multi-Way Partitioning of Boolean Networks (Abstract)

J. Cong , Department of Computer Science, University of California, Los Angeles, CA
pp. 670-675

Panel: Design Automation Tools for FPGA Design (PDF)

K. Knack , ASIC & EDA Magazine, Los Altos, CA
pp. 676

Permissible Observability Relations in FSM Networks (PDF)

Huey-Yih Wang , Department of EECS, University of California, Berkeley, CA
pp. 677-683

A Fully Implicit Algorithm for Exact State Minimization (Abstract)

T. Kam , Department of EECS, University of California at Berkeley, Berkeley, CA
pp. 684-690

Boolean Matching of Sequential Elements (Abstract)

S. Krishnamoorthy , Synopsis Inc., Mountain View, CA
pp. 691-697

Sequential Circuit Test Generation in a Genetic Algorithm Framework (Abstract)

E.M. Rudnick , Center for Reliable & High-Performance Computing, University of Illinois, Urbana, IL
pp. 698-704

Dynamic Search-Space Pruning Techniques in Path Sensitization (PDF)

J.P. Marques Silva , Department of Electrical Engineering and Computer Science, University of Michigan
pp. 705-711

Functional Test Generation for FSMs by Fault Extraction (Abstract)

B. Vinnakota , Department of Electrical Engineering, University of Minnesota, Minneapolis, MN
pp. 712-716

ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation (Abstract)

S. Parkes , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
pp. 717-721

Modeling of Intermediate Node States in Switch-Level Networks (Abstract)

P. Dahlgren , Department of Computer Engineering, Chalmers University of Technology, Gothenburg, Sweden
pp. 722-727

Statistical Estimation of the Switching Activity in Digital Circuitsy (PDF)

M.G. Xakellis , Coordinated Science Lab. & ECE Dept., University of Illinois at Urbana-Champaign, Urbana, IL
pp. 728-733

Improving the Accuracy of Circuit Activity Measurement (Abstract)

B. Kapoor , Integrated Systems Laboratory, Texas Instruments, Dallas, TX
pp. 734-739
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