The Community for Technology Leaders
30th ACM/IEEE Design Automation Conference (1993)
Dallas, TX, USA
June 14, 14 to June 18, 1993
ISSN: 0738-100X
ISBN: 0-89791-577-1
TABLE OF CONTENTS

Reviewers (PDF)

pp. ix,x,xi,xii,xiii,xiv

1993 Keynote Address (PDF)

W.F. Hayes , Defense Systems & Electronics Group, Texas Instruments Inc., Dallas, TX
pp. 1

Elimination of Dynamic Hazards by Factoring (PDF)

Cho W. Moon , Lattice Semiconductor, Santa Clara, CA
pp. 7-13

Optimized State Assignment of Single Fault Tolerant FSMs Based on SEC Codes (Abstract)

R. Leveugle , Institut National Polytechnique de Grenoble / CSI, Grenoble Cedex - FRANCE
pp. 14-18

Minimal Shift Counters and Frequency Division (Abstract)

A.M. Tokarnia , Department of Electrical Engineering, Stanford University, Stanford, CA
pp. 19-24

Algorithms for Approximate FSM Traversal (PDF)

Hyunwoo Cho , Department of Electrical and Computer Engineering, University of Colorado at Boulder
pp. 25-30

SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm (Abstract)

M. Ohlrich , Computer Science & Engineering Department, University of Washington, Seattle, WA
pp. 31-37

Resistance Extraction Using a Routing Algorithm (Abstract)

L. Ladage , Universitat Dortmund, Lehrstuhl Informatik 12, Dortmund, Germany
pp. 38-42

HV/VH Trees: A New Spatial Data Structure for Fast Region Queries (Abstract)

G.G. Lai , Department of Computer Sciences, University of Texas at Austin, Austin, TX
pp. 43-47

Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping (Abstract)

E.M. Clarke , School of Computer Science, Carnegie Mellon University, Pittsburgh, PA
pp. 54-60

Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs (Abstract)

P. Siegel , Center for Integrated Systems, Stanford University, Stanford CA
pp. 61-67

Technology Decomposition and Mapping Targeting Low Power Dissipation (PDF)

Chi-Ying Tsui , Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
pp. 68-73

Technology Mapping for Low Power (PDF)

V. Tiwari , Dept. of EE, Princeton Univ
pp. 74-79

INCREDYBLE-TG: INCREmental DYnamic Test Generation Based on LEarning (Abstract)

I. Pomeranz , Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA
pp. 80-85

Speed up of Behavioral A.T.P.G. Using a Heuristic Criterion (Abstract)

J. Santucci , Laboratoire d'Etude et de Recherche en Informatique, Nimes, FRANCE
pp. 92-96

A State Traversal Algorithm Using a State Covariance Matrix (Abstract)

A. Motohara , Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd., Osaka, Japan
pp. 97-101

Sequential Circuit Test Generation on a Distributed System (Abstract)

P. Agrawal , AT&T Bell Laboratories, Murray Hill, NJ
pp. 107-111

VIPER: An Efficient Vigorously Sensitizable Path Extractor (PDF)

Hoon Chang , Computer Engineering Research Center, University of Texas at Austin, Austin, TX
pp. 112-117

A Polynomial-Time Heuristic Approach to Approximate a Solution to the False Path Problem (PDF)

Shiang-Tang Huang , Dept. of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.
pp. 118-122

A Verification Technique for Gated Clock (Abstract)

M. Kawarabayashi , Advanced CAD Development Laboratory, NEC Corporation, Kawasaki, Kanagawa, Japan
pp. 123-127

Timing Optimization by Gate Resizing and Critical Path Identification (PDF)

Wen-Ben Jone , Department of Computer Science, National Chung-Cheng University, Chiayi, Taiwan, R.O.C.
pp. 135-140

Panel: What Is the Next Big Productivity Boost for Designers? (PDF)

K. Keutzer , Synopsys, Inc., Mountain View, CA
pp. 141

Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances (Abstract)

H.E. Graeb , Institute of Electronic Design Automation, Technical University Munich, Munich, Germany
pp. 142-147

A New Optimizer for Performance Optimization of Analog Integrated Circuits (Abstract)

N. Nagaraj , Texas Instruments (India) Pvt. Ltd., Bangalore, India
pp. 148-153

Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits (Abstract)

A. Dharchoudhury , Department of Electrical and Computer Engineering, Beckman Institute and Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, IL
pp. 154-158

Panel: Logic Emulation: A Niche or a Future Standard for Design Verification? (PDF)

J. Rose , Univ. of Toronto, Toronto, Ontario, Canada
pp. 164

Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization (Abstract)

S. Pullela , Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
pp. 165-170

High-Performance Routing Trees with Identified Critical Sinks (Abstract)

K.D. Boese , Computer Science Department, University of California at Los Angeles, Los Angeles, CA
pp. 182-187

The Sea-of-Wires Array Synthesis System (PDF)

Ing-Yi Chen , Dept. of Electronic Engr., Chung Yuan Christian University, Chungli, Taiwan, R.O.C.
pp. 188-193

Experiences in Functional Validation of a High Level Synthesis System (Abstract)

R. Vemuri , Laboratory for Digital Design Environments, Department of Electrical and Computer Engineering, University of Cincinnati, Cincinnati, OH
pp. 194-201

Performance Directed Technology Mapping for Look-Up Table Based FPGAs (Abstract)

P. Sawkar , Electrical and Computer Engineering Dept., Carnegie-Mellon University, Pittsburgh, PA
pp. 208-212

On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping (PDF)

Jason Cong , Department of Computer Science, University of California, Los Angeles, CA
pp. 213-218

MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs (Abstract)

M. Mehendale , Texas Instruments (India) Pvt. Ltd., Bangalore, INDIA
pp. 219-223

Sequential Synthesis for Table Look Up Programmable Gate Arrays (Abstract)

R. Murgai , Department of EECS, University of California, Berkeley, CA
pp. 224-229

Routability-Driven Fanout Optimization (Abstract)

H. Vaishnav , Department of EE - Systems, University of Southern California, Los Angeles, CA
pp. 230-235

Non-Scan Design-for-Testability Techniques for Sequential Circuits (Abstract)

V. Chickermane , Center for Reliable and High Performance Computing, University of Illinois, Urbana, IL
pp. 236-241

An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing (Abstract)

R. Srinivasan , Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
pp. 242-248

Partial Scan with Retiming (Abstract)

D. Kagaris , Computer Science Program, Dartmouth College, Hanover, NH
pp. 249-254

A Cost-Based Approach to Partial Scan (Abstract)

P.S. Parikh , AT&T Bell Laboratories, Naperville, IL; Illinois Institute of Technology, Chicago, IL
pp. 255-259

Reducing BDD Size by Exploiting Functional Dependencies (Abstract)

A.J. Hu , Department of Computer Science, Stanford University
pp. 266-271

Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems (Abstract)

S. Minato , NTT LSI Laboratories, Kanagawa Pref., JAPAN
pp. 272-277

Information Modelling of EDIF (Abstract)

R.Y.W. Lau , Department of Computer Science, University of Manchester, Manchester, UK
pp. 278-283

Panel: Life Expectancy of Standards (PDF)

S.R. Pollock , SRP Associates, Sunnyvale, CA
pp. 284

A Layout Estimation Algorithm for RTL Datapaths (Abstract)

M. Nourani , Department of Computer Engineering, Case Western Reserve University, Cleveland, OH
pp. 285-291

Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments (PDF)

Tien-Chien Lee , Department of Electrical Engineering, Princeton University, Princeton, NJ
pp. 292-297

Utilization of Multiport Memories in Data Path Synthesis (PDF)

Taewhan Kim , Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 298-302

Optimal Clustering for Delay Minimization (Abstract)

R. Rajaraman , Department of Computer Sciences, University of Texas at Austin, Austin, TX
pp. 309-314

Cost Minimization of Partitions into Multiple Devices (PDF)

R. Kuznar , Department of ECE, University of Ljubljana, Ljubljana, Slovenia
pp. 315-320

Iterative Wirability and Performance Improvement for FPGAs (PDF)

Sudip K. Nag , Dept. of Electrical Engineering, Carnegie-Mellon University, Pittsburgh, PA
pp. 321-325

On Routability Prediction for Field-Programmable Gate Arrays (Abstract)

P.K. Chan , Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA
pp. 326-330

The Clinton/Gore Technology Policies (Abstract)

R.D. Nurnberger , Conkling Fiskum & McCormick
pp. 331-335

High-Level Synthesis of Scalable Architectures for IIR Filters Using Multichip Modules (PDF)

Haigeng Wang , Department of Computer Science, University of California, Irvine, Irvine, CA
pp. 336-342

An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition (Abstract)

A. Chatterjee , School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA
pp. 343-348

InSyn: Integrated Scheduling for DSP Applications (Abstract)

A. Sharma , Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI
pp. 349-354

Estimating Architectural Resources and Performance for High-Level Synthesis Applications (PDF)

A. Sharms , Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI
pp. 355-360

Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering (Abstract)

B.S. Carlson , The Advanced IC Design and Simulation Laboratory and the Department of Electrical Engineering, State University of New York, Stony Brook, NY
pp. 361-366

Comparative Design Validation Based on Event Pattern Mappings (Abstract)

B.A. Gennart , NTT LSI Laboratories, Kanagawa, JAPAN
pp. 373-378

Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects (Abstract)

G.I. Stamoulis , University of Illinois at Urbana-Champaign, Department of Electrical and Computer Engineering and Coordinated Science Laboratory
pp. 379-383

Optimal Graph Constraint Reduction for Symbolic Layout Compaction (PDF)

Peichen Pan , Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 401-406

A Compaction Method for Full Chip VLSI Layouts (Abstract)

J. Dao , Semiconductor Device Engineering Lab., Toshiba Corporation, Kawasaki, Japan
pp. 407-412

High-Level Transformations for Minimizing Syntactic Variances (Abstract)

V. Chaiyakul , Department of Information and Computer Science, University of California, Irvine, CA
pp. 413-418

An Approach for Redesigning in Data Path Synthesis (Abstract)

C. Papachristou , Department of Computer Engineering, Case Western Reserve University, Cleveland, OH
pp. 419-423

High-level Symbolic Construction Techniques for High Performance Sequential Synthesis (Abstract)

A. Seawright , ECE Dept. University of California, Santa Barbara
pp. 424-428

High-Level Synthesis of Fault-Secure Microarchitectures (Abstract)

R. Karri , Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA
pp. 429-433

Towards Optimal System-Level Design (Abstract)

M.S. Haworth , Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MI
pp. 434-438

NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits (Abstract)

I. Pomeranz , Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA
pp. 439-445

Bridge Fault Simulation Strategies for CMOS Integrated Circuits (Abstract)

B. Chess , Computer Engineering Board of Studies, University of California, Santa Cruz
pp. 458-462

Minimum Length Synchronizing Sequences of Finite State Machine (PDF)

June-Kyung Rho , Department of Electrical and Computer Engineering, University of Colorado, Boulder
pp. 463-468

Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving (Abstract)

J.J. Joyce , Department of Computer Science, University of British Columbia, Vancouver, B.C., Canada
pp. 469-474

Panel: Are EDA Platform Preferences About to Shift (PDF)

W.S. Johnson , Sun Microsystems Computer Corp., Mountain View, CA
pp. 482

Sequential Circuit Delay Optimization Using Global Path Delays (Abstract)

S.T. Chakradhar , Computers and Communications Research Labs, NEC USA, Princeton, NJ
pp. 483-489

Resynthesis of Multi-Phase Pipelines (Abstract)

N.V. Shenoy , University of California - Berkeley CA
pp. 490-496

TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry (Abstract)

M.C. Papaefthymiou , MIT Laboratory for Computer Science, Cambridge, MA
pp. 497-502

Diagnosis and Correction of Logic Design Errors in Digital Circuits (PDF)

Pi-Yu Chung , Coordinated Science Lab. and Dept. of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign
pp. 503-508

DRAFTS: Discretized Analog Circuit Fault Simulator (Abstract)

N. Nagi , Computer Engg. Research Center, University of Texas at Austin, Austin, TX
pp. 509-514

Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy (Abstract)

W. Meyer , German National Research Center for Computer Science (GMD), Institute SET, St. Augustin, Germany
pp. 515-519

An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits (Abstract)

S. Chakravarty , Department of Computer Science, State University of New York, Buffalo, NY
pp. 520-524

A Buffer Distribution Algorithm for High-Speed Clock Routing (PDF)

Jun Dong Cho , Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL
pp. 537-543

Selective Pseudo Scan - Combinational Atpg with Reduced Scan in a Full Custom Risc Microprocessor (PDF)

G. Ganapathy , Embedded Products Division, Advanced Micro Devices, Austin, TX
pp. 550-555

ABLE: AMD Backplane for Layout Engines (Abstract)

K.W. Wan , CAD Technology and Systems, Advanced Micro Devices, Sunnyvale, CA
pp. 556-560

Practical Statistical Design of Complex Integrated Circuit Products (Abstract)

S.G. Duvall , Intel Corporation, Santa Clara, CA
pp. 561-565

Rotation Scheduling: A Loop Pipelining Algorithm (Abstract)

L. Chao , Department of Computer Science, Princeton University
pp. 566-572

Critical Path Minimization Using Retiming and Algebraic Speed-Up (Abstract)

Z. Iqbal , Dept. of EE - Systems, University of Southern California, Los Angeles, CA
pp. 573-577

A Tree-Based Scheduling Algorithm for Control-Dominated Circuits (Abstract)

S.H. Huang , Department of Computer Science, Taiwan Univ., Taipei, Taiwan
pp. 578-582

Synthesis of Pipelined Instruction Set Processors (Abstract)

R.J. Cloutier , Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
pp. 583-588

An Efficient Multilayer MCM Router Based on Four-Via Routing (PDF)

Kei-Yong Khoo , Department of Computer Science, University of California at Los Angeles, Los Angeles, CA
pp. 590-595

An Efficient Timing-Driven Global Routing Algorithm (PDF)

Jin Huang , Dept. of EECS, University of California at Berkeley, CA
pp. 596-600

A Negative Reinforcement Method for PGA Routing (Abstract)

F.D. Lewis , Department of Computer Science, University of Kentucky, Lexington, KY
pp. 601-605

Performance-Driven Interconnect Design Based on Distributed RC Delay Model (Abstract)

J. Cong , Department of Computer Science, University of California, Los Angeles, Los Angeles, CA
pp. 606-611

A Clustering-Based Optimization Algorithm in Zero-Skew Routings (Abstract)

M. Edahiro , Department of Computer Science, Princeton University, Princeton, NJ, USA and C&C Systems Research Laboratories, NEC Corporation, Kawasaki, Japan
pp. 612-616

Panel: Multi-vendor Tool Integration Experiences (PDF)

R. Collett , Collett International, Inc., Santa Clara, CA
pp. 617

ESPRESSO-SIGNATURE: A New Exact Minimizer for Logic Functions (Abstract)

P. McGeer , University of California at Berkeley, Berkeley, CA
pp. 618-624

A New Viewpoint on Two-Level Logic Minimization (Abstract)

O. Coudert , Bull Corporate Research Center, Les Clayes-sous-bois, FRANCE
pp. 625-630

Optimization of Combinational Logic Circuits Based on Compatible Gates (Abstract)

M. Damiani , Center for Integrated Systems, Stanford University, Stanford CA
pp. 631-636

Optimization and Resynthesis of Complex Data-Paths (Abstract)

H. Eveking , Johann Wolfgang Goethe-University Frankfurt, Frankfurt am Main, Germany
pp. 637-641

BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis (PDF)

Yung-Te Lai , Dept. of EE-Systems, Univ. of Southern California, Los Angeles, CA
pp. 642-647

Design Management Using Dynamically Defined Flows (Abstract)

P.R. Sutton , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
pp. 648-653

Active Documentation: a New Interface for VLSI Design (Abstract)

M.J. Silva , Computer Science Division, University of California, Berkeley, Berkeley, CA
pp. 654-660

Performance Specification Using Attributed Grammars (Abstract)

R. Mandayam , Laboratory for Digital Design Environments, Department of Electrical and Computer Engineering, University of Cincinnati, Cincinnati, OH
pp. 661-667

An Information Model of Time (Abstract)

C.A. Giumale , Computer Science Department, University of Manchester, Manchester, UK
pp. 668-672

A Cross-Debugging Method for Hardware/Software Co-design Environments (Abstract)

Y. Kra , Digital Equipment Corporation, Jerusalem, Israel
pp. 673-677

FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program (Abstract)

M. Kamon , Mass. Institute of Tech., Cambridge, MA
pp. 678-683

Fast Approximation of the Transient Response of Lossy Transmission Line Trees (PDF)

M. Sriram , Department of Electrical and Computer Engineering, Coordinated Science Laboratory and Beckman Institute, University of Illinois, Urbana, IL
pp. 691-696

Analysis and Reliable Design of ECL Circuits with Distributed RLC Interconnections (Abstract)

M. Haque , Department of Electrical and Computer Engineering, The University of Iowa, Iowa City, IA
pp. 697-701

Frequency Domain Microwave Modeling Using Retarded Partial Element Equivalent Circuits (Abstract)

H. Heeb , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 702-706

The State of CAD and VLSI in Russia (Abstract)

V. Yarnikh , Science & Research Center on Computer Technology. Moscow
pp. 707-708

The State of VHDL in Russia (Abstract)

Y. Tatarnikov , Information Systems Research Institute of Russia, Moscow
pp. 709-711

The State of Simulation in Russia (Abstract)

A. Birger , Almaz Corporation, Moscow
pp. 712-715

The State of EDA in Russian Universities (Abstract)

V.M. Mikhov , Department of Electronics and Computer Science, Moscow Institute of Electronic Engineering, Moscow, Russia
pp. 716-719

An Efficient Non-Quasi-Static Diode Model for Circuit Simulation (Abstract)

A.T. Yang , Department of Electrical Engineering, University of Washington, Seattle, WA
pp. 720-725

Addressing High-speed Interconnect Issues in Asymptotic Waveform Evaluation (Abstract)

E. Chiprout , Dept. of Electronics, Carleton University, Ottawa, Ontario, Canada
pp. 732-736

Incremental Event-Driven Simulation of Digital FET Circuits (Abstract)

C. Visweswariah , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 737-741

Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning (Abstract)

C.J. Alpert , Computer Science Department, University of California at Los Angeles, Los Angeles, CA
pp. 743-748

Spectral K-Way Ratio-Cut Partitioning and Clustering (PDF)

Pak K. Chan , Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA
pp. 749-754

A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design (Abstract)

J. Cong , Department of Computer Science, University of California, Los Angeles, Los Angeles, CA
pp. 755-760

Quadratic Boolean Programming for Performance-Driven System Partitioning (Abstract)

M. Shih , Department of EECS, University of California, Berkeley, CA
pp. 761-765

Panel: The Key to EDA Results: Component & Library Management (PDF)

R. Wadhwani , Aspect Development, Inc., Los Altos, CA
pp. 766
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