The Community for Technology Leaders
Design Automation Conference (1992)
Anaheim, CA, USA
June 12, 1992 to June 15, 1992
ISBN: 0-8186-2822-7
TABLE OF CONTENTS
Papers

The role of long and short paths in circuit performance optimization (PDF)

Cheng , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Du , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Chen , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 543-548

FARM: an efficient feed-through pin assignment algorithm (PDF)

Hong , California Univ., Berkeley, CA, USA
Huang , California Univ., Berkeley, CA, USA
pp. 530-535

Power and ground network topology optimization for cell based VLSIs (PDF)

Kuh , Electron. Res. Lab., California Univ., Berkeley, CA, USA
Mitsuhashi , Electron. Res. Lab., California Univ., Berkeley, CA, USA
pp. 524-529

Zero skew clock net routing (PDF)

Chao , ITRI, Hsin-Chu, Taiwan
pp. 518-523

Application-driven design automation for microprocessor design (PDF)

Pyo , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Cheng , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Koh , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Despain , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Tsui , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Liu , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Wu , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Chen , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Huang , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Pan , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Su , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 512-517

Automated design decision support system (PDF)

Beggs , Boeing Helicopters, Philadelphia, PA, USA
pp. 506-511

Design process management for CAD frameworks (PDF)

Jacome , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Director , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 500-505

A near optimal algorithm for technology mapping minimizing area under delay constraints (PDF)

Chaudhary , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 492-498

LATTIS: an iterative speedup heuristic for mapped logic (PDF)

Fishburn , AT&T Bell Labs., Murray Hill, NJ, USA
pp. 488-491

BDDMAP: a technology mapper based on a new covering algorithm (PDF)

Nix , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Kung , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Damiano , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 484-487

On the circuit implementation problem (combinatorial logic circuits) (PDF)

Li , Dept. of Comput. Sci., Arkansas Univ., AR, USA
pp. 478-483

IPDA: interconnect performance design assistant (PDF)

Change , Hewlett-Packard Co., Palo Alto, CA, USA
Chang , Hewlett-Packard Co., Palo Alto, CA, USA
Leo , Hewlett-Packard Co., Palo Alto, CA, USA
Lee , Hewlett-Packard Co., Palo Alto, CA, USA
Oh , Hewlett-Packard Co., Palo Alto, CA, USA
pp. 472-477

Tools to aid in wiring rule generation for high speed interconnects (PDF)

Steer , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Franzon , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Simovich , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Mehrotra , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Basel , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Mills , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 466-471

Challenges and advances in electrical interconnect analysis (PDF)

Heeb , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Ruehli , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 460-465

Test-set preserving logic transformations (PDF)

Hayes , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Batek , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 454-458

Optimization of primitive gate networks using multiple output two-level minimization (PDF)

Malik , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 449-453

Efficient sum-to-one subsets algorithm for logic optimization (PDF)

Chen , Fujitsu America Inc., San Jose, CA, USA
pp. 443-448

Coalgebraic division for multilevel logic synthesis (PDF)

Wen-Jun Hsu , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Wen-Zen Shen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 438-442

HLSIM-a new hierarchical logic simulator and netlist converter (PDF)

Engel , IBM, Hopewell Junction, NY, USA
Zein , IBM, Hopewell Junction, NY, USA
pp. 432-437

Performance evaluation of an event-driven logic simulation machine (PDF)

Hirose , Fujitsu Laboratories Ltd., Kawasaki, Japan
pp. 428-431

Zero delay versus positive delay in an incremental switch-level simulator (PDF)

Jones , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 424-427

Two new techniques for compiled multi-delay logic simulation (PDF)

Maurer , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Lee , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 420-423

An approach to symbolic timing verification (PDF)

Boriello , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
Amon , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 410-413

On the temporal equivalence of sequential circuits (PDF)

Shenoy , California Univ., Berkeley, CA, USA
Singh , California Univ., Berkeley, CA, USA
Brayton , California Univ., Berkeley, CA, USA
Sangiovanni-Vincentelli , California Univ., Berkeley, CA, USA
pp. 405-409

Computing optimal clock schedules (PDF)

Szymanski , AT&T Bell Labs., Murray Hill, NJ, USA
pp. 399-404

Analyzing cycle stealing on synchronous circuits with level-sensitive latches (PDF)

Eng , IBM Corp., Kingston, NY, USA
Lin , IBM Corp., Kingston, NY, USA
Ludwig , IBM Corp., Kingston, NY, USA
pp. 393-398

An improved synthesis algorithm for multiplexor-based PGAs (PDF)

Murgai , California Univ., Berkeley, CA, USA
Brayton , California Univ., Berkeley, CA, USA
Sangiovanni-Vincentelli , California Univ., Berkeley, CA, USA
pp. 380-386

Characterization of Boolean functions for rapid matching in EPGA technology mapping (PDF)

Schlichtmann , Inst. of Electron. Design Autom., Tech. Univ. of Munich, Germany
pp. 374-379

Area and delay mapping for table-look-up based field programmable gate arrays (PDF)

Sawkar , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
Thomas , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 368-373

TEMPT: technology mapping for the exploration of FPGA architectures with hard-wired connections (PDF)

Chung , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
Rose , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
pp. 361-367

A novel approach to delay-fault diagnosis (PDF)

Girard , Lab. d'Inf. de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, France
Landrault , Lab. d'Inf. de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, France
Pravossoudovitch , Lab. d'Inf. de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, France
pp. 357-360

Algorithms for current monitor based diagnosis of bridging and leakage faults (PDF)

Chakravarty , Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
pp. 353-356

Exact evaluation of diagnostic test resolution (PDF)

Fuchs , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
Saleh , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
Kubiak , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
Parkes , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 347-352

On the distribution of fault coverage and test length in random testing of combinational circuits (PDF)

Majumdar , Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
pp. 341-346

HOPE: an efficient parallel fault simulator (PDF)

Lee , Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Ha , Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 336-340

Concurrent fault simulation of logic gates and memory blocks on message passing multicomputers (PDF)

Agrawal , AT&T Bell Labs., Murray Hill, NJ, USA
Bose , AT&T Bell Labs., Murray Hill, NJ, USA
pp. 332-335

On efficient concurrent fault simulation for synchronous sequential circuits (PDF)

Reddy , Iowa Univ., Iowa City, IA, USA
Lee , Iowa Univ., Iowa City, IA, USA
pp. 327-331

A new hierarchical layout compactor using simplified graph models (PDF)

Wonjong Kim , Dept. of Electron. Eng., Hanyang Univ., Seoul, South Korea
pp. 323-326

Process independent constraint graph compaction (PDF)

Boyer , Bellcore, Red Bank, NJ, USA
pp. 318-322

Hierarchical pitchmatching compaction using minimum design (PDF)

Varadarajan , Cadence Design Systems, San Jose, CA, USA
Bamji , Cadence Design Systems, San Jose, CA, USA
pp. 311-317

An interpreter for general netlist design rule checking (PDF)

Pelz , Fraunhofer-Inst. of Microelectron. Circuits & Syst., Duisburg, Germany
pp. 305-310

Hcompare: a hierarchical netlist comparison program (PDF)

Cooke , Sun MicroSystems, Mountain View, CA, USA
Batra , Sun MicroSystems, Mountain View, CA, USA
pp. 299-304

Functional synthesis using area and delay optimization (PDF)

Gajski , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Rundensteiner , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 291-296

ISIS: a system for performance driven resource sharing (PDF)

MacMillen , Synopsys, Inc., Mountain View, CA, USA
Fogg , Synopsys, Inc., Mountain View, CA, USA
Gregory , Synopsys, Inc., Mountain View, CA, USA
pp. 285-290

Data path allocation using an extended binding model (PDF)

Krishnamoorthy , Mentor Graphics Corp., Warren, NJ, USA
pp. 279-284

Automatic test knowledge extraction from VHDL (ATKET) (PDF)

Vishakantaiah , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
Abraham , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 273-278

Multipole-accelerated 3-D capacitance extraction algorithms for structures with conformal dielectrics (PDF)

White , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
Nabors , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 710-715

An integrated approach to realistic worst-case design optimization of MOS analog circuits (PDF)

Dharchoudhury , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Kang , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 704-709

A mixed-integer nonlinear programming approach to analog circuit synthesis (PDF)

Maulik , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Carley , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Rutenbar , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 698-703

Experiments with a performance driven module generator (PDF)

Kim , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
Owens , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
Irwin , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
pp. 687-690

Routing considerations in symbolic layout synthesis (PDF)

Liao , Cadence Design Systems, Inc., San Jose, CA, USA
Chow , Cadence Design Systems, Inc., San Jose, CA, USA
pp. 682-686

An efficient routing algorithm for SOG cell generation on a dense gate-isolated layout style (PDF)

Okuda , Mitsubishi Electric Corp., Hyogo, Japan
Oguri , Mitsubishi Electric Corp., Hyogo, Japan
pp. 676-681

CAD Framework Initiative-a user perspective (PDF)

Scallan , IBM Corp., Kingston, NY, USA
pp. 672-675

The Electronic Design Interchange Format EDIF: present and future (PDF)

Kahn , Dept. of Comput. Sci., Manchester Univ., UK
pp. 666-671

Transformation-based high-level synthesis of fault-tolerant ASICs (PDF)

Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
Karri , Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
pp. 662-665

Control optimization in high-level synthesis using behavioral don't cares (PDF)

Bergamaschi , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 657-661

An efficient algorithm for microword length minimization (PDF)

Puri , Dept. of Electr. Eng., Calgary Univ., Alta., Canada
Gu , Dept. of Electr. Eng., Calgary Univ., Alta., Canada
pp. 651-656

Distributed design-space exploration for high-level synthesis systems (PDF)

Dutta , Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
Roy , Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
Vemuri , Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
pp. 644-650

Superpipelined control and data path synthesis (PDF)

Prabhu , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
Pangrle , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
pp. 638-643

The automatic generation of bus-interface models (PDF)

Birmingham , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Leong , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 634-637

Inductive verification of iterative systems (PDF)

Somenzi , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
Rho , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 628-633

Functional approaches to generating orderings for efficient symbolic representations (PDF)

Kapur , Texas Univ., Austin, TX, USA
Mercer , Texas Univ., Austin, TX, USA
pp. 624-627

Exact calculation of synchronization sequences based on binary decision diagrams (PDF)

Pixley , Mitsubishi Electric Res. Lab. Inc., Cambridge, MA, USA
pp. 620-623

A new model for improving symbolic product machine traversal (PDF)

Sonza Reorda , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
Gai , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
Cabodi , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
Camurati , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
Corno , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
Prinetto , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 614-619

Edge-valued binary decision for multi-level hierarchical verification (PDF)

Lai , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Sastry , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 608-613

Over-the-cell routers for new cell model (PDF)

Sherwani , Western Michigan Univ., Kalamazoo, MI, USA
Wu , Western Michigan Univ., Kalamazoo, MI, USA
pp. 604-607

Over-the-cell channel routing for high performance circuits (PDF)

Sherwani , Western Michigan Univ., Kalamazoo, MI, USA
Natarajan , Western Michigan Univ., Kalamazoo, MI, USA
pp. 600-603

A pin permutation algorithm for improving over-the-cell channel routing (PDF)

Chen , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
Hou , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 594-599

New models for four- and five-layer channel routing (PDF)

Ho , Dept. of Math. Comput. Sci. & Stat., McNeese State Univ., Lake Charles, LA, USA
pp. 589-593

A multi-layer channel router with new style of over-the-cell routing (PDF)

Mima , NEC Corp., Kanagawa, Japan
Fujii , NEC Corp., Kanagawa, Japan
Yoshimura , NEC Corp., Kanagawa, Japan
Matsuda , NEC Corp., Kanagawa, Japan
pp. 585-588

A new efficient approach to multilayer channel routing problem (PDF)

Shian-Lang Lee , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Wu-Shiung Feng , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Sung-Chuan Fang , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 579-584

State assignment using input/output functions (PDF)

Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 573-577

Solving the state assignment problem for signal transition graphs (PDF)

Moon , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Lavagno , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 568-572

Recurrence equations and the optimization of synchronous logic circuits (PDF)

De Micheli , Center for Integrated Syst., Stanford Univ., CA, USA
Damiani , Center for Integrated Syst., Stanford Univ., CA, USA
pp. 556-561

A methodology to reduce the computational cost of behavioral test pattern generation (PDF)

Santucci , Lab. d'Etudes et de Recherche en Inf., Nimes, France
Dray , Lab. d'Etudes et de Recherche en Inf., Nimes, France
Giambiasi , Lab. d'Etudes et de Recherche en Inf., Nimes, France
Boumedine , Lab. d'Etudes et de Recherche en Inf., Nimes, France
pp. 267-272

Hierarchical test generation under intensive global functional constraints (PDF)

Patel , Center for Reliable & High-Performance Comput., Illinois Univ., Urbana, IL, USA
Lee , Center for Reliable & High-Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 261-266

Circuit enhancement by eliminating long false paths (PDF)

Du , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Chen , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Cheng , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 249-252

Circuit structure relations to redundancy and delay: the KMS algorithm revisited (PDF)

Brayton , California Univ., Berkeley, CA, USA
Saldanha , California Univ., Berkeley, CA, USA
Sangiovanni-Vincentelli , California Univ., Berkeley, CA, USA
pp. 245-248

A path-oriented approach for reducing hazards in asynchronous designs (PDF)

Yu , AT&T Bell Lab., Holmdel, NJ, USA
Subrahmanyam , AT&T Bell Lab., Holmdel, NJ, USA
pp. 239-244

Partitioning by regularity extraction (PDF)

Kurdahi , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
Rao , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
pp. 235-238

High-level synthesis with pin constraints for multiple-chip designs (PDF)

Hung , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Parker , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 231-234

Synthesis and simulation of digital systems containing interacting hardware and software components (PDF)

Gupta , Center for Integrated Syst., Stanford Univ., CA, USA
De Micheli , Center for Integrated Syst., Stanford Univ., CA, USA
Coelho , Center for Integrated Syst., Stanford Univ., CA, USA
pp. 225-230

Specification partitioning for system design (PDF)

Gajski , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Vahid , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 219-224

AWEsymbolic: compiled analysis of linear(ized) circuits using asymptotic waveform evaluation (PDF)

Rohrer , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Lee , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 213-218

On the stability of moment-matching approximations in asymptotic waveform evaluation (PDF)

Pillage , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
Gopal , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
Anastasakis , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
Kim , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 207-212

Generalized moment-matching methods for transient analysis of interconnect networks (PDF)

Chiprout , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Nakhla , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
pp. 201-206

Synthesis from production-based specifications (PDF)

Seawright , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Brewer , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 194-199

High-level synthesis from VHDL with exact timing constraints (PDF)

Duzy , Siemens AG, Munchen, Germany
Stoll , Siemens AG, Munchen, Germany
pp. 188-193

The Princeton University behavioral synthesis system (PDF)

Manno , Dept. of Electr. Eng., Princeton Univ., NJ, USA
Wu , Dept. of Electr. Eng., Princeton Univ., NJ, USA
Takach , Dept. of Electr. Eng., Princeton Univ., NJ, USA
Huang , Dept. of Electr. Eng., Princeton Univ., NJ, USA
Wolf , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 182-187

At-speed delay testing of synchronous sequential circuits (PDF)

Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 177-181

Equivalence of robust delay-fault and single stuck-fault test generation (PDF)

Sangiovanni-Vincentelli , California Univ., Berkeley, CA, USA
Saldanha , California Univ., Berkeley, CA, USA
Brayton , California Univ., Berkeley, CA, USA
pp. 173-176

Fuzzy logic approach to placement problem (PDF)

Shragowitz , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Lin , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 153-158

A performance driven macro-cell placement algorithm (PDF)

Vaidya , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Liu , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Gao , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 147-152

APT: an area-performance-testability driven placement algorithm (PDF)

Kim , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
Banerjee , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
Chickermane , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
Patel , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 141-146

High level synthesis of pipelined instruction set processors and back-end compilers (PDF)

Huang , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Despain , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 135-140

An engineering environment for hardware/software co-simulation (PDF)

Becker , Dept. of Comput. Sci., North Carolina Univ., Chapel Hill, NC, USA
Tell , Dept. of Comput. Sci., North Carolina Univ., Chapel Hill, NC, USA
Singh , Dept. of Comput. Sci., North Carolina Univ., Chapel Hill, NC, USA
pp. 129-134

Time constrained allocation and assignment techniques for high throughput signal processing (PDF)

Catthoor , IMEC, Leuven, Belgium
Geurts , IMEC, Leuven, Belgium
De Man , IMEC, Leuven, Belgium
pp. 124-127

Optimal allocation and binding in high-level synthesis (PDF)

Rim , Wisconsin Univ., Madison, WI, USA
Jain , Wisconsin Univ., Madison, WI, USA
De Leone , Wisconsin Univ., Madison, WI, USA
pp. 120-123

Optimal scheduling and allocation of embedded VLSI chips (PDF)

Gebotys , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
pp. 116-119

Representing conditional branches for high-level synthesis applications (PDF)

Rim , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Jain , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 106-111

Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems (PDF)

Papachristou , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
Nourani , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 99-105

AWESpice: a general tool for the accurate and efficient simulation of interconnect problems (PDF)

Bracken , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Rohrer , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Raghavan , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 87-92

Transient simulation of lossy interconnect (PDF)

Kuh , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Lin , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 81-86

Simulating lossy interconnect with high frequency nonidealities in linear time (PDF)

Pederson , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Roychowdhury , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Newton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 75-80

Canonical embedding of rectangular duals with applications to VLSI floorplanning (PDF)

Bhattacharya , Indian Stat. Inst., Calcutta, India
Sur-Kolay , Indian Stat. Inst., Calcutta, India
pp. 69-74

A graph theoretic technique to speed up floorplan area optimization (PDF)

Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Wang , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 62-68

A wire length estimation technique utilizing neighborhood density equations (PDF)

Cheng , California Univ., San Diego, La Jolla, CA, USA
Chau , California Univ., San Diego, La Jolla, CA, USA
Hamada , California Univ., San Diego, La Jolla, CA, USA
pp. 57-61

Performance-driven system partitioning on multi-chip modules (PDF)

Shih , California Univ., Berkeley, CA, USA
Kuh , California Univ., Berkeley, CA, USA
pp. 53-56

Net partitions yield better module partitions (PDF)

Kahng , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Hagen , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 47-52

FPGA design principles (PDF)

Hill , AT&T Bell Labs., Naperville, IL, USA
pp. 45-46

Symbolic prime generation for multiple-valued functions (PDF)

Lin , California Univ., Berkeley, CA, USA
pp. 40-44

Implicit and incremental computation of primes and essential primes of Boolean functions (PDF)

Madre , Bull Corporate Res. Center, Les Clayes-sous-bois, France
Coudert , Bull Corporate Res. Center, Les Clayes-sous-bois, France
pp. 36-39

Fast exact and quasi-minimal minimization of highly testable fixed-polarity AND/XOR canonical networks (PDF)

Perkowski , Dept. of Electr. Eng., Portland State Univ., OR, USA
Sarabi , Dept. of Electr. Eng., Portland State Univ., OR, USA
pp. 30-35

SWiTEST: a switch level test generation system for CMOS combinational circuits (PDF)

Lee , Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan
pp. 26-29

On the over-specification problem in sequential ATPG algorithms (PDF)

Cheng , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 16-21

Parallel waveform relaxation of circuits with global feedback loops (PDF)

Johnson , IBM Thomas J. Watson Res. Centre, Yorktown Heights, NY, USA
Ruehli , IBM Thomas J. Watson Res. Centre, Yorktown Heights, NY, USA
pp. 12-15

Incremental circuit simulation using waveform relaxation (PDF)

Saleh , Illinois Univ., Urbana, IL, USA
Ju , Illinois Univ., Urbana, IL, USA
pp. 8-11

Maximum current estimation in CMOS circuits (PDF)

Kriplani , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 2-7
104 ms
(Ver )