Reviewers (PDF)

Cost constrained optimal architectural synthesis (PDF)

Synthesis of application-specific multiprocessor architectures (Abstract)

Constraint improvements for MILP-based hardware synthesis (Abstract)

ILLIADS: a new fast MOS timing simulator using direct equation-solving approach (Abstract)

ADAPTS: a digital transient simulation strategy for integrated circuits (Abstract)

Efficient simulation of bipolar digital ICs (Abstract)

Topological routing in SURF: generating a rubber-band sketch (Abstract)

Novel routing schemes for IC layout part I: two-layer channel routing (Abstract)

A new hypergraph based rip-up and reroute strategy (Abstract)

Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems (PDF)

Logic synthesis for efficient pseudoexhaustive testability (Abstract)

Correlation-reduced scan-path design to improve delay fault coverage (PDF)

The interdependence between delay-optimization of synthesized networks and testing (Abstract)

A technology mapping method based on perfect and semi-perfect matchings (Abstract)

Channel density reduction by routing over the cells (Abstract)

New algorithm for over-the-cell channel routing using vacant terminals (Abstract)

Algorithms for fast, memory efficient switch-level fault simulation (Abstract)

A system for fault diagnosis and simulation of VHDL descriptions (Abstract)

Sequential circuit fault simulation by fault information tracing algorithm : FIT (Abstract)

Parallel test generation for sequential circuits on general-purpose multiprocessors (Abstract)

Creator: general and efficient multilevel concurrent fault simulation (Abstract)

On removing redundancy in sequential circuits (PDF)

A framework for satisfying input and output encoding constraints (PDF)

A unified approach to input-output encoding for FSM state assignment (Abstract)

FSM decomposition revisited: algebraic structure theory applied to MCNC benchmark FSMs (Abstract)

A CAD system for the design of field programmable gate arrays (Abstract)

Basic concepts of timing-oriented design automation for high-performance mainframe computers (Abstract)

SIDECAR design support for reliability (Abstract)

Automatic generation of compiled simulations through program specialization (PDF)

Accelerating switch-level simulation by function caching (Abstract)

Utilizing logic information in multi-level timing simulation (Abstract)

Mapping switch-level simulation onto gate-level hardware accelerators (PDF)

Breaking the barrier of parallel simulation of digital systems (Abstract)

Chortle-crf: fast technology mapping for lookup table-based FPGAs (Abstract)

Technology mapping for electrically programmable gate arrays (Abstract)

Xmap: a technology mapper for table-lookup field-programmable gate arrays (Abstract)

Amap: a technology mapper for selector-based field-programmable gate arrays (Abstract)

A heuristic method for FPGA technology mapping based on the edge visibility (PDF)

Timing- and constraint-oriented placement for interconnected LSIs in mainframe design (Abstract)

Object oriented lisp implementation of the CHEOPS VLSI floor planning and routing system (Abstract)

Benchmarks for layout synthesis - evolution and current status (PDF)

A design for testability scheme with applications to data path synthesis (Abstract)

Enhanced controllability for IDDQ test sets using partial scan (Abstract)

ATPG based on a novel grid-addressable latch element (Abstract)

Graph partitioning for concurrent test scheduling in VLSI circuit (Abstract)

Delay test effectiveness evaluation of LSSD-Based VLSI logic circuits (Abstract)

Automatic synthesis of asynchronous circuits (PDF)

Algorithms for synthesis of hazard-free asynchronous circuits (Abstract)

Synthesis of multiple-input change asynchronous finite state machines (Abstract)

A global router using an efficient approximate multicommodity multiterminal flow algorithm (Abstract)

High-performance clock routing based on recursive geometric matching (Abstract)

On minimizing the number of L-shaped channels (PDF)

A general multi-layer area router (Abstract)

On achieving a complete fault coverage for sequential machines using the transition fault model (Abstract)

A transitive closure based algorithm for test generation (Abstract)

A synthesis-based test generation and compaction algorithm for multifaults (Abstract)

Control optimization based on resynchronization of operations (Abstract)

A unified approach for the synthesis of self-testable finite state machines (Abstract)

A data path synthesis method for self-testable designs (Abstract)

Automated micro-roll-back self-recovery synthesis (Abstract)

Proof-aided design of verified hardware (Abstract)

Formal hardware verification by symbolic ternary trajectory evaluation (Abstract)

Representing circuits more efficiently in symbolic model checking (Abstract)

Breadth-first manipulation of SBDD of boolean functions for vector processing (Abstract)

A general purpose multiple way partitioning algorithm (PDF)

Analytical placement: a linear or a quadratic objective function? (Abstract)

Branch-and-bound placement for building block layout (Abstract)

A probabilitistic testability measure for delay faults (PDF)

Testability of asynchronous timed control circuits with delay assumptions (Abstract)

A branching process model for observability analysis of combinational circuits (Abstract)

A resynthesis approach for network optimization (PDF)

Logic minimization using two-column rectangle replacement (PDF)

An efficient layout style for 2-metal CMOS leaf cells and their automatic generation (PDF)

Exact width and height minimization of CMOS cells (Abstract)

Optimal ordering of analog integrated circuit tests to minimize test time (Abstract)

Generation of performance sensitivities for analog cell layout (Abstract)

A constraint based approach to automatic design of analog cells (Abstract)

A layout improvement method based on constraint propagation for analog LSI's (Abstract)

CHOP: a constraint-driven system-level partitioner (PDF)

Industrial extensions to university high level synthesis tools: making it work in the real world (Abstract)

Bridging high-level slqvihesis to RTL technology libraries (PDF)

The effects of physical design characteristics on the area - performance tradeoff curve (Abstract)

An efficient parallel critical path algorithm (PDF)

Incremental techniques for the identification of statically sensitizable critical paths (PDF)

Critical path selection for performance optirnization (PDF)

Timing verification on a 1.2M-device full-custom CMOS design (PDF)

RICE: rapid interconnect circuit evaluator (Abstract)

A new nonlinear driver model for interconnect analysis (Abstract)

Propagation delay calculation for interconnection nets on printed circuit boards by reflected waves (Abstract)

GOALSERVER: a multiobjective design optimization tool for IC fabrication process (PDF)

Data-path synthesis using path analysis (Abstract)

Cathedral-III : architecture-driven high-level synthesis for high throughput DSP applications (Abstract)

Relevant issues in high-level connectivity synthesis (Abstract)

The role of timing verification in layout synthesis (Abstract)

An analytic net weighting approach for performance optimization in circuit placement (PDF)

A fast physical constraint generator for timing priven layout (PDF)

Dynamic prediction of critical paths and nets for constructive timing-driven placement (PDF)

An algorithm for performance-driven initial placement of small-cell ICs (Abstract)

Placement for clock period minimization with multiple wave propagation (Abstract)

Transition density, a stochastic measure of activity in digital circuits (Abstract)

Probabilistic CTSS: analysis of timing error probability in asynchronous logic circuits (Abstract)

CLOVER: a timing constraints verification system (Abstract)

3D scheduling: high-level synthesis with floorplanning (PDF)

Fast and near optimal scheduling in automatic data path synthesis (PDF)

Empirical evaluation of some high-level synthesis scheduling heuristics (PDF)

Sizing synchronization queues: a case study in higher level synthesis (Abstract)

The MCC CAD framework methodology management system (Abstract)

A configuration management system in a data management framework (Abstract)

Design version management in the GARDEN framework (Abstract)

Design flow management in the NELSIS CAD framework (Abstract)

REX - A VLSI parasitic extraction tool for electromigration and signal analysis (Abstract)

A new approach to hierarchical adaptation using sequence-control based on cell interactions (Abstract)

A two-dimensional topological compactor with octagonal geometry (Abstract)

On minimal closure constraint generation for symbolic cell assembly (PDF)

Efficient transient simulation of lossy interconnect (Abstract)

A transmission line simulator for GaAs integrated circuits (Abstract)

Modeling and simulation of higb-frequency integrated circuits based on scattering parameters (PDF)

Minimizing the number of delay buffers in the synchronization of pipelined systems (Abstract)

Scheduling for functional pipelining and loop winding (PDF)

Incremental tree height reduction for high level synthesis (Abstract)

Redundant operator creation: a scheduling optimization technique (Abstract)

Author index (PDF)