The Community for Technology Leaders
28th ACM/IEEE Design Automation Conference (1991)
San Francisco, California, USA
June 17, 1991 to June 21, 1991
ISBN: 0-89791-395-7

Reviewers (PDF)

pp. xi,xii,xiii

Efficient simulation of bipolar digital ICs (Abstract)

C. Visweswariah , Carnegie Mellon University
pp. 32-37

Routability of a rubber-band sketch (Abstract)

W.W.-M. Dai , University of California
pp. 45-48

A new hypergraph based rip-up and reroute strategy (Abstract)

M. Raith , Ludwig-Maximilians-University
pp. 54-59

A technology mapping method based on perfect and semi-perfect matchings (Abstract)

M. Crastes , Institut National Polytechnique de Grenoble / CSI
pp. 93-98

Layout driven technology mapping (Abstract)

M. Pedram , University of California
pp. 99-105

An ECL logic synthesis system (Abstract)

V. Morgan , Synopsys, Inc.
pp. 106-111

Routing the 3-D chip (Abstract)

R.J. Enbody , Michigan State University
pp. 132-137

SIDECAR design support for reliability (Abstract)

C.R. Yount , Carnegie Mellon University
pp. 199-204

Accelerating switch-level simulation by function caching (Abstract)

L.G. Jonesi , University of Illinois at Urbana-Champaign
pp. 211-214

Breaking the barrier of parallel simulation of digital systems (Abstract)

J.V. Briner , University of North Carolina at Greensboro
pp. 223-226

Benchmarks for layout synthesis - evolution and current status (PDF)

K. Kozminski , MCNC Center for Microelectronics
pp. 265-270

On minimizing the number of L-shaped channels (PDF)

Yang Cai , University of Texas at Austin
pp. 328-334

A general multi-layer area router (Abstract)

M. Guruswamy , The University of Texas at Austin
pp. 335-340

Automated micro-roll-back self-recovery synthesis (Abstract)

V. Raghavendra , University of Southwestern Louisiana
pp. 385-390

Proof-aided design of verified hardware (Abstract)

H. Busch , Siemens AG, Corporate Research and Development
pp. 391-396

Using bdds to verify multipliers (Abstract)

J.R. Burch , Carnegie Mellon University
pp. 408-412

Logic optimization of MOS networks (Abstract)

J.C. Limqueco , University of Illinois
pp. 464-469

Flexible transistor matrix (FTM) (Abstract)

K.C. Ho , University of Southern California
pp. 475-480

CHOP: a constraint-driven system-level partitioner (PDF)

K. Kucukcakar , University of Southern California
pp. 514-519

RICE: rapid interconnect circuit evaluator (Abstract)

C.L. Ratzlaff , The University of Texas at Austin
pp. 555-560

A new nonlinear driver model for interconnect analysis (Abstract)

V. Raghavan , Carnegie Mellon University
pp. 561-566

Data-path synthesis using path analysis (Abstract)

R.A. Bergamaschi , Thomas J. Watson Research Center
pp. 591-596

The role of timing verification in layout synthesis (Abstract)

J. Benkoski , Carnegie Mellon University
pp. 612-619

A fast physical constraint generator for timing priven layout (PDF)

W.K. Luk , IBM Thomas J. Watson Research Center
pp. 626-631

OEsim: a simulator for timing behavior (Abstract)

T. Amon , University of Washington
pp. 656-661

Bottom up synthesis based on fuzzy schedules (Abstract)

T.A. Ly , University of Alberta
pp. 674-679

Fast and near optimal scheduling in automatic data path synthesis (PDF)

In-Cheol Park , Korea Advanced Institute of Science and Technology
pp. 680-685

The MCC CAD framework methodology management system (Abstract)

W. Allen , Microelectronics and Computer Technology Corporation
pp. 694-698

Redundant operator creation: a scheduling optimization technique (Abstract)

D.A. Lobo , The Pennsylvania State University
pp. 775-778

Author index (PDF)

pp. 781-783
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