The Community for Technology Leaders
Design Automation Conference (1991)
San Francisco, California
June 21, 1991 to June 21, 1991
ISBN: 0-89791-395-7
TABLE OF CONTENTS
Papers

Reviewers (PDF)

pp. xi-xiii

Routability of a rubber-band sketch (PDF)

Dai , University of California
pp. 45-48

A technology mapping method based on perfect and semi-perfect matchings (PDF)

Crastes , Institut National Polytechnique de Grenoble / CSI
pp. 93-98

Layout driven technology mapping (PDF)

Pedram , University of California
pp. 99-105

An ECL logic synthesis system (PDF)

Morgan , Synopsys, Inc.
pp. 106-111

Routing the 3-D chip (PDF)

Enbody , Michigan State University
pp. 132-137

SIDECAR design support for reliability (PDF)

Yount , Carnegie Mellon University
pp. 199-204

Accelerating switch-level simulation by function caching (PDF)

Jonesi , University of Illinois at Urbana-Champaign
pp. 211-214

Breaking the barrier of parallel simulation of digital systems (PDF)

Briner , University of North Carolina at Greensboro
pp. 223-226

Benchmarks for layout synthesis - evolution and current status (PDF)

Kozminski , MCNC Center for Microelectronics
pp. 265-270

On minimizing the number of L-shaped channels (PDF)

Yang Cai , University of Texas at Austin
pp. 328-334

A general multi-layer area router (PDF)

Guruswamy , The University of Texas at Austin
pp. 335-340

Automated micro-roll-back self-recovery synthesis (PDF)

Raghavendra , University of Southwestern Louisiana
pp. 385-390

Proof-aided design of verified hardware (PDF)

Busch , Siemens AG, Corporate Research and Development
pp. 391-396

Sing BDDs to verify multipliers (PDF)

Burch , Carnegie Mellon University
pp. 408-412

Logic optimization of MOS networks (PDF)

Limqueco , University of Illinois
pp. 464-469

Flexible transistor matrix (FTM) (PDF)

Ho , University of Southern California
pp. 475-480

CHOP: a constraint-driven system-level partitioner (PDF)

Kucukcakar , University of Southern California
pp. 514-519

RICE: rapid interconnect circuit evaluator (PDF)

Ratzlaff , The University of Texas at Austin
pp. 555-560

Data-path synthesis using path analysis (PDF)

Bergamaschi , Thomas J. Watson Research Center
pp. 591-596

A fast physical constraint generator for timing priven layout (PDF)

Luk , IBM Thomas J. Watson Research Center
pp. 626-631

OEsim: a simulator for timing behavior (PDF)

Amon , University of Washington
pp. 656-661

3D scheduling: high-level synthesis with floorplanning (PDF)

Jen-Pin Weng , University of Southern California
pp. 668-673

Bottom up synthesis based on fuzzy schedules (PDF)

Ly , University of Alberta
pp. 674-679

Fast and near optimal scheduling in automatic data path synthesis (PDF)

In-Cheol Park , Korea Advanced Institute of Science and Technology
pp. 680-685

The MCC CAD framework methodology management system (PDF)

Allen , Microelectronics and Computer Technology Corporation
pp. 694-698

Author Index (PDF)

pp. 781-783
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