The Community for Technology Leaders
Design Automation Conference (1990)
Orlando, FL, USA
June 24, 1990 to June 28, 1990
ISBN: 0-89791-363-9
TABLE OF CONTENTS
Papers

The VHDL validation suite (PDF)

Cho , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Armstrong , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Kosaraju , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Shah , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 2-7

An intermediate representation for behavioral synthesis (PDF)

Gajski , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Hadley , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Dutt , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 14-19

Optimization by simulated evolution with applications to standard cell placement (PDF)

Banerjee , Center for Reliable & High-Performance Comput., Illinois Univ., Urbana, IL, USA
King , Center for Reliable & High-Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 20-25

Stochastic evolution: a fast effective heuristic for some generic layout problems (PDF)

Rao , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Saab , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 26-31

Integrated placement for mixed macro cell and standard cell designs (PDF)

Upton , Seattle Silicon Corp., WA, USA
Sugiyama , Seattle Silicon Corp., WA, USA
Samii , Seattle Silicon Corp., WA, USA
pp. 32-35

A new simultaneous partitioning and chip placement approach based on simulated annealing (PDF)

Hartley , Gen. Electr. Res. & Dev. Center, Schenectady, NY, USA
Chatterjee , Gen. Electr. Res. & Dev. Center, Schenectady, NY, USA
pp. 36-39

Efficient implementation of a BDD package (PDF)

Brace , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 40-45

Sequential circuit verification using symbolic model checking (PDF)

Clarke , Carnegie Mellon Univ., Pittsburgh, PA, USA
McMillan , Carnegie Mellon Univ., Pittsburgh, PA, USA
Burch , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 46-51

Shared binary decision diagram with attributed edges for efficient Boolean function manipulation (PDF)

Ishiura , Dept. of Inf. Sci., Kyoto Univ., Japan
Minato , Dept. of Inf. Sci., Kyoto Univ., Japan
Yajima , Dept. of Inf. Sci., Kyoto Univ., Japan
pp. 52-57

Relative scheduling under timing constraints (PDF)

De Micheli , Center for Integrated Syst., Stanford Univ., CA, USA
Ku , Center for Integrated Syst., Stanford Univ., CA, USA
pp. 59-64

Optimum and heuristic data path scheduling under resource constraints (PDF)

Cheng-Tsung Hwang , Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
Youn-Lang Lin , Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
Yu-Chin Hsu , Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
pp. 65-70

The combination of scheduling, allocation, and mapping in a single algorithm (PDF)

Cloutier , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Thomas , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 71-76

A linear program driven scheduling and allocation method followed by an interconnect optimization algorithm (PDF)

Papachristou , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 77-83

An adaptive timing-driven layout for high speed VLSI (PDF)

Sutanthavibul , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Shragowitz , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 90-95

A new min-cut placement algorithm for timing assurance layout design meeting net length constraint (PDF)

Sato , Mitsubishi Electr. Corp., Hyogo, Japan
Terai , Mitsubishi Electr. Corp., Hyogo, Japan
Takahashi , Mitsubishi Electr. Corp., Hyogo, Japan
pp. 96-102

Performance-driven constructive placement (PDF)

Lin , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Du , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 103-106

Analysis and design of latch-controlled synchronous digital circuits (PDF)

Mudge , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Olukotun , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Sakallah , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 111-117

Timing verification using HDTV (PDF)

Chiarulli , Pittsburgh Univ., PA, USA
Levitan , Pittsburgh Univ., PA, USA
Martello , Pittsburgh Univ., PA, USA
pp. 118-123

Timing analysis in precharge/unate networks (PDF)

McGeer , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 124-129

Coded time-symbolic simulation using shared binary decision diagram (PDF)

Ishiura , Dept. of Inf. Sci., Kyoto Univ., Japan
Deguchi , Dept. of Inf. Sci., Kyoto Univ., Japan
Yajima , Dept. of Inf. Sci., Kyoto Univ., Japan
pp. 130-135

Design management based on design traces (PDF)

Casotto , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Newton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 136-141

Meta data management in the NELSIS CAD framework (PDF)

Sloof , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
van der Wolf , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Dewilde , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Bingley , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 142-145

A design platform for the NELSIS CAD framework (PDF)

van der Wolf , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Bingley , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 146-149

An intelligent component database for behavioral synthesis (PDF)

Chen , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 150-155

Design data management in a CAD framework environment (PDF)

Liu , Silicon Graphics Inc., Mountain View, CA, USA
pp. 156-161

Memory, control and communications synthesis for scheduled algorithms (PDF)

Grant , Dept. of Electr. Eng., Edinburgh Univ., UK
Denver , Dept. of Electr. Eng., Edinburgh Univ., UK
pp. 162-167

A generalized interconnect model for data path synthesis (PDF)

Ly , Audesyn Inc., Edmonton, Alta., Canada
Elwood , Audesyn Inc., Edmonton, Alta., Canada
Girczyc , Audesyn Inc., Edmonton, Alta., Canada
pp. 168-173

Automatic operator configuration in the synthesis of pipelined architectures (PDF)

Casavant , GE Corp. R&D, Schenectady, NY, USA
McNall , GE Corp. R&D, Schenectady, NY, USA
pp. 174-179

An optimal algorithm for floorplan area optimization (PDF)

Wang , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 180-186

An analytical approach to floorplan design and optimization (PDF)

Sutanthavibul , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 187-192

Pad placement and ring routing for custom chip layout (PDF)

Wang , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 193-199

Comparing structurally different views of a VLSI design (PDF)

Spreitzer , Xerox Palo Alto Res. Center, CA, USA
pp. 200-206

How to prove the completeness of a set of register level design transformations (PDF)

Vemuri , Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
pp. 207-212

Verification of interacting sequential circuits (PDF)

Ghosh , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 213-219

Is redundancy necessary to reduce delay? (PDF)

Keutzer , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 228-234

Test function specification in synthesis (PDF)

Agrawal , AT&T Bell Lab., Murray Hill, NJ, USA
Cheng , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 235-240

Layout synthesis of MOS digital cells (PDF)

Domic , Digital Equipment Corp., Hudson, MA, USA
pp. 241-245

Design and performance evaluation of new massively parallel VLSI mask verification algorithms in JIGSAW (PDF)

Rutenbar , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Carlson , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 253-259

Circuit extraction on a message-based multiprocessor (PDF)

Tonkin , Adelaide Univ., SA, Australia
pp. 260-265

SKILL: a CAD system extension language (PDF)

Barnes , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 266-271

Brel-a PROLOG knowledge-based system shell for VLSI CAD (PDF)

Jabri , Syst. Eng. & Design Autom. Lab., Sydney Univ., NSW, Australia
pp. 272-277

Boolean resubstitution with permissible functions and binary decision diagrams (PDF)

Sato , Fujitsu Ltd., Kawasaki, Japan
Yasue , Fujitsu Ltd., Kawasaki, Japan
pp. 284-289

Reduced offsets for two-level multi-valued logic minimization (PDF)

Malik , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 290-296

An entropy measure for the complexity of multi-output Boolean functions (PDF)

Agrawal , AT&T Bell Lab., Murray Hill, NJ, USA
Cheng , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 302-305

A data path layout assembler for high performance DSP circuits (PDF)

Six , IMEC Lab., Leuven, Belgium
Note , IMEC Lab., Leuven, Belgium
de Man , IMEC Lab., Leuven, Belgium
Cai , IMEC Lab., Leuven, Belgium
pp. 306-311

Global routing considerations in a cell synthesis system (PDF)

Hill , AT&T Bell Lab., Murray Hill, NJ, USA
Shugard , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 312-316

Benchmarks for cell synthesis (PDF)

HiIl , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 317-320

New algorithm for overlapping cell treatment in hierarchical CAD data/electron beam exposure data conversion (PDF)

Watanabe , NTT LSI Lab., Kanagawa, Japan
Wada , NTT LSI Lab., Kanagawa, Japan
Okubo , NTT LSI Lab., Kanagawa, Japan
pp. 321-326

Design of repairable and fully diagnosable folded PLAs for yield enhancement (PDF)

Ding , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Wey , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
pp. 327-332

NASFLOW, a simulation tool for silicon technology development (PDF)

Gadepally , Nat. Semicond. Corp., Santa Clara, CA, USA
Agarwal , Nat. Semicond. Corp., Santa Clara, CA, USA
Yeh , Nat. Semicond. Corp., Santa Clara, CA, USA
Aronowitz , Nat. Semicond. Corp., Santa Clara, CA, USA
Forsythe , Nat. Semicond. Corp., Santa Clara, CA, USA
pp. 333-337

Timing optimization for multi-level combination networks (PDF)

Muroga , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Chen , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 339-344

Logic optimization algorithm by linear programming approach (PDF)

Shimizu , Hitachi Ltd., Tokyo, Japan
Miura , Hitachi Ltd., Tokyo, Japan
Kageyama , Hitachi Ltd., Tokyo, Japan
pp. 345-348

Delay and area optimization in standard-cell design (PDF)

Marek-Sadowska , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Lin , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Kuh , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 349-352

Algorithms for library-specific sizing of combinational logic (PDF)

Chan , Comput. Eng.., California Univ., Santa Cruz, CA, USA
pp. 353-356

A heuristic algorithm for the fanout problem (PDF)

Singh , California Univ., Berkeley, CA, USA
Sangiovanni-Vincentelli , California Univ., Berkeley, CA, USA
pp. 357-360

Multilevel synthesis minimizing the routing factor (PDF)

Sakouti , Inst. Nat. Polytech. de Grenoble/CSI, France
Saucier , Inst. Nat. Polytech. de Grenoble/CSI, France
Abouzeid , Inst. Nat. Polytech. de Grenoble/CSI, France
pp. 365-368

Layout compaction with attractive and repulsive constraints (PDF)

Onozawa , NTT LSI Lab., Kanagawa, Japan
pp. 369-374

A hierarchy preserving hierarchical compactor (PDF)

Marple , Philips Res. Lab., Eindhoven, Netherlands
pp. 375-381

An O(n/sup 1.5/ log n) 1-d compaction algorithm (PDF)

Lo , AT&T Bell Lab., Murray Hill, NJ, USA
Varadarajan , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 382-387

Parallel circuit simulation using hierarchical relaxation (PDF)

Wen , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
Gallivan , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
Saleih , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
Hung , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
pp. 394-399

PARASPICE: a parallel circuit simulator for shared-memory multiprocessors (PDF)

Yang , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
pp. 400-405

Waveform moment methods for improved interconnection analysis (PDF)

McCormick , Res. Lab. of Electron., MIT, Cambridge, MA, USA
Allen , Res. Lab. of Electron., MIT, Cambridge, MA, USA
pp. 406-412

System simulation of printed circuit boards including packages and connectors (PDF)

Adamiak , Quantic Lab. Inc., Winnipeg, Man., Canada
Poltz , Quantic Lab. Inc., Winnipeg, Man., Canada
Allen , Quantic Lab. Inc., Winnipeg, Man., Canada
Rebizant , Quantic Lab. Inc., Winnipeg, Man., Canada
Wexler , Quantic Lab. Inc., Winnipeg, Man., Canada
pp. 413-418

A framework for industrial layout generators (PDF)

Seaquist , AT&T Bell Lab., Allentown, PA, USA
Bower , AT&T Bell Lab., Allentown, PA, USA
pp. 419-424

Organized C: a unified method of handling data in CAD algorithms and databases (PDF)

Soukup , Code Farms Inc., Richmond, Ont., Canada
pp. 425-430

An object-oriented VHDL design environment (PDF)

Chung , Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
Kim , Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
pp. 431-436

An object-oriented kernel for an integrated design and process planning system (PDF)

Marefat , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
Kashyap , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
Feghhi , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 437-443

Percolation based synthesis (PDF)

Potasman , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
pp. 444-449

Synthesis using path-based scheduling: algorithms and exercises (PDF)

Camposano , IBM Res. Div., Yorktown Heights, NY, USA
Bergamaschi , IBM Res. Div., Yorktown Heights, NY, USA
pp. 450-455

A transistor reordering technique for gate matrix layout (PDF)

Singh , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
Chen , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 462-467

LiB: a cell layout generator (PDF)

Yung-Ching Hsieh , Electron. Res. & Service Organ., Ind. Technol. Res. Inst., Hsin-Chu, Taiwan
pp. 474-479

Techniques for unit-delay compiled simulation (PDF)

Maurer , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Wang , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 480-484

LECSIM: a levelized event-driven compiled logic simulator (PDF)

Maurer , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Wang , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 491-496

Data path allocation based on bipartite weighted matching (PDF)

Yen-Shen Chen , Dept. of Comput. Sci., Tsing Hua Univ., Hsin-Chu, Taiwan
Yan-Long Lin , Dept. of Comput. Sci., Tsing Hua Univ., Hsin-Chu, Taiwan
Chu-Yi Huang , Dept. of Comput. Sci., Tsing Hua Univ., Hsin-Chu, Taiwan
Yu-Chin Hsu , Dept. of Comput. Sci., Tsing Hua Univ., Hsin-Chu, Taiwan
pp. 499-504

Data path tradeoffs using MABAL (PDF)

Kucukcakar , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Parker , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 511-516

Symbolic simulation-techniques and applications (PDF)

Bryant , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 517-521

An efficient delay test generation system for combinational logic circuits (PDF)

Park , Mentor Graphics Corp., Beaverton, OR, USA
pp. 522-528

Automatic incorporation of on-chip testability circuits (PDF)

Ito , Fujitsu Ltd., Kawasaki, Japan
pp. 529-534

Architecture synthesis of high-performance application-specific processors (PDF)

Shen , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Breternitz , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 542-548

High-level synthesis: technology transfer to industry (PDF)

Dooley , Texas Instrum. Ltd., Bedford, UK
Newman , Texas Instrum. Ltd., Bedford, UK
Hetherington , Texas Instrum. Ltd., Bedford, UK
Sarma , Texas Instrum. Ltd., Bedford, UK
pp. 549-554

ASSURE: automated design for dependability (PDF)

Gupta , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Brennan , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Siewiorek , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Edmond , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 555-560

Constraint generation for routing analog circuits (PDF)

Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Choudhury , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 561-566

Segmented channel routing (PDF)

Greene , Actel Corp., Sunnyvale, CA, USA
pp. 567-572

Clock routing for high-performance ICs (PDF)

Kuh , Electron. Res. Lab., California Univ., Berkeley, CA, USA
Jackson , Electron. Res. Lab., California Univ., Berkeley, CA, USA
Srinivasan , Electron. Res. Lab., California Univ., Berkeley, CA, USA
pp. 573-579

Sequential test generation at the register-transfer and logic levels (PDF)

Ghosh , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 580-586

Behavioral fault simulation in VHDL (PDF)

Ward , Robertshaw Controls Co., Richmond, VA, USA
pp. 587-593

Speed up of test generation using high-level primitives (PDF)

Kunda , Illinois Univ., Urbana, IL, USA
Narain , Illinois Univ., Urbana, IL, USA
pp. 594-599

A unified approach to the decomposition and re-decomposition of sequential machines (PDF)

Ashar , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 601-606

Corolla based circuit partitioning and resynthesis (PDF)

Dey , Dept. of Comput. Sci., Duke Univ., Durham, NC, USA
pp. 607-612

Chortle: a technology mapping program for lookup table-based field programmable gate arrays (PDF)

Rose , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
Francis , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
Chung , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
pp. 613-619

Logic synthesis for programmable gate arrays (PDF)

Murgai , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Nishizaki , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Shenoy , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 620-625

A gridless router for industrial design rules (PDF)

Kirsch , Siemens AG, Munich, Germany
Kruger , Siemens AG, Munich, Germany
Schiele , Siemens AG, Munich, Germany
Just , Siemens AG, Munich, Germany
pp. 626-631

Layout optimization by pattern modification (PDF)

Hojati , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 632-637

A channel/switchbox definition algorithm for building-block layout (PDF)

Cai , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 638-641

New placement and global routing algorithms for standard cell layouts (PDF)

Edahiro , NEC Corp., Kawasaki, Japan
Yoshimura , NEC Corp., Kawasaki, Japan
pp. 642-645

PHIGURE: a parallel hierarchical global router (PDF)

Brouwer , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
Banerjee , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 650-653

Automatic test generation using quadratic 0-1 programming (PDF)

Chakradhar , Dept. of Comput. Sci., Rutgers Univ., Piscataway, NJ, USA
pp. 654-659

SOPRANO: an efficient automatic test pattern generator for stuck-open faults in CMOS combinational circuits (PDF)

Lee , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Ha , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 660-666

EST: the new frontier in automatic test-pattern generation (PDF)

Bushnell , Rutgers Univ., Piscataway, NJ, USA
Giraldi , Rutgers Univ., Piscataway, NJ, USA
pp. 667-672

The influences of fault type and topology on fault model performance and the implications to test and testable design (PDF)

Mercer , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Butler , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 673-678

Abstract data types and high-level synthesis (PDF)

Newton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Whitcomb , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 680-685

Failure recovery in the MICON system (PDF)

Birmingham , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Data , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 686-691

The FSM network model for behavioral synthesis of control-dominated machines (PDF)

Wolf , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 692-697

MISER: an integrated three layer gridless channel router and compacter (PDF)

Sherwani , Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
Gidwani , Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
pp. 698-703

A multi-layer router utilizing over-cell areas (PDF)

Kinnen , Dept. of Electr. Eng., Rochester Univ., NY, USA
Katsadas , Dept. of Electr. Eng., Rochester Univ., NY, USA
pp. 704-708

General models and algorithms for over-the-cell routing in standard cell design (PDF)

Cong , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 709-715

A parallel pattern mixed-level fault simulator (PDF)

Tyh-Song Hwang , Inst. of Electron., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
Ching Ping Wu , Inst. of Electron., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
Chung Len Lee , Inst. of Electron., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
Wen Zen Shen , Inst. of Electron., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
pp. 716-719

Extension of the critical path tracing algorithm (PDF)

Kinney , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Ramakrishnan , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 720-723

BIST PLAs, pass or fail-a case study (PDF)

Upadhyaya , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
Thodiyil , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
pp. 724-727

A variable observation time method for testing delay faults (PDF)

Mao , Dept. of Electr. & Comput. Eng., Colorado Univ., Colorado Springs, CO, USA
Ciletti , Dept. of Electr. & Comput. Eng., Colorado Univ., Colorado Springs, CO, USA
pp. 728-731

A fault analysis method for synchronous sequential circuits (PDF)

Lee , Inst. of Electr. & Comput. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Wang , Inst. of Electr. & Comput. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Kuo , Inst. of Electr. & Comput. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 732-735

On synthesizing and identifying stuck-open testable CMOS combinational circuits (PDF)

Chakravarty , Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
pp. 736-739

The use of observability and external don't cares for the simplification of multi-level networks (PDF)

Savoj , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 297-301
103 ms
(Ver )