The Community for Technology Leaders
26th ACM/IEEE Design Automation Conference (1989)
Las Vegas, NV, USA
June 25, 1989 to June 29, 1989
ISSN: 0738-100X
ISBN: 0-89791-310-8
TABLE OF CONTENTS

Reviewers (PDF)

pp. x,xi,xii

The Last Decade of Design Automation. And the next. (PDF)

G. Langler , Mentor Graphics Corporation
pp. xxv,xxvi

A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs (Abstract)

M. Potkonjak , Department of EECS, University of California, Berkeley
pp. 7-12

Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers (Abstract)

P. Sadayappan , Department of Computer and Information Science, The Ohio State University, Columbus, OH
pp. 13-18

A Framework for Scheduling Multi-rate Circuit Simulation (Abstract)

A.P.-C. Ng , Computer Science Division, University of California, Berkeley, Berkeley, CA
pp. 19-24

Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator (Abstract)

P. Odent , IMEC, Interuniversity Micro Electronics Center, VSDM division, Leuven, Belgium
pp. 25-30

Template Style Considerations for Sea-of-Gates Layout Generation (Abstract)

G.D. Adams , Computer Science Division, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 31-36

Gate Matrix Layout Synthesis with Two-Dimensional Folding (PDF)

Ichiang Lin , Department of Computer Science, University of Minnesota, Minneapolis, MN
pp. 37-42

Transistor Size Optimization in the Tailor Layout System (Abstract)

D. Marple , Philips Research Laboratories, Eindhoven, Netherlands
pp. 43-48

Tutorial/Panel Languages for Behavioral Description and Synthesis (PDF)

R. Piloty , Inst. fur Datentechnik, Darmstadt, FRG
pp. 49

VLSI Design Language Standardization Effort in Japan (Abstract)

O. Karatsu , Nippon Telegraph and Telephone Corporation, Tokyo, Japan
pp. 50-55

Experience with the ADAM Synthesis System (Abstract)

R. Jain , Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
pp. 56-61

Architectural Partitioning for System Level Design (Abstract)

E.D. Lagnese , Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA
pp. 62-67

Integrated Scheduling and Binding : A Synthesis Approach for Design Space Exploration (Abstract)

M. Balakrishnan , Comp. Sci. & Engg. Dept., I.I.T. Delhi, New Delhi, INDIA
pp. 68-74

Characterization of Parallelism and Deadlocks in Distributed Digital Logic Simulation (Abstract)

L. Soule , Computer Systems Laboratory, Stanford University, CA
pp. 81-86

Scheduling High-Level Blocks for Functional Simulation (PDF)

Zhicheng Wang , Department of Computer Science and Engineering, University of South Florida, Tampa, FL
pp. 87-90

Massively Parallel Switch-Level Simulation: A Feasibility Study (Abstract)

S.A. Kravitz , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
pp. 91-97

Data Parallel Simulation Using Time-Warp on the Connection Machine (PDF)

Moon Jung Chung , Department of Computer Science, Michigan State University, East Lansing, MI
pp. 98-103

LASSIE: Structure to Layout for Behavioral Synthesis Tools (Abstract)

M.T. Trick , Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA
pp. 104-109

Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout (Abstract)

W.K. Luk , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 110-115

Performance Optimized Floor Planning by Graph Planarization (Abstract)

B. Lokanathan , Dept. of Electrical Engineering, University of Rochester, Rochester NY
pp. 116-121

ORCA A Sea-of-gates Place and Route System (Abstract)

M. Igusa , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 122-127

Tutorial/Panel Social Impact of Computerization (PDF)

R. Newton , University of California, Berkeley, CA
pp. 128

The MICON System for Computer Design (Abstract)

W.P. Birmingham , EECS Dept, University of Michigan, Ann Arbor, MI
pp. 135-140

Automatic Synthesis of Microprogrammed Control Units from Behavioral Descriptions (Abstract)

A. Kumar , Department of Computer Science & Engineering, Indian Institute of Technology, Delhi, New Delhi, INDIA
pp. 147-154

On Global Wire Ordering for Macro-Cell Routing (Abstract)

P. Groeneveld , Faculty of Electrical Engineering, Delft University of Technology, Delft, The Netherlands
pp. 155-160

A New Approach to the Rectilinear Steiner Tree Problem (PDF)

Jan-ming Ho , Department of EECS, Northwestern University, Evanston, IL
pp. 161-166

A New Heuristic for Single Row Routing Problems (Abstract)

N.A. Sherwani , Department of Computer Science, Western Michigan University, Kalamazoo, MI
pp. 167-172

IRSIM: An Incremental MOS Switch-Level Simulator (Abstract)

A. Salz , Computer Systems Laboratory, Stanford University, CA
pp. 173-178

Locating Functional Errors in Logic Circuits (Abstract)

K.A. Tamura , NEC Corp. C&C Systems Research Laboratories, Kawasaki, Japan
pp. 185-191

Tutorial/Panel Case for Electronic Design Automation (PDF)

A. Rappaport , Technology Research Group, Boston, MA
pp. 192

CASE Environments for Design Automation (PDF)

A.I. Wasserman , Interactive Development Environments, Inc., San Francisco, CA
pp. 193-196

An Object Oriented Approach to CAD Tool Control within a Design Framework (Abstract)

J. Daniell , Electrical and Computer Engineering Dept., Carnegie Mellon University, Pittsburgh, PA
pp. 197-202

DeBuMA: Description, Building and Management of Applications (Abstract)

C. Frydman , L.E.R.I Laboratoire d'Etude et Recherche en Informatique, Nimes, France
pp. 203-208

Experience with the D-BUS Architecture for a Design Automation Framework (Abstract)

E.C. VanHorn , Digital Equipment Corporation, Marlboro, MA
pp. 209-214

Multi-Level Logic Synthesis Using Communication Complexity (PDF)

Ting-Ting Hwang , Department of Computer Science, The Pennsylvania State University, University Park, PA
pp. 215-220

Efficient Prime Factorization of Logic Expressions (Abstract)

P.C. McGeer , Department of EECS, University of California, Berkeley
pp. 221-225

New Methods in the Analysis of Logic Minimization Data and Algorithms (Abstract)

A.J. Coppola , Mentor Graphics Corporation, Beaverton, OR
pp. 226-231

The Layout Synthesizer: An Automatic Netlist-to-Layout System (Abstract)

C.C. Chen , Cadence Design Systems, Inc., San Jose, CA
pp. 232-238

GENAC: An Automatic Cell Synthesis Tool (PDF)

Chong-Leong Ong , AT&T Bell Laboratories, Murray Hill, NJ
pp. 239-244

A Module Generator for Optimized CMOS Buffers (Abstract)

A.J. Al-Khalili , Dept. of Electrical and Computer Engineering, Concordia University, Montreal, Canada
pp. 245-250

Use of Change Coordination in an Information-Rich Design Environment (Abstract)

M. Winslett , Computer Science Department, University of Illinois, Urbana, ILand Computer Science Department, Stanford University, Stanford, CA
pp. 252-257

Database Support for Evolving Design Objects (Abstract)

A. Biliris , Computer Science Department, Boston University, Boston, MA
pp. 258-263

Protection and Versioning for OCT (Abstract)

M. Silva , Electronics Research Laboratory, University of California, Berkeley, Berkeley, CA
pp. 264-269

Approaches to Multi-Level Sequential Logic Synthesis (Abstract)

S. Devadas , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge
pp. 270-276

Multi-Level Logic Simplification Using Don't Cares and Filters (Abstract)

A. Saldanha , EECS Department, University of Califronia, Berkeley, Berkeley, CA
pp. 277-282

Automatic Synthesis of Boolean Equations Using Programmable Array Logic (Abstract)

R.P. Gore , Dept. of Computer Science, University of Melbourne, Parkville, Australia
pp. 283-289

An Efficient Two-Dimensional Layout Compaction Algorithm (PDF)

Hyunchul Shin , AT&T Bell Laboratories, Murray Hill, NJ
pp. 290-295

Technology Tracking of Non Manhattan VLSI Layout (Abstract)

J. Waterkamp , Universitat Dortmund, Lehrstuhl Informatik 1, Dortmund, West Germany
pp. 296-301

Automatic Tub Region Generation for Symbolic Layout Compaction (PDF)

Chi-Yuan Lo , AT&T Bell Laboratories, Murray Hill, NJ
pp. 302-306

General Decomposition of Sequential Machines: Relationships to State Assignment (Abstract)

S. Devadas , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge
pp. 314-320

NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations (Abstract)

T. Villa , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 327-332

Horizontal Partitioning of PLA-based Finite State Machines (Abstract)

P.G. Paulin , INPG/CSI, Grenoble Cedex, France
pp. 333-338

A Parallel Branch and Bound Algorithm for Test Generation (Abstract)

S. Patil , Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 339-344

Test Pattern Generation for Stuck-Open Faults Using Stuck-At Test Sets in CMOS Combinational Circuits (PDF)

Hyung Ki Lee , Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA
pp. 345-350

A Deterministic Approach to Adjacency Testing for Delay Faults (Abstract)

C.T. Glover , Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
pp. 351-356

Parallel Pattern Fault Simulation of Path Delay Faults (Abstract)

M.H. Schulz , Institute of Computer Aided Design, Department of Electrical Engineering, Technical University of Munich, Munich, West Germany
pp. 357-363

Path-Delay Constrained Floorplanning: A Mathematical Programming Approach for Initial Placement (Abstract)

S. Prasitjutrakul , Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 364-369

Performance-Driven Placement of Cell Based IC's (Abstract)

M.A.B. Jackson , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 370-375

An Analytic Optimization Technique for Placement of Macro-Cells (Abstract)

A. Herrigel , Integrated System Laboratory, Swiss Federal Institute of Technology Zurich, Zurich, Switzerland
pp. 376-381

An Investigation into Statistical Properties of Partitioning and Floorplanning Problems (Abstract)

S. Sastry , Dept. of EE-Systems, University of Southern California, Los Angeles, CA
pp. 382-387

Multi Chip Modules (PDF)

R.H. Bruce , Xerox Research Center, Palo Alto, CA
pp. 389-393

Automatic Layout of Silicon-On-Silicon Hybrid Packages (PDF)

B. Preas , Computer Science Laboratory, Xerox Palo Alto Research Center,Palo Alto, CA
pp. 394-399

Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks (Abstract)

R. Libeskind-Hadas , Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 400-405

A Neural Network Design for Circuit Partitioning (PDF)

Jih-Shyr Yih , Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MI
pp. 406-411

An Automatic Test Generation Algorithm for Hardware Description Languages (Abstract)

F.E. Norrod , Hewlett Packard, Fort Collins, CO
pp. 429-434

VVDS: A Verification/Diagnosis System for VHDL (PDF)

Heh-Tyan Liaw , Department of Electrical Engeneering, National Taiwan University, Taipei, Taiwan, ROC
pp. 435-440

Verification of Hardware Descriptions by Retargetable Code Generation (Abstract)

L. Nowak , Nixdorf Computer AG, Paderborn, W. Germany
pp. 441-447

GRASP: A Grammar-based Schematic Parser (Abstract)

C. Bamji , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge
pp. 448-453

Design for Manufacturability and Yield (Abstract)

A.J. Strojwas , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
pp. 454-459

MIOS: A Flexible System for PCB Manufacturing (Abstract)

A.C. Hung , Tektronix, Inc., Beaverton, OR
pp. 460-465

An Approach to Intelligent Assistance for the Specification of ASIC Design Using Objects and Rules (Abstract)

K.D. Mueller-Glaser , University of Erlangen-Nuernberg, Department of Electrical Engineering, Erlangen, West-Germany
pp. 472-477

Computing Signal Delay in General RC Networks by Tree/Link Partitioning (PDF)

P.K. Chan , Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA
pp. 485-490

Worst-Case Delay Estimation of Transistor Groups (Abstract)

S. Gaiotti , Dept. of Electrical Engineering, McGill University, Montreal, Quebec, Canada
pp. 491-496

Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits (Abstract)

N. Ishiura , Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto, JAPAN
pp. 497-502

An O(n log m) Algorithm for VLSI Design Rule Checking (PDF)

C.R. Bonapace , AT&T Bell Laboratories, Murray Hill, NJ
pp. 503-507

The Use of Inverse Layout Trees for Hierarchical Design Rule Checking (Abstract)

N. Hedenstierna , Chalmers University of Technology, School of Electrical and Computer Engineering, Department of Solid-State Electronics, Goteborg, Sweden
pp. 508-512

Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour (Abstract)

I. Bolsens , IMEC, Interuniversity Micro Electronics Center, VSDM division, Leuven, Belgium
pp. 513-518

MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits (Abstract)

T. Ogihara , ASIC Design Engineering Center, Mitsubishi Electric Corporation, Kanagawa, JAPAN
pp. 519-524

A Scheme for Overlaying Concurrent Testing of VLSI Circuits (PDF)

Wen-Ben Jone , Department of Computer Science, New Mexico Tech, Socorro, NM
pp. 531-536

ACE: A Hierarchical Graphical Interface for Architectural Synthesis (Abstract)

O.A. Buset , VLSI Group, Electrical Engineering Department, University of Waterloo, Waterloo, Ontario, CANADA
pp. 537-542

ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software (Abstract)

D.E. Setliff , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
pp. 543-548

High-Level Graphical User Interface Management in the FACE Synthesis Environment (Abstract)

M. Dragomirecky , GE Aerospace, Simulation & Control Systems Department, Daytona Beach, FL
pp. 549-554

On the General False Path Problem in Timing Analysis (Abstract)

D.H.C. Du , Department of Computer Science, University of Minnesota, Minneapolis, MN
pp. 555-560

Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network (Abstract)

P.C. McGeer , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley
pp. 561-567

Static Timing Analysis of Dynamically Sensitizable Paths (Abstract)

S. Perremans , IMEC, Interuniversity Micro Electronics Center, VSDM division, 3030 Leuven, Belgium
pp. 568-573

Average Interconnection Length and Interconnection Distribution Based on Rent's Rule (Abstract)

C.V. Gura , Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-champaign
pp. 574-577

Efficient Final Placement Based on Nets-as-points (PDF)

Xueqing Zhang , Department of Electrical Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
pp. 578-581

PIAF: A Knowledge-based/Algorithmic Top-down Floorplanning System (Abstract)

M.A. Jabri , Systems Engineering and Design Automation Laboratory, Sydney University Electrical Engineering, NSW, Australia
pp. 582-585

Efficient Floorplan Area Optimization (Abstract)

D.F. Wong , Department of Computer Sciences University of Texas at Austin, Austin, TX
pp. 586-589

A Parallel Row-Based Algorithm for Standard Cell Placement with Integrated Error Control (Abstract)

J.S. Sargent , Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 590-593

A Note on Clustering Modules for Floorplanning (Abstract)

J.D. Gabbe , AT&T Bell Laboratories, Holmdel, NJ
pp. 594-597

An Interactive Tool for Register-Level Structure Optimization (Abstract)

D.W. Knapp , University of Illinois at Urbana-Champaign
pp. 598-601

VHDL Synthesis Using Structured Modeling (Abstract)

J.S. Lis , Dept. of Information & Computer Science, University of California, Irvine, Irvine, CA
pp. 606-609

Capturing Designer Expertise The CGEN System (Abstract)

W.P. Birmingham , Advanced Computer Architecture Laboratory, Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, MI
pp. 610-613

Evaluation of a Reconfigurable Architecture for Digital Beamforming Using the OODRA Workbench (Abstract)

D.K. Hwang , Computer Systems Group Coordinated Science Laboratory, University of Illinois, Urbana, IL
pp. 614-617

An ASIC Methodology for Mixed Analog-Digital Simulation (Abstract)

M. Rumsey , Texas Instruments Ltd., Bedford, England
pp. 618-621

A Novel Algorithm for Improving Convergence Behavior of Circuit Simulators (PDF)

Zhiping Yu , The Institute of Microelectronics, Tsinghua University, Beijing, China
pp. 626-629

iSMILE: A Novel Circuit Simulation Program with emphasis on New Device Model Development (Abstract)

A.T. Yang , Center for Compound Semiconductor Microelectronics, Coordinated Science Laboratory and Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL
pp. 630-633

AWEsim: Asymptotic Waveform Evaluation for Timing Analysis (Abstract)

L.T. Pillage , Department of Electrical Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
pp. 634-637

A Novel Approach to Accurate Timing Verification Using RTL Descriptions (Abstract)

K. Roy , Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 638-641

Evaluating Hardware Models in DIGITAL's System Simulation Environment (Abstract)

A.K. George , Digital Equipment Corporation, Maynard, MA
pp. 642-644

Algorithms for Accuracy Enhancement in a Hardware Logic Simulator (Abstract)

P. Agrawal , AT&T Bell Laboratories, Murray Hill, NJ
pp. 645-648

Efficient Algorithms for Extracting the K Most Critical Paths in Timing Analysis (Abstract)

S.H.C. Yen , Department of Computer Science, University of Minnesota, Minneapolis, MN
pp. 649-654

Timing Analysis in a Logic Synthesis Environment (Abstract)

N. Weiner , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 655-661

Rule-Based VLSI Verification System Constrained by Layout Parasitics (Abstract)

J. Wenin , Bell Alcatel - Antwerp, VLSI Department, Francis Wellesplein, Antwerp, Belgium
pp. 662-667

Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator (Abstract)

J. Benkoski , SRC-CMU Research Center for CAD, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
pp. 668-673

Special Purpose Architecture for Accelerating Bitmap DRC (Abstract)

N.B. Bhat , Elec. Comm. Engg., Indian Institute of Science, Bangalore, INDIA
pp. 674-677

An Efficient Finite Element Method for Submicron IC Capacitance Extraction (Abstract)

N.P. van der Meijs , Delft University of Technology, Department of Electrical Engineering, Delft, The Netherlands
pp. 678-681

Resistance Extraction and Resistance Calculation in GOALIE2 (PDF)

Kuang-Wei Chiang , AT&T Bell Laboratories, Murray Hill, NJ
pp. 682-685

From Network to Artwork (Abstract)

L. Stok , Eindhoven University of Technology, Eindhoven, The Netherlands
pp. 686-689

Extracting Schematic-Like Information from CMOS Circuit Net-Lists (PDF)

Wen-Jeng Lue , Computer Science Department, University of California, Los Angeles, Los Angeles, CA
pp. 690-693

A Comparison of Four Two-Dimensional Gate Matrix Layout Tools (Abstract)

M.J. Irwin , Department of Computer Science, The Pennsylvania State University, University Park, PA
pp. 698-701

Plowing: Modifying Cells and Routing in 45 ° -Layouts (PDF)

K.M. Just , Siemens AG, Semiconductor Division, Munich, FRG
pp. 702-705

CrossCheck: A Cell Based VLSI Testability Solution (Abstract)

T. Gheewala , CrossCheck Technology, Inc., East San Jose, CA
pp. 706-709

On the Repair of Redundant RAMs (Abstract)

V.G. Hemmady , Department of Electrical and Computer Engineering, University of Iowa, Iowa City, IA
pp. 710-713

CMOS Stuck-Open Fault Detection Using Single Test Patterns (Abstract)

R. Rajsuman , Department of Computer Engineering, Case Western Reserve University, Cleveland, OH
pp. 714-717

A Functional-Level Test Generation Methodology Using Two-Level Representations (Abstract)

U.J. Dave , Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 722-725

A New Approach to Derive Robust Tests for Stuck-Open Faults in CMOS Combinational Logic Circuits (PDF)

Jhing-Fa Wang , Institute of Electrical and Computer Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C.
pp. 726-729

A Simplified Six-Waveform Type Method for Delay Fault Testing (PDF)

Wei-Wei Mao , Department of Electrical and Computer Engineering, University of Colorado at Colorado Springs, Colorado Springs, CO
pp. 730-733

A Massively Parallel Algorithm for Fault Simulation on the Connection Machine (Abstract)

V. Narayanan , ECE Department, Syracuse University, Syracuse, NY
pp. 734-737

A New Model for the High Level Description and Simulation of VLSI Networks (Abstract)

A.J. van der Hoeven , Delft University of Technology, Faculty of Electrical Engineering, Delft, The Netherlands
pp. 738-741

Toward Synthesis from English Descriptions (Abstract)

W. Cyre , Corporate Research and Engineering, Control Data Corporation, Minneapolis, MN
pp. 742-745

Behavioral Modeling of Transmission Gates in VHDL (Abstract)

S.S. Leung , Department of Electrical Engineering, Michigan State University, East Lansing, MI
pp. 746-749

VCOMP: A VHDL Composition System (PDF)

P.R. Jordan , Barron Associates, Inc., Stanardsville, VA
pp. 750-753

Designer Controlled Behavioral Synthesis (Abstract)

N.D. Dutt , Dept. of Information & Computer Science, University of California, Irvine, Irvine, CA
pp. 754-757

Partitioning by Probability Condensation (Abstract)

J. Blanks , Mentor Graphics Corporation
pp. 758-761

Fast Hypergraph Partition (Abstract)

A.B. Kahng , Department of Computer Science, University of California, San Diego, La Jolla, CADepartment of Computer Science, University of California, San Diego, La Jolla, CA
pp. 762-766

An Evolution-Based Approach to Partitioning ASIC Systems (Abstract)

Y. Saab , Coordinated Science Laboratory and Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 767-770

Min-Cost Partitioning on a Tree Structure and Applications (Abstract)

G. Vijayan , IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 771-774

Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms (PDF)

Thang Bui , Computer Science Department, Pennsylvania State University, University Park, PA
pp. 775-778

Compaction of a Routed Channel on the Connection Machine (Abstract)

S. Ganguly , Dept. of Electrical and Computer Engineering, Syracuse University, Syracuse NY
pp. 779-782

Automatic Sizing of Power/Ground (P/G) Networks in VLSI (Abstract)

R. Dutta , Digital Equipment Corporation, Hudson, MA
pp. 783-786

Optimum Design of Reliable IC Power Networks Having General Graph Topologies (Abstract)

S. Chowdhury , Department of Electrical and Computer Engineering, University of Iowa, Iowa City, IA
pp. 787-790

DYNAJUST: An Efficient Automatic Routing Technique Optimizing Delay Conditions (Abstract)

Y. Fujihara , Hitachi Research Laboratory, Hitachi Ltd., Ibaraki-ken, Japan
pp. 791-794

DTR: A Defect-Tolerant Routing Algorithm (Abstract)

A. Pitaksanonkul , The Center for Advanced Computer Studies, University of Southwestern Louisiana, Lafayette, LA
pp. 795-798

Via Minimization by Layout Modification (Abstract)

K. The , Dept. of Computer Sciences University of Texas at Austin, Austin, TX
pp. 799-802

A Unified Data Exchange Environment Based on EDIF (PDF)

Wanhao Li , Motorola Inc. ASIC Division, Chandler, AZ
pp. 803-806

An Object-Oriented Datamodel for the VLSI Design System PLAYOUT (Abstract)

E. Siepmann , University of Kaiserslautern, Kaiserslautern, West-Germany
pp. 814-817

CEDIF: A Data Driven EDIF Reader (Abstract)

M. Roberts , ASIC Design Automation, National Semiconductor, Puyallup, WA
pp. 818-821

Fast Online/Offline Netlist Compilation of Hierarchical Schematics (Abstract)

L.G. Jones , Computer Science Department, University of Illinois at Urbana-Champaign
pp. 822-825

Semantics of a Hardware Design Language for Japanese Standardization (Abstract)

H. Yasuura , Department of Electronics, Faculty of Engineering, Kyoto University, Kyoto, Japan
pp. 836-839
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