The Community for Technology Leaders
Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
TABLE OF CONTENTS
Papers

An automated BIST approach for general sequential logic synthesis (PDF)

Stroud , AT&T Bell Lab., Naperville, IL, USA
pp. 3-8

Automatic insertion of BIST hardware using VHDL (PDF)

Ha , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Kim , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Tront , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 9-15

VLSI design synthesis with testability (PDF)

Elmasry , Dept. of Electr. Eng., Waterloo Univ., Ont., Canada
Gebotys , Dept. of Electr. Eng., Waterloo Univ., Ont., Canada
pp. 16-21

A defect-tolerant and fully testable PLA (PDF)

Roth , Inst. fuer Halbleitertech., Tech. Hochschule Darmstadt, West Germany
Wehn , Inst. fuer Halbleitertech., Tech. Hochschule Darmstadt, West Germany
Caesar , Inst. fuer Halbleitertech., Tech. Hochschule Darmstadt, West Germany
Mann , Inst. fuer Halbleitertech., Tech. Hochschule Darmstadt, West Germany
Glesner , Inst. fuer Halbleitertech., Tech. Hochschule Darmstadt, West Germany
pp. 22-27

Experience with the VHDL environment (PDF)

Cerny , Dept. d'Inf. et de Recherche Operationnelle, Montreal Univ., Que., Canada
Cote , Dept. d'Inf. et de Recherche Operationnelle, Montreal Univ., Que., Canada
Loughzail , Dept. d'Inf. et de Recherche Operationnelle, Montreal Univ., Que., Canada
Aboulhamid , Dept. d'Inf. et de Recherche Operationnelle, Montreal Univ., Que., Canada
pp. 28-33

The role of VHDL in the MCC CAD system (PDF)

Read , Microelectron. Comput. Technol. Corp., Austin, TX, USA
Alexandre , Microelectron. Comput. Technol. Corp., Austin, TX, USA
Acosta , Microelectron. Comput. Technol. Corp., Austin, TX, USA
Inken , Microelectron. Comput. Technol. Corp., Austin, TX, USA
pp. 34-39

VHDL: a call for standards (PDF)

Coelho , Vantage Anal. Syst., Inc., Fremont, CA, USA
pp. 40-47

Verification of VHDL designs using VAL (PDF)

Augustin , Comput. Syst. Lab., Stanford Univ., CA, USA
Gennart , Comput. Syst. Lab., Stanford Univ., CA, USA
Huh , Comput. Syst. Lab., Stanford Univ., CA, USA
Stanculescu , Comput. Syst. Lab., Stanford Univ., CA, USA
Luckham , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 48-53

A module area estimator for VLSI layout (PDF)

Chen , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
Bushnell , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 54-59

A new area and shape function estimation technique for VLSI layouts (PDF)

Zimmerman , FB Inf., Kaiserslautern Univ., West Germany
pp. 60-65

Optimal aspect ratios of building blocks in VLSI (PDF)

Wimer , Dept. of Electr. Eng., Technion, Israel Inst. of Technol., Israel
pp. 66-71

Opportunities in computer integrated manufacturing (PDF)

Hodges , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 82-83

A method of delay fault test generation (PDF)

Glover , Dept. of Electr. & Comput. Eng., Austin Univ., TX, USA
Mercer , Dept. of Electr. & Comput. Eng., Austin Univ., TX, USA
pp. 90-95

SPLIT circuit model for test generation (PDF)

Cheng , AT&T Eng. Res. Center, Princeton, NJ, USA
pp. 96-101

A notation for describing multiple views of VLSI circuits (PDF)

Winder , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
Baer , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
Snyder , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
Nottrott , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
Liem , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
McMurchie , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
pp. 102-107

A graphical hardware design language (PDF)

Wang , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
Bammi , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
Drongowski , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
Ramaswamy , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
Iyengar , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
pp. 108-114

A human machine interface for silicon compilation (PDF)

Hirata , Dept. of Precision Eng., Tokyo Univ., Japan
Hattori , Dept. of Precision Eng., Tokyo Univ., Japan
Odawara , Dept. of Precision Eng., Tokyo Univ., Japan
Okuzawa , Dept. of Precision Eng., Tokyo Univ., Japan
Tomita , Dept. of Precision Eng., Tokyo Univ., Japan
pp. 115-120

Parallel placement on reduced array architecture (PDF)

Kumar , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Sastry , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 121-127

Parallel channel routing (PDF)

Zargham , Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA
pp. 128-133

Mask verification on the Connection Machine (PDF)

Carlson , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
Rutenbar , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 134-140

On path selection in combinational logic circuits (PDF)

Li , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 142-147

Pearl: a CMOS timing analyzer (PDF)

Cherry , Symbolics Cambridge Res. Center, MA, USA
pp. 148-153

ATV: an abstract timing verifier (PDF)

Wallace , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Sequin , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 154-159

An empirical study of on-chip parallelism (PDF)

Bailey , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
Snyder , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
pp. 160-165

Parallel logic simulation on general purpose machines (PDF)

Blank , Center for Integrated Syst., Stanford Univ., CA, USA
Soule , Center for Integrated Syst., Stanford Univ., CA, USA
pp. 166-171

A programmable hardware accelerator for compiled electrical simulation (PDF)

Lewis , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
pp. 172-177

Recursive channel router (PDF)

Heyns , Silvar-Lisco, Leuven, Belgium
Nieuwenhove , Silvar-Lisco, Leuven, Belgium
pp. 178-182

Multi-pads, single layer power net routing in VLSI circuits (PDF)

Cai , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 183-188

LocusRoute: a parallel global router for standard cells (PDF)

Rose , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 189-195

Formal specification and verification of hardware: a comparative case study (PDF)

Stavridou , Dept. of Comput. Sci., Manchester Univ., UK
Barringer , Dept. of Comput. Sci., Manchester Univ., UK
Edwards , Dept. of Comput. Sci., Manchester Univ., UK
pp. 197-204

Proving circuit correctness using formal comparison between expected and extracted behaviour (PDF)

Madre , Bull Res. Center, Louveciennes, France
Billon , Bull Res. Center, Louveciennes, France
pp. 205-210

Formal verification of the Sobel image processing chip (PDF)

Narendran , Gen. Electr. Co., Schenectady, NY, USA
pp. 211-217

The IBM engineering verification engine (PDF)

Beece , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 218-224

Logic simulation system using simulation processor (SP) (PDF)

Hirose , Fujitsu Ltd., Kawasaki, Japan
Masuda , Fujitsu Ltd., Kawasaki, Japan
Saitoh , Fujitsu Ltd., Kawasaki, Japan
Kakegawa , Fujitsu Ltd., Kawasaki, Japan
Kawato , Fujitsu Ltd., Kawasaki, Japan
Nakamura , Fujitsu Ltd., Kawasaki, Japan
Hamamura , Fujitsu Ltd., Kawasaki, Japan
Iwata , Fujitsu Ltd., Kawasaki, Japan
pp. 225-230

Algorithm for vectorizing logic simulation and evaluation of 'VELVET' performance (PDF)

Knoshita , Hitachi Ltd., Kanagawa, Japan
Kazama , Hitachi Ltd., Kanagawa, Japan
pp. 231-236

A structural representation for VLSI design (PDF)

Serlet , Xerox PARC Comput. Sci. Lab., Palo Alto, CA, USA
Barth , Xerox PARC Comput. Sci. Lab., Palo Alto, CA, USA
pp. 237-242

Parameterized schematics (VLSI) (PDF)

Barth , Xerox PARC Comput. Sci. Lab., Palo Alto, CA, USA
Sindhu , Xerox PARC Comput. Sci. Lab., Palo Alto, CA, USA
Serlet , Xerox PARC Comput. Sci. Lab., Palo Alto, CA, USA
pp. 243-249

PatchWork: layout from schematic annotations (PDF)

Serlet , Xerox PARC Comput. Sci. Lab., Palo Alto, CA, USA
Barth , Xerox PARC Comput. Sci. Lab., Palo Alto, CA, USA
Monier , Xerox PARC Comput. Sci. Lab., Palo Alto, CA, USA
pp. 250-255

A database management system for a VLSI design system (PDF)

Parng , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Chen , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 257-262

An enhanced data model for CAD/CAM database systems (PDF)

Yang , Harris Corp., Melbourne, FL, USA
pp. 263-268

Browsing the chip design database (PDF)

Katz , Div. of Comput. Sci., California Univ., Berkeley, CA, USA
Gedye , Div. of Comput. Sci., California Univ., Berkeley, CA, USA
pp. 269-274

Versions and change notification in an object-oriented database system (PDF)

Kim , MCC, Austin, TX, USA
Chou , MCC, Austin, TX, USA
pp. 275-281

An accurate and efficient gate level delay calculator for MOS circuits (PDF)

Chen , AT&T Bell Lab., Murray Hill, NJ, USA
Chang , AT&T Bell Lab., Murray Hill, NJ, USA
Subramaniam , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 282-287

Delay modeling and timing of bipolar digital circuits (PDF)

Saab , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Hajj , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Yang , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 288-293

Pattern-independent current estimation for reliability analysis of CMOS circuits (PDF)

Hocevar , Texas Instrum Inc., Dallas, TX, USA
Burch , Texas Instrum Inc., Dallas, TX, USA
Najm , Texas Instrum Inc., Dallas, TX, USA
Yang , Texas Instrum Inc., Dallas, TX, USA
pp. 294-299

Improved methods of simulating RLC coupled and uncoupled transmission lines based on the method of characteristics (PDF)

Abraham , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Gura , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 300-305

Performance of a new annealing schedule (PDF)

Lam , Yale Univ., New Haven, CT, USA
Delosme , Yale Univ., New Haven, CT, USA
pp. 306-311

Clustering based simulated annealing for standard cell placement (PDF)

Grover , AT&T Bell Lab., Murray Hill, NJ, USA
Mallela , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 312-317

High-level synthesis: current status and future directions (PDF)

Borriello , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
pp. 477-482

HERCULES-a system for high-level synthesis (PDF)

Ku , Comput. Syst. Lab., Stanford Univ., CA, USA
de Micheli , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 483-488

Design process model in the Yorktown silicon compiler (PDF)

Camposano , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 489-494

For incremental circuit analysis using extracted hierarchy (PDF)

Beatty , Carnegie-Mellon Univ., Pittsburgh, PA, USA
Bryant , Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 495-500

Incremental-in-time algorithm for digital simulation (PDF)

Hwang , Stanford Univ., CA, USA
Choi , Stanford Univ., CA, USA
Blank , Stanford Univ., CA, USA
pp. 501-505

A dynamically-directed switch model for MOS logic simulation (PDF)

Adler , Silicon Compiler Syst., Liberty Corner, NJ, USA
pp. 506-511

A circuit comparison system with rule-based functional isomorphism checking (PDF)

Takashima , Toshiba Corp., Kawasaki, Japan
Ikeuchi , Toshiba Corp., Kawasaki, Japan
pp. 512-516

A PROLOG-based connectivity verification tool (PDF)

Papaspyridis , Dept. of Electr. Eng., Imperial Coll., London, UK
pp. 523-527

CORAL II: linking behavior and structure in an IC design system (PDF)

Thomas , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
Koenig , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
Blackburn , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 529-535

Splicer: a heuristic approach to connectivity binding (PDF)

Pangrle , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 536-541

Module selection for pipelined synthesis (PDF)

Jain , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Parker , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 542-547

The use of Petri nets for modeling pipelined processors (PDF)

Razouk , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 548-553

Fast algorithm for optimal layer assignment (PDF)

Kuo , Inst. of Inf. Sci., Acad. Sinica, China
Chern , Inst. of Inf. Sci., Acad. Sinica, China
Shih , Inst. of Inf. Sci., Acad. Sinica, China
pp. 554-559

Connectivity biased channel construction and ordering for building-block layout (PDF)

Cai , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 560-565

A new approach to the pin assignment problem (PDF)

Liu , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Yao , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Yamada , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 566-572

The constrained via minimization problem for PCB and VLSI design (PDF)

Kuh , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Xiong , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 573-578

Micro-operation perturbations in chip level fault modeling (PDF)

Chao , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Gray , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 579-582

A new two task algorithm for clock mode fault simulation in sequential circuits (PDF)

Hill , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Shen , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Huang , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Abuelyamen , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
pp. 583-586

Switch level random pattern testability analysis (PDF)

Cirit , Silicon Compiler Syst., Liberty Corner, NJ, USA
pp. 587-590

DYTEST: a self-learning algorithm using dynamic testability measures to accelerate test generation (PDF)

Mao , Dept. of Electr. Eng., Colarado Univ., Colorado Springs, CO, USA
Ciletti , Dept. of Electr. Eng., Colarado Univ., Colorado Springs, CO, USA
pp. 591-596

CATAPULT: concurrent automatic testing allowing parallelization and using limited topology (PDF)

Mercer , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Butler , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Gaede , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 597-600

A graph compaction approach to fault simulation (PDF)

Harel , Tektronix Inc., Beaverton, OR, USA
Krishnamurthy , Tektronix Inc., Beaverton, OR, USA
pp. 601-604

Automatic functional test program generation for microprocessors (PDF)

Ho , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Lin , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 605-608

Spare allocation and reconfiguration in large area VLSI (PDF)

Kuo , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Fuchs , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 609-612

The architecture of a highly integrated simulation system (PDF)

Dure , Eur. Silicon Structures, Sevres, France
Heydemann , Eur. Silicon Structures, Sevres, France
Plaignaud , Eur. Silicon Structures, Sevres, France
pp. 617-621

Constraint propagation in an object-orientated IC design environment (PDF)

Girczyc , Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
Ly , Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
pp. 628-633

Design automation for the component parts industry (PDF)

Chang , Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
pp. 634-637

Automatic building of graphs for rectangular dualisation (IC floorplanning) (PDF)

Jabri , Sch. of Electr. Eng., Sydney Univ., NSW, Australia
pp. 638-641

Automatic layout procedures for serial routing devices (PDF)

Terai , Hitachi Ltd., Tokyo, Japan
Ogawa , Hitachi Ltd., Tokyo, Japan
Kozawa , Hitachi Ltd., Tokyo, Japan
pp. 645

A digital-serial silicon compiler (PDF)

Hartley , Gen. Electr. Res. & Dev. Center, Schenectady, NY, USA
Corbett , Gen. Electr. Res. & Dev. Center, Schenectady, NY, USA
pp. 646-649

DECOMPOSER: a synthesizer for systolic systems (PDF)

Hou , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
Owens , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
Irwin , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
pp. 650-653

SMART: tools and methods for synthesis of VLSI chips with processor architecture (PDF)

Gessner , Siemens AG, Munich, West Germany
Wallstab , Siemens AG, Munich, West Germany
Bergstraesser , Siemens AG, Munich, West Germany
Hafner , Siemens AG, Munich, West Germany
pp. 654-657

Routing algorithm for gate array macro cells (PDF)

Chakraverti , Renssalaer Polytech. Inst., Troy, NY, USA
pp. 658-662

How to obtain more compactable channel routing solutions (PDF)

Cong , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 663-666

A channelless, multilayer router (PDF)

Lunow , Lawrence Livermore Nat. Lab., CA, USA
pp. 667-671

An interactive maze router with hints (PDF)

Scott , Lawrence Livermore Nat. Lab., California Univ., CA, USA
Arnold , Lawrence Livermore Nat. Lab., California Univ., CA, USA
pp. 672-676

Improved channel routing by via minimization and shifting (PDF)

Cheng , Bellcore, Morristown, NJ, USA
Deutsch , Bellcore, Morristown, NJ, USA
pp. 677-680

The min-cut shuffle: toward a solution for the global effect problem of min-cut placement (PDF)

Bhandari , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
Slewiorek , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
Hirsch , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 681-685

Fault simulation in a distributed environment (PDF)

Roy , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Duba , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abraham , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 686-691

The performance of the concurrent fault simulation algorithms in MOZART (PDF)

Gai , Politecnico di Torino, Italy
Montessoro , Politecnico di Torino, Italy
pp. 692-697

An approach to fast hierarchical fault simulation (PDF)

Motohara , Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
pp. 698-703

Why partial design verification works better than it should (PDF)

Savir , IBM Corp., Poughkeepsie, NY, USA
pp. 704-707

Advances in functional abstraction from structure (PDF)

Hall , Artificial Intelligence Lab., MIT, Cambrdige, MA, USA
Lathrop , Artificial Intelligence Lab., MIT, Cambrdige, MA, USA
pp. 708-711

Hardware logic simulation by compilation (PDF)

Hansen , MIPS Comput. Syst. Inc., Sunnyvale, CA, USA
pp. 712-715

Clock event suppression algorithm of VELVET and its application to S-820 development (PDF)

Takamine , Hitachi Ltd., Tokyo, Japan
Miyamoto , Hitachi Ltd., Tokyo, Japan
Nagashima , Hitachi Ltd., Tokyo, Japan
pp. 716-719

A path selection algorithm for timing analysis (PDF)

Ghanta , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Du , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Yen , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 720-723

Algorithms for timing requirement analysis and generation (PDF)

Sherman , Digital Equipment Corp., Maynard, MA, USA
pp. 724-727
96 ms
(Ver )