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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 716-719
Takamine , Hitachi Ltd., Tokyo, Japan
Miyamoto , Hitachi Ltd., Tokyo, Japan
Nagashima , Hitachi Ltd., Tokyo, Japan
ABSTRACT
An advanced clock event suppression algorithm for high-speed logic simulation is described. A signal value, Cn, and a current clock (CC), which indicates the current status of clock signals, has been introduced to realize this algorithm. This algorithm suppresses about 60% of the total events, and eliminates 40% of CPU time. No overhead is needed to incorporate this algorithm using hardware support of VELVET (vectorized processing system for logic verification). Hitachi's latest supercomputer S-820 has been developed using VELVET. The development period has been shortened to 3/4 that of the S-810.
INDEX TERMS
Hitachi, VELVET, S-820 development, clock event suppression algorithm, high-speed logic simulation, vectorized processing system, logic verification, supercomputer
CITATION

Takamine, Miyamoto, Miyoshi, Nagashima and Kawabe, "Clock event suppression algorithm of VELVET and its application to S-820 development," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 716-719.
doi:10.1109/DAC.1988.14849
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