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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 698-703
Motohara , Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
ABSTRACT
The authors present an approach to hierarchical fault simulation which generates several simulation models of one circuit and carries out simulation for each. Fault insertion and simulation-model generation is done automatically. Switch-level simulation which utilizes lookup tables is as fast as gate-level simulation. Experimental results show that using behavioral description and switch-level truth tables is effective in improving simulation speed.
INDEX TERMS
fault insertion, logic design environment, hierarchical fault simulation, simulation-model generation, lookup tables, behavioral description, switch-level truth tables
CITATION

Urano, Masuda, Motohara, Sugano and Murakami, "An approach to fast hierarchical fault simulation," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 698-703.
doi:10.1109/DAC.1988.14845
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