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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 646-649
Hartley , Gen. Electr. Res. & Dev. Center, Schenectady, NY, USA
Corbett , Gen. Electr. Res. & Dev. Center, Schenectady, NY, USA
ABSTRACT
A novel silicon compiler is described, called PARSIFAL. It constructs chips with a data-flow architecture in which data is passed in a digit-wide pipeline form one computational element to the next. The size of a digit can be specified by the user to be any value between one and the full word size of the chip. A digit size of one gives bit-serial chips, whereas a digit-size equal to the word-size gives fully parallel computation. It is shown that an intermediate value of the digit-size usually gives the most efficient chips in terms of throughput per unit area.
INDEX TERMS
CAD, layout design, logic design, digital-serial silicon compiler, PARSIFAL, data-flow architecture, digit-wide pipeline, bit-serial chips, fully parallel computation
CITATION

Hartley and Corbett, "A digital-serial silicon compiler," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 646-649.
doi:10.1109/DAC.1988.14834
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