Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
A method for efficient complication of circuits which is used in a commercially available fault grader is described. Data structures and algorithms are presented which can be used in processing circuits in a textural or schematic format. Performance is documented by showing the results for various circuits. It is shown that on the average, the compiler can process 2000 lines of CDL text per minute, and the loader and flattener process 10300 flattened nets per minute. These times show that incremental circuit changes can be performed in analysis tools without using a separate complication procedure. This efficiency is possible by creating data structures which require minimal manipulation and by the organization of data in the circuit library. Memory utilization is kept to a minimum by optimizing the location of circuit information on the data structures.
circuit compilers, textural format, CDLCON, Caedent, hierarchical design language, fault grader, schematic format, CDL text, incremental circuit changes, data structures
Diss, "Circuit compilers don't have to be slow," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 622-627.