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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 601-604
Harel , Tektronix Inc., Beaverton, OR, USA
Krishnamurthy , Tektronix Inc., Beaverton, OR, USA
ABSTRACT
The authors describe a graph-compaction-based algorithm for fault simulation in combination circuits. The algorithm consists of reducing the circuit graph by repeatedly removing nonreconvergent vertices. The algorithm has been implemented in Smalltalk and preliminary experimental results are presented. A version of the algorithm outperforms all known fault simulation algorithms on a family of hard circuits.
INDEX TERMS
logic testing, graph compaction, fault simulation, combination circuits, nonreconvergent vertices, Smalltalk
CITATION

Harel and Krishnamurthy, "A graph compaction approach to fault simulation," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 601-604.
doi:10.1109/DAC.1988.14824
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