Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
Gaede , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Mercer , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Butler , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
An improved algorithm is presented for identifying redundant faults and finding tests for hard faults in combination circuits. A concurrent approach is proposed which is based on the concepts of functional decomposition, explicit representation of fanout stems, and the Boolean difference. The data structure used is the binary decision diagram. The algorithm operates as a back end to test generators which use random patterns or heuristics or a combination of the two.
test generator back end, logic testing, CATAPULT, concurrent automatic testing, hard faults, combination circuits, functional decomposition, explicit representation, fanout stems, Boolean difference, data structure, binary decision diagram
Ross, Mercer, Butler and Gaede, "CATAPULT: concurrent automatic testing allowing parallelization and using limited topology," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 597-600.